EP1547156A1 - Finfet having improved carrier mobility and method of its formation - Google Patents

Finfet having improved carrier mobility and method of its formation

Info

Publication number
EP1547156A1
EP1547156A1 EP03799284A EP03799284A EP1547156A1 EP 1547156 A1 EP1547156 A1 EP 1547156A1 EP 03799284 A EP03799284 A EP 03799284A EP 03799284 A EP03799284 A EP 03799284A EP 1547156 A1 EP1547156 A1 EP 1547156A1
Authority
EP
European Patent Office
Prior art keywords
layer
silicon
channel region
finfet
finfet body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP03799284A
Other languages
German (de)
French (fr)
Other versions
EP1547156B1 (en
Inventor
Ming-Ren Lin
Jung-Suk Goo
Haihong Wang
Qi Xiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP1547156A1 publication Critical patent/EP1547156A1/en
Application granted granted Critical
Publication of EP1547156B1 publication Critical patent/EP1547156B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure

Definitions

  • the invention pertains to semiconductor devices, and more particularly to vertical double gate MOSFETs, also known as FinFETs. 2. Related Technology
  • MOSFETs Metal oxide semiconductor field effect transistors
  • the conventional MOSFET is constructed from a semiconductor substrate in which dopant-implanted active regions are formed. As a result, the active components of the MOSFET are surrounded by semiconductor material.
  • channel lengths are reduced to less than 100 nm, the use of semiconductor substrate construction in MOSFETs creates performance degrading phenomena such as short channel effect.
  • the short channel effect degrades the ability of the MOSFET gate to control conductivity in the MOSFET channel region due to interactions of the source and drain regions that occur as a result of the semiconductor materials of the semiconductor substrate that surround the active regions.
  • SOI construction An alternative to the conventional semiconductor substrate construction is silicon on insulator (SOI) construction.
  • SOI construction devices such as MOSFETS are formed as monolithic semiconductor structures supported on a dielectric substrate, rather than as regions formed within a semiconductor substrate.
  • SOI devices have been found to have a number of advantages over devices formed using semiconductor substrate construction, such as better isolation between devices, reduced leakage current, reduced latch-up between CMOS elements, reduced chip capacitance, and reduction or elimination of short channel coupling between source and drain regions.
  • the FinFET is constructed from a silicon body that includes a source region 12, a drain region 14 and a fin-shaped channel region 16.
  • the source 12, drain 14 and channel 16 regions are formed of a monolithic silicon body that is patterned from a silicon layer provided on a dielectric substrate 18.
  • a gate oxide is grown or deposited over the silicon body, and then a conductive gate 20 as shown in Figure lb is patterned so as to surround the channel region 16.
  • the gate 20 is patterned from a conductive material such as polysilicon.
  • Figure 2 shows a view of a cross-section of the gate and channel region of the FinFET of Figure lb taken at line A-A' .
  • the gate 20 and channel region 16 are separated by the gate oxide 22, and the gate 20 surrounds the channel region 16 on both of its sidewalk, thus serving as a double gate that imparts gate voltage to both sides of the channel region 16.
  • the channel width of a FinFET is therefore approximately double the height of the channel region fin, enabling a high driving current compared to semiconductor substrate MOSFETs of comparable size.
  • a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer.
  • An epitaxial layer of strained silicon is then formed on the Silicon germanium FinFET body.
  • a tensile strain is imparted to the epitaxial silicon as a result of differences in the dimensionalities of a relaxed intrinsic silicon lattice and the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown.
  • Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET body.
  • a higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.
  • a silicon on insulator MOSFET device comprises a substrate comprising a dielectric layer.
  • a FinFET body is formed on the dielectric layer.
  • the FinFET body is typically silicon germanium.
  • the FinFET body includes source and drain regions that have a channel region extending therebetween.
  • a layer of strained silicon is formed on the surfaces of at least the channel region.
  • a gate insulating layer is formed over at least the channel region to cover the strained silicon formed on surfaces of the channel region.
  • a conductive gate surrounds the sidewalls and the top portion of the channel region and is separated from the channel region by the gate insulating layer and the strained silicon.
  • a silicon on insulator MOSFET device is formed by initially providing a SOI substrate that includes a semiconductor layer overlying a dielectric layer.
  • the semiconductor layer is typically silicon germanium.
  • the semiconductor layer is patterned to form a FinFET body that includes source and drain regions and a channel region extending therebetween.
  • a layer of strained silicon is then formed on the surfaces of at least the channel region.
  • a gate insulating layer is formed over at least the strained silicon grown on the channel region to cover the strained silicon grown on the channel region.
  • a conductive gate is then formed.
  • the conductive gate surrounds sidewalls and a top portion of the channel region and is separated from the channel region by the gate insulating layer and the strained silicon.
  • multiple FinFETs as described above may be combined to form CMOS devices, and FinFET bodies may be formed to have multiple channel regions to thereby provide greater channel width.
  • Figure la shows a body portion of a conventional FinFET
  • Figure lb shows a gate portion formed over the body portion of the conventional FinFET of Figure la;
  • Figure 2 shows a cross section of a conventional FinFET gate and channel taken along line A-A' of Figure la;
  • Figure 3 shows a cross section of a FinFET gate and channel of a FinFET formed in accordance with an embodiment of the present invention
  • Figure 4a shows a substrate and mask for forming a FinFET in accordance with an embodiment of the invention
  • Figure 4b shows the structure of Figure 4a after etching of the substrate to form a FinFET body
  • Figure 4c shows the structure of Figure 4b after formation of a gate
  • Figure 5a shows the implantation of oxygen into a silicon germanium substrate
  • Figure 5b shows the structure of Figure 5a after annealing to form a buried oxide (BOX) layer of a silicon germanium SOI substrate
  • Figure 5c shows the structure of Figure 5b after patterning of a FinFET body from a silicon germanium layer;
  • BOX buried oxide
  • Figure 6a shows the implantation of hydrogen into a silicon germanium substrate
  • Figure 6b shows the structure of Figure 6a after being inverted and bonded to an oxide layer of a second substrate
  • Figure 6c shows the structure of Figure 6b after annealing to fracture the first substrate in the region of implanted hydrogen
  • Figure 6d shows the structure of Figure 6c after planarization to yield a silicon germanium SOI substrate
  • Figure 7 shows a process flow encompassing the preferred embodiment and alternative embodiments.
  • FIG. 3 A cross section of a gate and a channel region of a FinFET formed in accordance with an embodiment of the present invention is shown in Figure 3.
  • the structure comprises a silicon germanium channel region 32 on which is grown an epitaxial layer of strained silicon 34.
  • the silicon germanium lattice of the silicon germanium channel region 32 is generally more widely spaced than an intrinsic silicon lattice as a result of the presence of the larger germanium atoms in the lattice. Because the atoms of the silicon lattice align with the more widely spread silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another.
  • the amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the silicon germanium lattice.
  • the epitaxial silicon layer 34 grown on the silicon germanium channel region 32 is subjected to a tensile strain.
  • the application of tensile strain to the silicon lattice causes four of its six silicon valence bands to increase in energy and two of its valence bands to decrease in energy.
  • electrons effectively weigh 30 percent less when passing through the lower energy bands of strained silicon.
  • the lower energy bands offer less resistance to electron flow.
  • electrons encounter less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon.
  • carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, offering a potential increase in mobility of 80% or more for electrons and 20% or more for holes.
  • the increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter.
  • a gate insulating layer 36 is formed over the strained silicon layer 34, and a double gate structure 38 is formed around the channel portion 32 overlying the gate insulating layer 36.
  • the structure shown in Figure 3 forms part of a FinFET that exhibits enhanced carrier mobility as the result of the strained silicon layer provided at the surface of the channel region as well as the source and drain regions.
  • the aspect ratio of the cross section of the channel portion is probably as high as possible so as to form a tall, narrow channel region that is fully depleted and provides a maximum effective channel width.
  • Figure 4a shows a SOI substrate including a dielectric layer 40 and a relaxed silicon germanium layer 42.
  • the silicon germanium layer 42 preferably has a composition Si ⁇ Ge, . , where x is approximately .2, and is more generally in the range of .1 - .3.
  • a mask 44 is formed on the silicon germanium layer 42 for etching the silicon germanium layer 42.
  • the mask is preferentially a hardmask formed by etching of a bi-layer structure using a photoresist mask of similar shape as an etch mask.
  • Figure 4b shows the structure of Figure 4a after etching using the mask 44 as an etch mask to remove unmasked silicon germanium and to thereby form a silicon germanium FinFET body 46.
  • An epitaxial strained silicon layer is then formed by selective growth on the silicon germanium
  • the strained silicon layer is preferably grown by chemical vapor deposition (CVD) using Si 2 H 6 as a source gas with a partial pressure of 30mPa and a substrate temperature of approximately 600 - 900 degrees C.
  • the epitaxial silicon layer is strained upon its formation as the result of forces within the silicon lattice created as the result of alignment of the silicon atoms through bonding to corresponding atoms of the silicon germanium lattice.
  • the epitaxial strained silicon has a thickness of 100 - 200 Angstroms.
  • a gate insulating layer of silicon oxide is formed over the layer of strained silicon.
  • the silicon oxide may be formed by deposition or may be selectively grown from the strained silicon layer.
  • the final thickness of the strained silicon layer is preferably approximately 80 - 200 A. Therefore, the amount of strained silicon that is initially grown will be determined in part based on whether some of the strained silicon will be consumed during oxide growth.
  • a gate 48 is formed, yielding the structure illustrated in Figure 4c.
  • the gate is preferably formed by deposition of a conformal layer of polysilicon over the substrate including the silicon germanium FinFET body 46, followed by planarization of the polysilicon layer and then patterning using an etch mask to define a gate 48 as shown in Figure 4c.
  • a pair of FinFETs that are doped with respective complementary dopants may have gates that are electrically connected to thereby constitute a CMOS FinFET.
  • the source and drain regions of the FinFET may be connected by multiple channel regions that extend between them, thus providing greater surface area contact between the channel regions and the gate and have greater channel width.
  • the silicon germanium SOI substrate may be provided in a variety of manners.
  • Figures 5a, 5b and 5c show structures formed using implanted oxygen to form a buried oxide (BOX) layer in a silicon germanium substrate.
  • a silicon germanium substrate 50 is provided.
  • the substrate typically comprises a layer of silicon germanium grown on a silicon wafer.
  • Silicon germanium may be grown, for example, by chemical vapor deposition using disilane (Si 2 H 6 ) and germane (GeH 4 ) as source gases, with a substrate temperature of 600 - 90 degrees C, a Si 2 H 6 partial pressure of 30 mPa, and a GeH partial pressure of 60 mPa.
  • the partial pressure of GeH t may be gradually increased beginning from a lower pressure or zero pressure to form a gradient composition.
  • the thickness of the silicon germanium layer may be determined in accordance with the particular application.
  • the portion of the silicon germanium layer to be used for forming the FinFET body should have a uniform composition.
  • the silicon germanium substrate 50 is implanted with oxygen 52 at an energy sufficient to form an oxygenated region 54 at such a depth to leave a required thickness of silicon germanium above the oxygenated region.
  • Figure 5b shows the structure of Figure 5a after annealing of the silicon germanium substrate 50 to form a buried silicon germanium oxide layer 56 within the substrate. Annealing is typically performed at approximately 1350 degrees C for approximately four hours, and typically serves to relax any residual strain in the silicon germanium lattice.
  • the oxide layer 56 serves as the dielectric layer on which monolithic FinFET bodies are later formed, as described above.
  • Figure 5c shows the structure of Figure 5b after patterning a silicon germanium FinFET body 58 (shown in cross section at the channel region) from the silicon germanium layer that overlies the oxide layer 56.
  • Figures 6a - 6d shows structures formed in accordance with a second method for forming a silicon germanium SOI substrate.
  • Figure 6a shows a planarized silicon germanium substrate 60.
  • the substrate 60 is implanted with hydrogen 62 to fo ⁇ n a hydrogen rich region 64 within the silicon germanium material.
  • the hydrogen 62 is implanted with an energy such that the amount of silicon germanium remaining above the hydrogen rich region exceeds the thickness of the silicon germanium layer to be formed on the SOI substrate.
  • FIG. 6b shows the silicon germanium substrate of Figure 6a after being cleaned, stripped of oxide in a diluted HF solution, rinsed in deionized water to form an active native oxide on its surface, and then inverted and bonded to a planarized oxide layer 72 formed on a semiconductor layer 74 of second substrate 70.
  • Bonding may be performed at room temperature, and requires precise planarization of both substrates to provide maximum surface contact for optimal bonding. After bonding, the bonded substrates are annealed, for example at a temperature of 600 degrees C for approximately three hours.
  • annealing causes the silicon germanium substrate to fracture along the hydrogen rich region 64, thus leaving a new substrate comprising a silicon germanium layer 76 bonded to an oxide layer 72, and having a residual hydrogen rich region 64 at its upper surface.
  • the new substrate is subsequently planarized and cleaned, leaving a silicon germanium SOI substrate as shown in Figure 6d, from which a silicon germanium FinFET body may be patterned as described previously.
  • Figure 7 illustrates a process flow encompassing the preferred embodiment, the aforementioned alternatives and various other alternatives for forming a SOI MOSFET device.
  • a SOI substrate is provided (80).
  • the SOI substrate comprises a semiconductor layer that overlies a dielectric layer.
  • the semiconductor layer is preferably silicon germanium and the dielectric layer is preferably silicon germanium oxide or silicon oxide.
  • the semiconductor layer is then patterned to form a FinFET body comprising source and drain regions having a channel region extending therebetween (82).
  • a layer of strained silicon is then formed on surfaces of at least the channel region (84), although the layer of strained silicon may additionally be formed over the surfaces of the entire FinFET body.
  • a gate insulating layer is formed over at least the strained silicon grown on the channel region of the FinFET body to cover the strained silicon grown on the channel region (86).
  • the gate insulating layer may be an oxide grown from the strained silicon or may be deposited over the strained silicon.
  • a conductive gate is then formed (88). The gate surrounds sidewalls and a top portion of the channel region and is separated from the channel region by the gate insulating layer and the strained silicon layer.
  • CMOS devices devices having multiple channel regions, and devices employing varying material compositions and material layer structures.
  • FinFET structures incorporating strained silicon as described herein may also be formed by alternative methods, such as growth of a silicon germanium layer on a semiconductor FinFET body, or implantation of germanium into a silicon FinFET body, followed by growth of strained silicon on the silicon germanium lattice at the surface of the FinFET body.
  • the strained silicon may be formed by implantation of carbon into the surface of a silicon FinFET body. Therefore, strained silicon FinFETs in accordance with the invention may be generally characterized as comprising a layer of strained silicon formed on at least the channel region of a FinFET body.
  • the FinFET body comprises a layer of silicon germanium at the surface of at least its channel region.
  • the strain in a semiconductor layer may be enhanced by implanting germanium into the supporting oxide layer to expand the oxide layer.
  • a high k material having a lattice spacing to that of silicon germanium may be used as the gate insulating layer to provide additional support for the strain in the strained silicon layer.
  • intermediate processing tasks such as formation and removal of passivation layers or protective layers between processing tasks, formation and removal of photoresist masks and other masking layers, doping and counter-doping, cleaning, planarization, and other tasks, may be performed along with the tasks specifically described above.
  • the process need not be performed on an entire substrate such as an entire wafer, but rather may be performed selectively on sections of the substrate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)

Abstract

A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body (46) is patterned from a layer of silicon germanium (SiGe) (42) that overlies a dielectric layer (40). An epitaxial layer of silicon (34) is then formed on the silicon germanium FinFET body (46). A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

Description

FINFET HAVING IMPROVED CARRIER MOBILITY AND METHOD OF ITS FORMATION
BACKGROUND OF THE INVENTION 1. Field of the Invention
The invention pertains to semiconductor devices, and more particularly to vertical double gate MOSFETs, also known as FinFETs. 2. Related Technology
Metal oxide semiconductor field effect transistors (MOSFETs) are the primary component of most semiconductor devices. The conventional MOSFET is constructed from a semiconductor substrate in which dopant-implanted active regions are formed. As a result, the active components of the MOSFET are surrounded by semiconductor material. However, as channel lengths are reduced to less than 100 nm, the use of semiconductor substrate construction in MOSFETs creates performance degrading phenomena such as short channel effect. The short channel effect degrades the ability of the MOSFET gate to control conductivity in the MOSFET channel region due to interactions of the source and drain regions that occur as a result of the semiconductor materials of the semiconductor substrate that surround the active regions.
An alternative to the conventional semiconductor substrate construction is silicon on insulator (SOI) construction. In SOI construction, devices such as MOSFETS are formed as monolithic semiconductor structures supported on a dielectric substrate, rather than as regions formed within a semiconductor substrate. SOI devices have been found to have a number of advantages over devices formed using semiconductor substrate construction, such as better isolation between devices, reduced leakage current, reduced latch-up between CMOS elements, reduced chip capacitance, and reduction or elimination of short channel coupling between source and drain regions.
One type of MOSFET structure that is formed using SOI construction is conventionally known as a vertical double-gate MOSFET, or a FinFET. As shown in Figure la, the FinFET is constructed from a silicon body that includes a source region 12, a drain region 14 and a fin-shaped channel region 16. The source 12, drain 14 and channel 16 regions are formed of a monolithic silicon body that is patterned from a silicon layer provided on a dielectric substrate 18. After patterning the silicon body, a gate oxide is grown or deposited over the silicon body, and then a conductive gate 20 as shown in Figure lb is patterned so as to surround the channel region 16. The gate 20 is patterned from a conductive material such as polysilicon. Figure 2 shows a view of a cross-section of the gate and channel region of the FinFET of Figure lb taken at line A-A' . As seen in Figure 2, the gate 20 and channel region 16 are separated by the gate oxide 22, and the gate 20 surrounds the channel region 16 on both of its sidewalk, thus serving as a double gate that imparts gate voltage to both sides of the channel region 16. The channel width of a FinFET is therefore approximately double the height of the channel region fin, enabling a high driving current compared to semiconductor substrate MOSFETs of comparable size.
While the conventional FinFET provides the aforementioned advantages over MOSFETs formed on semiconductor substrates due to its SOI construction, some fundamental characteristics of the FinFET such as carrier mobility are the same as those of other MOSFETs because the FinFET source, drain and channel regions are typically made from conventional MOSFET semiconductor materials such as silicon. SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a FinFET device that improves over conventional FinFETs by enhancing characteristics of the device such as carrier mobility. In accordance with embodiments of the invention, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of strained silicon is then formed on the Silicon germanium FinFET body. A tensile strain is imparted to the epitaxial silicon as a result of differences in the dimensionalities of a relaxed intrinsic silicon lattice and the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET body. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.
In accordance with one embodiment of the invention, a silicon on insulator MOSFET device comprises a substrate comprising a dielectric layer. A FinFET body is formed on the dielectric layer. The FinFET body is typically silicon germanium. The FinFET body includes source and drain regions that have a channel region extending therebetween. A layer of strained silicon is formed on the surfaces of at least the channel region. A gate insulating layer is formed over at least the channel region to cover the strained silicon formed on surfaces of the channel region. A conductive gate surrounds the sidewalls and the top portion of the channel region and is separated from the channel region by the gate insulating layer and the strained silicon. In accordance with another embodiment of the invention, a silicon on insulator MOSFET device is formed by initially providing a SOI substrate that includes a semiconductor layer overlying a dielectric layer. The semiconductor layer is typically silicon germanium. The semiconductor layer is patterned to form a FinFET body that includes source and drain regions and a channel region extending therebetween. A layer of strained silicon is then formed on the surfaces of at least the channel region. A gate insulating layer is formed over at least the strained silicon grown on the channel region to cover the strained silicon grown on the channel region. A conductive gate is then formed. The conductive gate surrounds sidewalls and a top portion of the channel region and is separated from the channel region by the gate insulating layer and the strained silicon. In accordance with further alternatives, multiple FinFETs as described above may be combined to form CMOS devices, and FinFET bodies may be formed to have multiple channel regions to thereby provide greater channel width.
DESCRIPTION OF THE DRAWINGS
Embodiments of the invention are described in conjunction with the appended drawings, in which:
Figure la shows a body portion of a conventional FinFET; Figure lb shows a gate portion formed over the body portion of the conventional FinFET of Figure la;
Figure 2 shows a cross section of a conventional FinFET gate and channel taken along line A-A' of Figure la; Figure 3 shows a cross section of a FinFET gate and channel of a FinFET formed in accordance with an embodiment of the present invention;
Figure 4a shows a substrate and mask for forming a FinFET in accordance with an embodiment of the invention; Figure 4b shows the structure of Figure 4a after etching of the substrate to form a FinFET body;
Figure 4c shows the structure of Figure 4b after formation of a gate;
Figure 5a shows the implantation of oxygen into a silicon germanium substrate;
Figure 5b shows the structure of Figure 5a after annealing to form a buried oxide (BOX) layer of a silicon germanium SOI substrate; Figure 5c shows the structure of Figure 5b after patterning of a FinFET body from a silicon germanium layer;
Figure 6a shows the implantation of hydrogen into a silicon germanium substrate;
Figure 6b shows the structure of Figure 6a after being inverted and bonded to an oxide layer of a second substrate; Figure 6c shows the structure of Figure 6b after annealing to fracture the first substrate in the region of implanted hydrogen;
Figure 6d shows the structure of Figure 6c after planarization to yield a silicon germanium SOI substrate;
Figure 7 shows a process flow encompassing the preferred embodiment and alternative embodiments.
DESCRIPTION OF PREFERRED EMBODIMENTS
A cross section of a gate and a channel region of a FinFET formed in accordance with an embodiment of the present invention is shown in Figure 3. As seen in Figure 3, the structure comprises a silicon germanium channel region 32 on which is grown an epitaxial layer of strained silicon 34. The silicon germanium lattice of the silicon germanium channel region 32 is generally more widely spaced than an intrinsic silicon lattice as a result of the presence of the larger germanium atoms in the lattice. Because the atoms of the silicon lattice align with the more widely spread silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. The amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the silicon germanium lattice. As a result, the epitaxial silicon layer 34 grown on the silicon germanium channel region 32 is subjected to a tensile strain. The application of tensile strain to the silicon lattice causes four of its six silicon valence bands to increase in energy and two of its valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands of strained silicon. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons encounter less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, offering a potential increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
As further shown in Figure 3, a gate insulating layer 36 is formed over the strained silicon layer 34, and a double gate structure 38 is formed around the channel portion 32 overlying the gate insulating layer 36. Thus the structure shown in Figure 3 forms part of a FinFET that exhibits enhanced carrier mobility as the result of the strained silicon layer provided at the surface of the channel region as well as the source and drain regions. The aspect ratio of the cross section of the channel portion is probably as high as possible so as to form a tall, narrow channel region that is fully depleted and provides a maximum effective channel width.
A process for forming a FinFET in accordance with a preferred embodiment of the invention is now described with reference to Figures 4a-4c
Figure 4a shows a SOI substrate including a dielectric layer 40 and a relaxed silicon germanium layer 42. Various manners for producing such a substrate are discussed below. The silicon germanium layer 42 preferably has a composition Si^Ge,., where x is approximately .2, and is more generally in the range of .1 - .3. A mask 44 is formed on the silicon germanium layer 42 for etching the silicon germanium layer 42.
The mask is preferentially a hardmask formed by etching of a bi-layer structure using a photoresist mask of similar shape as an etch mask.
Figure 4b shows the structure of Figure 4a after etching using the mask 44 as an etch mask to remove unmasked silicon germanium and to thereby form a silicon germanium FinFET body 46. An epitaxial strained silicon layer is then formed by selective growth on the silicon germanium
FinFET body 46. The strained silicon layer is preferably grown by chemical vapor deposition (CVD) using Si2H6 as a source gas with a partial pressure of 30mPa and a substrate temperature of approximately 600 - 900 degrees C. The epitaxial silicon layer is strained upon its formation as the result of forces within the silicon lattice created as the result of alignment of the silicon atoms through bonding to corresponding atoms of the silicon germanium lattice. In preferred embodiments, the epitaxial strained silicon has a thickness of 100 - 200 Angstroms.
After growth of the strained silicon layer, a gate insulating layer of silicon oxide is formed over the layer of strained silicon. The silicon oxide may be formed by deposition or may be selectively grown from the strained silicon layer. The final thickness of the strained silicon layer is preferably approximately 80 - 200 A. Therefore, the amount of strained silicon that is initially grown will be determined in part based on whether some of the strained silicon will be consumed during oxide growth.
After formation of the gate insulating layer, a gate 48 is formed, yielding the structure illustrated in Figure 4c. The gate is preferably formed by deposition of a conformal layer of polysilicon over the substrate including the silicon germanium FinFET body 46, followed by planarization of the polysilicon layer and then patterning using an etch mask to define a gate 48 as shown in Figure 4c.
Following patterning of the gate 48, further processing may be performed such as formation of insulating spacers on sidewalls of the gate, implantation of dopant in the source and drain regions, formation of source, drain and gate suicides, and formation of a protective layer around the FinFET. While the process described with reference to Figures 4a - 4c concerns the formation of a single FinFET, it should be understood that a variety of alternative structures may be implemented using similar processing. For example, in one alternative implementation, a pair of FinFETs that are doped with respective complementary dopants may have gates that are electrically connected to thereby constitute a CMOS FinFET. In another alternative implementation, the source and drain regions of the FinFET may be connected by multiple channel regions that extend between them, thus providing greater surface area contact between the channel regions and the gate and have greater channel width.
The silicon germanium SOI substrate may be provided in a variety of manners. Figures 5a, 5b and 5c show structures formed using implanted oxygen to form a buried oxide (BOX) layer in a silicon germanium substrate. As shown in Figure 5a, a silicon germanium substrate 50 is provided. The substrate typically comprises a layer of silicon germanium grown on a silicon wafer. Silicon germanium may be grown, for example, by chemical vapor deposition using disilane (Si2H6) and germane (GeH4) as source gases, with a substrate temperature of 600 - 90 degrees C, a Si2H6 partial pressure of 30 mPa, and a GeH partial pressure of 60 mPa. Growth of the silicon germanium material may be initiated using these ratios, or alternatively the partial pressure of GeHt may be gradually increased beginning from a lower pressure or zero pressure to form a gradient composition. The thickness of the silicon germanium layer may be determined in accordance with the particular application. Preferably the portion of the silicon germanium layer to be used for forming the FinFET body should have a uniform composition.
As shown in Figure 5a, the silicon germanium substrate 50 is implanted with oxygen 52 at an energy sufficient to form an oxygenated region 54 at such a depth to leave a required thickness of silicon germanium above the oxygenated region.
Figure 5b shows the structure of Figure 5a after annealing of the silicon germanium substrate 50 to form a buried silicon germanium oxide layer 56 within the substrate. Annealing is typically performed at approximately 1350 degrees C for approximately four hours, and typically serves to relax any residual strain in the silicon germanium lattice. The oxide layer 56 serves as the dielectric layer on which monolithic FinFET bodies are later formed, as described above. Figure 5c shows the structure of Figure 5b after patterning a silicon germanium FinFET body 58 (shown in cross section at the channel region) from the silicon germanium layer that overlies the oxide layer 56.
Figures 6a - 6d shows structures formed in accordance with a second method for forming a silicon germanium SOI substrate. Figure 6a shows a planarized silicon germanium substrate 60. The substrate 60 is implanted with hydrogen 62 to foπn a hydrogen rich region 64 within the silicon germanium material. The hydrogen 62 is implanted with an energy such that the amount of silicon germanium remaining above the hydrogen rich region exceeds the thickness of the silicon germanium layer to be formed on the SOI substrate. It may be preferred to implant the hydrogen into a strained region of the silicon germanium Figure 6b shows the silicon germanium substrate of Figure 6a after being cleaned, stripped of oxide in a diluted HF solution, rinsed in deionized water to form an active native oxide on its surface, and then inverted and bonded to a planarized oxide layer 72 formed on a semiconductor layer 74 of second substrate 70. Bonding may be performed at room temperature, and requires precise planarization of both substrates to provide maximum surface contact for optimal bonding. After bonding, the bonded substrates are annealed, for example at a temperature of 600 degrees C for approximately three hours. As shown in Figure 6c, annealing causes the silicon germanium substrate to fracture along the hydrogen rich region 64, thus leaving a new substrate comprising a silicon germanium layer 76 bonded to an oxide layer 72, and having a residual hydrogen rich region 64 at its upper surface. The new substrate is subsequently planarized and cleaned, leaving a silicon germanium SOI substrate as shown in Figure 6d, from which a silicon germanium FinFET body may be patterned as described previously.
Figure 7 illustrates a process flow encompassing the preferred embodiment, the aforementioned alternatives and various other alternatives for forming a SOI MOSFET device. Initially a SOI substrate is provided (80). The SOI substrate comprises a semiconductor layer that overlies a dielectric layer. The semiconductor layer is preferably silicon germanium and the dielectric layer is preferably silicon germanium oxide or silicon oxide. The semiconductor layer is then patterned to form a FinFET body comprising source and drain regions having a channel region extending therebetween (82). A layer of strained silicon is then formed on surfaces of at least the channel region (84), although the layer of strained silicon may additionally be formed over the surfaces of the entire FinFET body. A gate insulating layer is formed over at least the strained silicon grown on the channel region of the FinFET body to cover the strained silicon grown on the channel region (86). The gate insulating layer may be an oxide grown from the strained silicon or may be deposited over the strained silicon. A conductive gate is then formed (88). The gate surrounds sidewalls and a top portion of the channel region and is separated from the channel region by the gate insulating layer and the strained silicon layer. As mentioned above, a variety of structural implementations may be formed using this process flow, including the single device shown in Figures 4a - 4c, as well as CMOS devices, devices having multiple channel regions, and devices employing varying material compositions and material layer structures.
In addition, FinFET structures incorporating strained silicon as described herein may also be formed by alternative methods, such as growth of a silicon germanium layer on a semiconductor FinFET body, or implantation of germanium into a silicon FinFET body, followed by growth of strained silicon on the silicon germanium lattice at the surface of the FinFET body. Further, the strained silicon may be formed by implantation of carbon into the surface of a silicon FinFET body. Therefore, strained silicon FinFETs in accordance with the invention may be generally characterized as comprising a layer of strained silicon formed on at least the channel region of a FinFET body. Typically the FinFET body comprises a layer of silicon germanium at the surface of at least its channel region.
In further alternatives, the strain in a semiconductor layer may be enhanced by implanting germanium into the supporting oxide layer to expand the oxide layer. In other alternatives, a high k material having a lattice spacing to that of silicon germanium may be used as the gate insulating layer to provide additional support for the strain in the strained silicon layer. It will be apparent to those having ordinary skill in the art that the tasks described in the above processes are not necessarily exclusive of other tasks, but rather that further tasks may be incorporated into the above processes in accordance with the particular structures to be formed. For example, intermediate processing tasks such as formation and removal of passivation layers or protective layers between processing tasks, formation and removal of photoresist masks and other masking layers, doping and counter-doping, cleaning, planarization, and other tasks, may be performed along with the tasks specifically described above. Further, the process need not be performed on an entire substrate such as an entire wafer, but rather may be performed selectively on sections of the substrate. Thus, while the embodiments illustrated in the figures and described above are presently preferred, it should be understood that these embodiments are offered by way of example only. The invention is not limited to a particular embodiment, but extends to various modifications, combinations, and permutations that fall within the scope of the claimed inventions and their equivalents.

Claims

What is claimed is:
1. A silicon on insulator (SOI) MOSFET device comprising: a substrate comprising a dielectric layer (40); a FinFET body formed (46) on the dielectric layer (40), the FinFET body (46) comprising source and drain regions having a channel region extending therebetween; a layer of strained silicon (34) formed on surfaces of at least the channel region of the FinFET body; a gate insulating layer (36) formed over at least the channel region to cover the strained silicon (34) formed on surfaces of the channel region; and a conductive gate (48) that surrounds sidewalls and a top portion of the channel region and that is separated from the channel region by the gate insulating layer and the strained silicon layer.
2. The device claimed in claim 1, wherein the FinFET body (46) is silicon germanium.
3. The device claimed in claim 1, wherein the FinFET body (46) comprises a first FinFET body, and wherein the device further comprises: a second FinFET body formed on the dielectric layer, the second FinFET body comprising second source and drain regions having a second channel region extending therebetween; a layer of strained silicon formed on surfaces of the second channel region; a gate insulating layer formed over at least the second channel region to cover the strained silicon formed on surfaces of the second channel region; and a second conductive gate that surrounds sidewalls and a top portion of the second channel region and that is separated from the second channel region by the gate insulating layer and the strained silicon layer, and that is electrically connected to the conductive gate surrounding the channel region of the first FinFET body, the source and drain of the first FinFET body being doped with a first dopant, and the source and drain of the second FinFET body being doped with a second dopant complementary to the first dopant.
4. The device claimed in claim 1, further comprising a spacer formed on sidewalls of the conductive gate.
5. A method for forming a silicon on insulator (SOI) MOSFET device comprising: providing a SOI substrate (40) comprising a semiconductor layer (42) overlying a dielectric layer; patterning the semiconductor layer (42) to form a FinFET body (46) comprising source and drain regions having a channel region extending therebetween; forming a layer of strained silicon (34) on surfaces of at least the channel region; forming a gate insulating layer (36) over at least the strained silicon (34) grown on the channel region to cover the strained silicon grown (34) on the channel region; and forming a conductive gate that surrounds sidewalls and a top portion of the channel region and is separated from the channel region by the gate insulating layer (36) and the strained silicon (34).
6. The method claimed in claim 5, wherein the semiconductor layer (42) is silicon germanium and the FinFET body (46) is silicon germanium.
7. The method claimed in claim 5, wherein the FinFET body (46) comprises a first FinFET body, and wherein the method further comprises: patterning the semiconductor layer to form a second FinFET body comprising second source and drain regions having a second channel region extending therebetween, concurrently with patterning of said first FinFET body; forming a layer of strained silicon on surfaces of at least the second channel region of the second
FinFET body, concurrently with growing a layer of strained silicon on said first FinFET body; forming a gate insulating layer over at least the strained silicon grown on the second channel region of said second FinFET body to cover the strained silicon grown on the second channel region, concurrently with forming a gate insulating layer over said first FinFET body; and forming a second conductive gate that surrounds sidewalls and a top portion of the second channel region and is separated from the second channel region by the gate insulating layer and the strained silicon, concurently with forming the conductive gate over the first FinFET body, wherein the conductive gate of the first FinFET body and the conductive gate of the second FinFET are electrically connected.
8. The method claimed in claim 5, wherein the FinFET body (46) has at least first and second channel regions extending between the source and drain regions.
9. The method claimed in claim 5, wherein providing a SOI substrate comprising a semiconductor layer overlying a dielectric layer comprises: providing a substrate comprising a silicon germanium layer; implanting oxygen into the silicon germanium layer; and annealing the substrate to form a buried silicon germanium oxide layer in the silicon germanium layer.
10. The method claimed in claim 5, wherein providing a SOI substrate comprising a semiconductor layer overlying a dielectric layer comprises: providing a first substrate comprising a silicon germanium layer; implanting hydrogen into the silicon germanium layer to form a hydrogen rich region in the silicon germanium layer; bonding the first substrate to an oxide layer of a second semiconductor substrate; annealing the bonded first and second substrates to fracture the first substrate in the hydrogen rich region; and removing the first substrate to yield the second substrate having a silicon germanium layer bonded to said oxide layer.
EP03799284A 2002-09-30 2003-09-12 Finfet having improved carrier mobility and method of its formation Expired - Lifetime EP1547156B1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US41522602P 2002-09-30 2002-09-30
US415226P 2002-09-30
US10/335,474 US6800910B2 (en) 2002-09-30 2002-12-31 FinFET device incorporating strained silicon in the channel region
US335474 2002-12-31
PCT/US2003/028660 WO2004032246A1 (en) 2002-09-30 2003-09-12 Finfet having improved carrier mobility and method of its formation

Publications (2)

Publication Number Publication Date
EP1547156A1 true EP1547156A1 (en) 2005-06-29
EP1547156B1 EP1547156B1 (en) 2010-12-15

Family

ID=32033323

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03799284A Expired - Lifetime EP1547156B1 (en) 2002-09-30 2003-09-12 Finfet having improved carrier mobility and method of its formation

Country Status (9)

Country Link
US (1) US6800910B2 (en)
EP (1) EP1547156B1 (en)
JP (1) JP2006501672A (en)
KR (1) KR101020811B1 (en)
CN (1) CN100524827C (en)
AU (1) AU2003266149A1 (en)
DE (1) DE60335391D1 (en)
TW (1) TWI364095B (en)
WO (1) WO2004032246A1 (en)

Families Citing this family (162)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6855990B2 (en) * 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US7091068B1 (en) * 2002-12-06 2006-08-15 Advanced Micro Devices, Inc. Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices
US6803631B2 (en) 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US7304336B2 (en) * 2003-02-13 2007-12-04 Massachusetts Institute Of Technology FinFET structure and method to make the same
US6855606B2 (en) * 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
KR100483425B1 (en) * 2003-03-17 2005-04-14 삼성전자주식회사 Semiconductor device and method for manufacturing the same
TWI231994B (en) * 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
US7074656B2 (en) * 2003-04-29 2006-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US6909186B2 (en) * 2003-05-01 2005-06-21 International Business Machines Corporation High performance FET devices and methods therefor
WO2004107452A1 (en) * 2003-05-30 2004-12-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing same
US7045401B2 (en) * 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7005330B2 (en) * 2003-06-27 2006-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for forming the gate electrode in a multiple-gate transistor
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6943405B2 (en) * 2003-07-01 2005-09-13 International Business Machines Corporation Integrated circuit having pairs of parallel complementary FinFETs
EP1519421A1 (en) 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum Vzw Multiple gate semiconductor device and method for forming same
US6921982B2 (en) * 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
EP1503424A3 (en) * 2003-07-25 2008-06-04 Interuniversitair Micro-Elektronica Centrum (IMEC) Multiple gate semiconductor device and method for forming same
US7078742B2 (en) * 2003-07-25 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel semiconductor structure and method of fabricating the same
JP2005051241A (en) * 2003-07-25 2005-02-24 Interuniv Micro Electronica Centrum Vzw Multilayer gate semiconductor device and manufacturing method therefor
US7301206B2 (en) * 2003-08-01 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US7355253B2 (en) * 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
US6970373B2 (en) * 2003-10-02 2005-11-29 Intel Corporation Method and apparatus for improving stability of a 6T CMOS SRAM cell
US6855588B1 (en) * 2003-10-07 2005-02-15 United Microelectronics Corp. Method of fabricating a double gate MOSFET device
US7888201B2 (en) * 2003-11-04 2011-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
KR100605497B1 (en) * 2003-11-27 2006-07-28 삼성전자주식회사 Methods of forming SOI substrates, methods of fabricating semiconductor devices using the same, and semiconductor devices fabricated using the same
US6924178B2 (en) * 2003-12-08 2005-08-02 International Business Machines Corporation Oxide/nitride stacked in FinFET spacer process
US7388258B2 (en) * 2003-12-10 2008-06-17 International Business Machines Corporation Sectional field effect devices
US7105390B2 (en) 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7247912B2 (en) * 2004-01-05 2007-07-24 International Business Machines Corporation Structures and methods for making strained MOSFETs
US7705345B2 (en) * 2004-01-07 2010-04-27 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US6936516B1 (en) * 2004-01-12 2005-08-30 Advanced Micro Devices, Inc. Replacement gate strained silicon finFET process
US7385247B2 (en) * 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
KR100781538B1 (en) * 2004-02-07 2007-12-03 삼성전자주식회사 Fabrication method for active structure of multi-gate transistor with improved performance and active structure and multi-gate transistor fabricated thereby
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
KR100625175B1 (en) * 2004-05-25 2006-09-20 삼성전자주식회사 Semiconductor device having a channel layer and method of manufacturing the same
US7452778B2 (en) * 2004-06-10 2008-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-wire devices and methods of fabrication
US7084461B2 (en) * 2004-06-11 2006-08-01 International Business Machines Corporation Back gate FinFET SRAM
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US6951784B1 (en) * 2004-08-05 2005-10-04 International Business Machines Corporation Three-mask method of constructing the final hard mask used for etching the silicon fins for FinFETs
US7348284B2 (en) * 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
KR100674914B1 (en) * 2004-09-25 2007-01-26 삼성전자주식회사 MOS transistor having strained channel layer and methods of manufacturing thereof
DE102005045078B4 (en) * 2004-09-25 2009-01-22 Samsung Electronics Co., Ltd., Suwon Field effect transistor with a strained channel layer on sidewalls of a structure on a semiconductor substrate
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US7611943B2 (en) * 2004-10-20 2009-11-03 Texas Instruments Incorporated Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
KR100652381B1 (en) * 2004-10-28 2006-12-01 삼성전자주식회사 Multi bridge channel field effect transistor comprising nano-wire channels and method of manufacturing the same
CN100392859C (en) * 2004-11-03 2008-06-04 中国科学院微电子研究所 Structure and preparation method of fish-shaped field effect transistor
JP2006135067A (en) * 2004-11-05 2006-05-25 Toshiba Corp Semiconductor device and manufacturing method thereof
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
KR100630723B1 (en) * 2004-12-06 2006-10-02 삼성전자주식회사 Semiconductor device having multibridge-channel and method of fabricating the same
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
CN100562987C (en) 2005-02-18 2009-11-25 富士通微电子株式会社 Memory cell array and manufacture method thereof and the semiconductor circuit arrangement that uses this memory cell array
JP4369379B2 (en) * 2005-02-18 2009-11-18 富士通マイクロエレクトロニクス株式会社 Semiconductor device
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
JP4367357B2 (en) * 2005-02-28 2009-11-18 セイコーエプソン株式会社 Manufacturing method of semiconductor device
US20060197129A1 (en) * 2005-03-03 2006-09-07 Triquint Semiconductor, Inc. Buried and bulk channel finFET and method of making the same
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8110863B2 (en) 2005-06-01 2012-02-07 Sandisk 3D Llc TFT charge storage memory cell having high-mobility corrugated channel
JP4648096B2 (en) * 2005-06-03 2011-03-09 株式会社東芝 Manufacturing method of semiconductor device
WO2006132172A1 (en) * 2005-06-07 2006-12-14 Nec Corporation Fin type field effect transistor, semiconductor device and production method thereof
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7902598B2 (en) 2005-06-24 2011-03-08 Micron Technology, Inc. Two-sided surround access transistor for a 4.5F2 DRAM cell
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7375394B2 (en) * 2005-07-06 2008-05-20 Applied Intellectual Properties Co., Ltd. Fringing field induced localized charge trapping memory
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7400031B2 (en) * 2005-09-19 2008-07-15 International Business Machines Corporation Asymmetrically stressed CMOS FinFET
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7947546B2 (en) * 2005-10-31 2011-05-24 Chartered Semiconductor Manufacturing, Ltd. Implant damage control by in-situ C doping during SiGe epitaxy for device applications
US7348638B2 (en) * 2005-11-14 2008-03-25 International Business Machines Corporation Rotational shear stress for charge carrier mobility modification
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7402856B2 (en) * 2005-12-09 2008-07-22 Intel Corporation Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same
US7439588B2 (en) * 2005-12-13 2008-10-21 Intel Corporation Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate
US7512017B2 (en) * 2005-12-21 2009-03-31 Intel Corporation Integration of planar and tri-gate devices on the same substrate
US7525160B2 (en) 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
US7396711B2 (en) 2005-12-27 2008-07-08 Intel Corporation Method of fabricating a multi-cornered film
US20070148926A1 (en) * 2005-12-28 2007-06-28 Intel Corporation Dual halo implant for improving short channel effect in three-dimensional tri-gate transistors
US20070152266A1 (en) * 2005-12-29 2007-07-05 Intel Corporation Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers
KR100719180B1 (en) * 2006-02-28 2007-05-17 주식회사 하이닉스반도체 Memory device with saddle type transistor and fin type transistor and method for manufacturing the same
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US20070235763A1 (en) * 2006-03-29 2007-10-11 Doyle Brian S Substrate band gap engineered multi-gate pMOS devices
US7449373B2 (en) 2006-03-31 2008-11-11 Intel Corporation Method of ion implanting for tri-gate devices
US7425500B2 (en) 2006-03-31 2008-09-16 Intel Corporation Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors
US7407847B2 (en) * 2006-03-31 2008-08-05 Intel Corporation Stacked multi-gate transistor design and method of fabrication
JP4552908B2 (en) * 2006-07-26 2010-09-29 エルピーダメモリ株式会社 Manufacturing method of semiconductor device
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
US7435683B2 (en) * 2006-09-15 2008-10-14 Intel Corporation Apparatus and method for selectively recessing spacers on multi-gate devices
US20080097346A1 (en) * 2006-09-19 2008-04-24 Alcon, Inc. Trocar cannula
US7700470B2 (en) 2006-09-22 2010-04-20 Intel Corporation Selective anisotropic wet etching of workfunction metal for semiconductor devices
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
WO2008039495A1 (en) 2006-09-27 2008-04-03 Amberwave Systems Corporation Tri-gate field-effect transistors formed by aspect ratio trapping
WO2008051503A2 (en) 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
US8368144B2 (en) 2006-12-18 2013-02-05 Infineon Technologies Ag Isolated multigate FET circuit blocks with different ground potentials
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
US7538391B2 (en) * 2007-01-09 2009-05-26 International Business Machines Corporation Curved FINFETs
US20080173942A1 (en) * 2007-01-22 2008-07-24 International Business Machines Corporation STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESSED SILICIDE
DE102007008562A1 (en) * 2007-02-21 2008-08-28 Qimonda Ag Field effect transistor arrangement
US7821061B2 (en) * 2007-03-29 2010-10-26 Intel Corporation Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
KR101361129B1 (en) * 2007-07-03 2014-02-13 삼성전자주식회사 luminous device and method of manufacturing the same
US8344242B2 (en) 2007-09-07 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-junction solar cells
US7671418B2 (en) * 2007-09-14 2010-03-02 Advanced Micro Devices, Inc. Double layer stress for multiple gate transistors
US8288756B2 (en) * 2007-11-30 2012-10-16 Advanced Micro Devices, Inc. Hetero-structured, inverted-T field effect transistor
EP2070533B1 (en) * 2007-12-11 2014-05-07 Apoteknos Para La Piel, s.l. Use of a compound derived from P-hydroxyphenyl propionic acid for the treatment of psoriasis
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
EP2335273A4 (en) 2008-09-19 2012-01-25 Taiwan Semiconductor Mfg Formation of devices by epitaxial layer overgrowth
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US20100155801A1 (en) * 2008-12-22 2010-06-24 Doyle Brian S Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application
US7999298B2 (en) * 2008-12-30 2011-08-16 Intel Corporation Embedded memory cell and method of manufacturing same
JP5705207B2 (en) 2009-04-02 2015-04-22 台湾積體電路製造股▲ふん▼有限公司Ｔａｉｗａｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｍｐａｎｙ，Ｌｔｄ． Device formed from non-polar surface of crystalline material and method of manufacturing the same
US8440517B2 (en) * 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8283653B2 (en) * 2009-12-23 2012-10-09 Intel Corporation Non-planar germanium quantum well devices
US8796759B2 (en) 2010-07-15 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
EP2477216A1 (en) * 2011-01-13 2012-07-18 Soitec Hybrid bulk/SOI device with a buried doped layer and manufacturing method thereof
US8852998B1 (en) * 2011-08-30 2014-10-07 Sandia Corporation Method to fabricate micro and nano diamond devices
US9040399B2 (en) 2011-10-27 2015-05-26 International Business Machines Corporation Threshold voltage adjustment for thin body MOSFETs
CN103137671B (en) * 2011-12-02 2015-06-24 中芯国际集成电路制造(上海)有限公司 Multi-grid field effect transistor and manufacturing method thereof
US8796695B2 (en) 2012-06-22 2014-08-05 United Microelectronics Corp. Multi-gate field-effect transistor and process thereof
US9947773B2 (en) 2012-08-24 2018-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor arrangement with substrate isolation
CN103219384B (en) * 2013-04-03 2015-05-20 北京大学 Anti-single particle radiation multi-grid device and preparation method thereof
CN104183488A (en) * 2013-05-21 2014-12-03 中芯国际集成电路制造(上海)有限公司 FinFET semiconductor device and manufacturing method thereof
US9000498B2 (en) * 2013-06-28 2015-04-07 Stmicroelectronics, Inc. FinFET with multiple concentration percentages
KR101462430B1 (en) * 2013-07-18 2014-11-18 경북대학교 산학협력단 Manufacturing methode of semiconductor device
KR102099193B1 (en) * 2013-09-27 2020-04-09 인텔 코포레이션 Forming led structures on silicon fins
EP3050091B1 (en) * 2013-09-27 2019-04-10 Intel Corporation Ge and iii-v channel semiconductor devices having maximized compliance and free surface relaxation
EP3050089A4 (en) * 2013-09-27 2017-05-03 Intel Corporation Non-planar semiconductor devices having multi-layered compliant substrates
US9391171B2 (en) 2014-01-24 2016-07-12 International Business Machines Corporation Fin field effect transistor including a strained epitaxial semiconductor shell
CN104022152B (en) * 2014-06-04 2017-03-01 重庆大学 Double grid p-channel MOSFET with compressive strain thin film strain source and preparation method
US9178068B1 (en) 2014-06-05 2015-11-03 International Business Machines Corporation FinFET with oxidation-induced stress
CN105280496B (en) 2014-06-05 2019-06-11 联华电子股份有限公司 Semiconductor element and preparation method thereof with fin structure
US9502565B2 (en) 2014-06-27 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Channel strain control for nonplanar compound semiconductor devices
US9306067B2 (en) 2014-08-05 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Nonplanar device and strain-generating channel dielectric
US9941406B2 (en) 2014-08-05 2018-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with source/drain cladding
CN105529241A (en) * 2014-09-29 2016-04-27 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and formation method thereof
KR102255174B1 (en) 2014-10-10 2021-05-24 삼성전자주식회사 Semiconductor device having active region and method of forming the same
US9577101B2 (en) 2015-03-13 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain regions for fin field effect transistors and methods of forming same
US9496259B2 (en) 2015-04-14 2016-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET semiconductor device having fins with stronger structural strength
US9583626B2 (en) 2015-04-29 2017-02-28 International Business Machines Corporation Silicon germanium alloy fins with reduced defects
US10079302B2 (en) 2015-12-28 2018-09-18 International Business Machines Corporation Silicon germanium fin immune to epitaxy defect
FR3053834B1 (en) * 2016-07-05 2020-06-12 Stmicroelectronics Sa TRANSISTOR STRUCTURE
CN109920846B (en) * 2019-03-11 2023-11-03 长江存储科技有限责任公司 Transistor, forming method thereof and memory
KR20210130899A (en) 2020-04-22 2021-11-02 삼성디스플레이 주식회사 Display apparatus
CN111509048A (en) * 2020-04-28 2020-08-07 上海华力集成电路制造有限公司 N-type fin transistor and manufacturing method thereof

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (en) * 1991-09-18 1993-10-29 Commissariat Energie Atomique PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL.
US5461250A (en) * 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
JP2002043576A (en) * 2000-07-24 2002-02-08 Univ Tohoku Semiconductor device
US6562665B1 (en) * 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US7163864B1 (en) * 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
JP3782021B2 (en) * 2002-02-22 2006-06-07 株式会社東芝 Semiconductor device, semiconductor device manufacturing method, and semiconductor substrate manufacturing method
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2004032246A1 *

Also Published As

Publication number Publication date
CN1685523A (en) 2005-10-19
EP1547156B1 (en) 2010-12-15
AU2003266149A1 (en) 2004-04-23
US20040061178A1 (en) 2004-04-01
KR101020811B1 (en) 2011-03-09
JP2006501672A (en) 2006-01-12
KR20050047129A (en) 2005-05-19
TW200414452A (en) 2004-08-01
WO2004032246A1 (en) 2004-04-15
DE60335391D1 (en) 2011-01-27
US6800910B2 (en) 2004-10-05
CN100524827C (en) 2009-08-05
TWI364095B (en) 2012-05-11

Similar Documents

Publication Publication Date Title
EP1547156B1 (en) Finfet having improved carrier mobility and method of its formation
US7001837B2 (en) Semiconductor with tensile strained substrate and method of making the same
US7071065B1 (en) Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
US6657223B1 (en) Strained silicon MOSFET having silicon source/drain regions and method for its fabrication
US6943087B1 (en) Semiconductor on insulator MOSFET having strained silicon channel
US7138302B2 (en) Method of fabricating an integrated circuit channel region
KR101243997B1 (en) Methods for fabricating a stressed mos device
KR101093785B1 (en) Semiconductor on insulator substrate and device formed therefrom
US20050054164A1 (en) Strained silicon MOSFETs having reduced diffusion of n-type dopants
US6730576B1 (en) Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer
US6849527B1 (en) Strained silicon MOSFET having improved carrier mobility, strained silicon CMOS device, and methods of their formation
US7033869B1 (en) Strained silicon semiconductor on insulator MOSFET
US7923346B2 (en) Field effect transistor structure with an insulating layer at the junction
US7015078B1 (en) Silicon on insulator substrate having improved thermal conductivity and method of its formation
US6924182B1 (en) Strained silicon MOSFET having reduced leakage and method of its formation
US6900143B1 (en) Strained silicon MOSFETs having improved thermal dissipation
JP2009016423A (en) Semiconductor device and manufacturing method thereof
US6893929B1 (en) Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends
CN102751282B (en) A kind of strain BiCMOS integrated device based on crystal face selection and preparation method
CN102738172B (en) A kind of two polyplanar SOI BiCMOS integrated device and preparation method

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20050322

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK

DAX Request for extension of the european patent (deleted)
RBV Designated contracting states (corrected)

Designated state(s): DE FR GB

RIN1 Information on inventor provided before grant (corrected)

Inventor name: XIANG, QI

Inventor name: LIN, MING-REN

Inventor name: GOO, JUNG-SUK

Inventor name: WANG, HAIHONG

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 29/423 20060101ALI20100223BHEP

Ipc: H01L 29/10 20060101ALN20100223BHEP

Ipc: H01L 21/336 20060101ALI20100223BHEP

Ipc: H01L 29/786 20060101AFI20100223BHEP

Ipc: H01L 29/78 20060101ALN20100223BHEP

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 60335391

Country of ref document: DE

Date of ref document: 20110127

Kind code of ref document: P

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20110916

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 60335391

Country of ref document: DE

Effective date: 20110916

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20130910

Year of fee payment: 11

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20150529

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140930

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20220923

Year of fee payment: 20

Ref country code: DE

Payment date: 20220617

Year of fee payment: 20

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230530

REG Reference to a national code

Ref country code: DE

Ref legal event code: R071

Ref document number: 60335391

Country of ref document: DE

REG Reference to a national code

Ref country code: GB

Ref legal event code: PE20

Expiry date: 20230911

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20230911