JP4157496B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP4157496B2 JP4157496B2 JP2004170403A JP2004170403A JP4157496B2 JP 4157496 B2 JP4157496 B2 JP 4157496B2 JP 2004170403 A JP2004170403 A JP 2004170403A JP 2004170403 A JP2004170403 A JP 2004170403A JP 4157496 B2 JP4157496 B2 JP 4157496B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- layer
- effect transistor
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
Description
図1は、本発明の第1の実施形態に係わる半導体装置の概略構成を示す断面図である。
図6は、本発明の第2の実施形態に係わる半導体装置の概略構成を示す断面図である。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
図7は、本発明の第3の実施形態に係わる半導体装置の概略構成を示す断面図である。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
図8は、本発明の第4の実施形態に係わる半導体装置の概略構成を示す断面図である。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
図13は、本発明の第5の実施形態に係わる半導体装置の概略構成を示す断面図である。
図18は、本発明の第6の実施形態に係わる半導体装置の概略構成を示す断面図である。
図21は、本発明の第7の実施形態に係わる半導体装置の要部構造を示す断面図である。なお、図18と同一部分には同一符号を付して、その詳しい説明は省略する。
図24は、本発明の第8の実施形態に係わる半導体装置の要部構造を示す断面図である。
図27は、本発明の第9の実施形態に係わる半導体装置の要部構造を示す断面図である。なお、図24と同一部分には同一符号を付して、その詳しい説明は省略する。
図31は、本発明の第10の実施形態に係わる半導体装置の要部構造を示す断面図である。なお、図27と同一部分には同一符号を付して、その詳しい説明は省略する。
なお、本発明は上述した各実施形態に限定されるものではない。第1〜第10の実施形態で用いた個別技術、例えばソース・ドレインの構造やゲート絶縁膜、ゲート電極の材料等は適宜組み合わせを変えて用いることが可能である。また、SiGeのGe組成として実施形態中に明記されていない値を用いることも当然可能である。集積回路中の各回路ブロックとチャネル材料の組み合わせについても、実施形態中の記述に限定されるものではなく、適宜変更が可能である。
20…pチャネルMISFET
30…インターフェース回路ブロック
40…CPU回路ブロック
50…メモリ回路ブロック
101,301,401,501…Si基板
102,302,402,502…Si酸化膜(絶縁膜)
105,305,405,505…歪みSi層(SOI層)
106,406,506,575…歪みGe層(GOI層)
107,157,207,307,407,507…SiGeゲート電極
108,408,508…HfSiONゲート絶縁膜
109,159,319,409,509…NiSiGe層
110…Si酸化膜(側壁絶縁膜)
111…Si窒化膜(側壁絶縁膜)
112,312,412,512…層間絶縁膜
113,313,413,513…電極
114,127,177…Si酸化膜
115,128…Si窒化膜
117,131…SiGe層
118…Si層
151〜154,251〜254,351,451,551〜555…レジスト
155…Si層(SOI層)
208,308…HfONゲート絶縁膜
209,290,309,569…NiSi層
219…NiGe層
306…歪みSiGe層(SGOI層)
561…バルクSi層
567…ポリSiゲート電極
568…Si酸窒化ゲート絶縁膜
Claims (8)
- Si基板上の一部に形成された絶縁膜と、
前記Si基板上の前記絶縁膜の形成されていない部分に成長形成されたバルクSi領域と、
前記絶縁膜上に該絶縁膜に直接接して形成され、且つ前記バルクSi領域と最上面がほぼ面一に形成された圧縮歪みを有するSi1-x Gex 薄膜(0<x≦1)と、
前記バルクSi領域に形成された第1の電界効果トランジスタと、
前記Si1-x Gex 薄膜に形成された第2の電界効果トランジスタと、
を具備してなることを特徴とする半導体装置。 - 絶縁膜上の一部に該絶縁膜に直接接して形成された伸張歪みを有するSi薄膜と、
前記絶縁膜上の前記Si薄膜が形成されていない部分に該絶縁膜に直接接して形成され、且つ前記Si薄膜と最上面がほぼ面一に形成された圧縮歪みを有するSi1-x Gex 薄膜(0<x≦1)と、
前記Si薄膜に形成されたnチャネルの電界効果トランジスタと、
前記Si1-x Gex 薄膜に形成されたpチャネルの電界効果トランジスタと、
を具備してなることを特徴とする半導体装置。 - Si基板上の一部に形成された絶縁膜と、
前記Si基板上の前記絶縁膜の形成されていない部分に成長形成されたバルクSi領域と、
前記絶縁膜上の一部に該絶縁膜に直接接して形成され、且つ前記バルクSi領域と最上面がほぼ面一に形成された伸張歪みを有するSi薄膜と、
前記絶縁膜上の前記Si薄膜が形成されていない部分に該絶縁膜に直接接して形成され、且つ前記バルクSi領域と最上面がほぼ面一に形成された圧縮歪みを有するSi1-x Gex 薄膜(0<x≦1)と、
前記バルクSi領域に形成された第1の電界効果トランジスタと、
前記Si薄膜に形成された第2の電界効果トランジスタと、
前記Si1-x Gex 薄膜に形成された第3の電界効果トランジスタと、
を具備してなることを特徴とする半導体装置。 - 前記Si薄膜に形成する電界効果トランジスタはnチャネル金属絶縁膜半導体電界効果トランジスタ(MISFET)であり、前記Si1-x Gex 薄膜に形成する電界効果トランジスタはpチャネルMISFETであることを特徴とする請求項3記載の半導体装置。
- 前記Si1-x Gex 薄膜に形成する電界効果トランジスタは、前記バルクSi領域又はSi薄膜に形成される電界効果トランジスタで構成される回路ブロックよりも高速性が要求される回路ブロックを構成するものであることを特徴とする請求項1〜3の何れかに記載の半導体装置。
- 前記nチャネルの電界効果トランジスタはインターフェース回路ブロックを構成するものであり、前記pチャネルの電界効果トランジスタはCPU回路ブロックを構成するものであることを特徴とする請求項2記載の半導体装置。
- 第1の電界効果トランジスタはメモリ回路ブロックを構成するものであり、第2の電界効果トランジスタはインターフェース回路ブロックを構成するものであり、第3の電界効果トランジスタはCPU回路ブロックを構成するものであることを特徴とする請求項3記載の半導体装置。
- 絶縁膜上にSi薄膜を形成する工程と、
前記Si薄膜上の一部にSi1-y Gey 薄膜(0<y<1)を形成する工程と、
酸素を含む雰囲気中で熱処理することにより、前記Si1-y Gey 薄膜とその下のSi薄膜を酸化して表面側にSi酸化膜を形成すると共に、前記絶縁膜に直接接するように圧縮歪みを有するSi1-x Gex 薄膜(0<x≦1,x>y)を形成する工程と、
前記Si酸化膜を除去する工程と、
前記Si薄膜に第1の電界効果トランジスタを形成する工程と、
前記Si1-x Gex 薄膜に第2の電界効果トランジスタを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004170403A JP4157496B2 (ja) | 2004-06-08 | 2004-06-08 | 半導体装置及びその製造方法 |
US11/146,071 US7675115B2 (en) | 2004-06-08 | 2005-06-07 | Semiconductor device and method for manufacturing the same |
US12/656,411 US7985634B2 (en) | 2004-06-08 | 2010-01-28 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004170403A JP4157496B2 (ja) | 2004-06-08 | 2004-06-08 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005353701A JP2005353701A (ja) | 2005-12-22 |
JP4157496B2 true JP4157496B2 (ja) | 2008-10-01 |
Family
ID=35446723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004170403A Active JP4157496B2 (ja) | 2004-06-08 | 2004-06-08 | 半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7675115B2 (ja) |
JP (1) | JP4157496B2 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2908924A1 (fr) * | 2006-12-06 | 2008-05-23 | Commissariat Energie Atomique | PROCEDE DE REALISATION DE ZONES A BASE DE Si1-yGey DE DIFFERENTES TENEURS EN Ge SUR UN MEME SUBSTRAT PAR CONDENSATION DE GERMANIUM |
EP1868233B1 (fr) * | 2006-06-12 | 2009-03-11 | Commissariat A L'energie Atomique | Procédé de réalisation de zones à base de Si1-yGey de différentes teneurs en Ge sur un même substrat par condensation de germanium |
FR2902234B1 (fr) * | 2006-06-12 | 2008-10-10 | Commissariat Energie Atomique | PROCEDE DE REALISATION DE ZONES A BASE DE Si1-yGey DE DIFFERENTES TENEURS EN Ge SUR UN MEME SUBSTRAT PAR CONDENSATION DE GERMANIUM |
JP4271210B2 (ja) | 2006-06-30 | 2009-06-03 | 株式会社東芝 | 電界効果トランジスタ、集積回路素子、及びそれらの製造方法 |
FR2905519B1 (fr) | 2006-08-31 | 2008-12-19 | St Microelectronics Sa | Procede de fabrication de circuit integre a transistors completement depletes et partiellement depletes |
US7838353B2 (en) | 2008-08-12 | 2010-11-23 | International Business Machines Corporation | Field effect transistor with suppressed corner leakage through channel material band-edge modulation, design structure and method |
US8125037B2 (en) | 2008-08-12 | 2012-02-28 | International Business Machines Corporation | Field effect transistor with channel region edge and center portions having different band structures for suppressed corner leakage |
FR2936095B1 (fr) * | 2008-09-18 | 2011-04-01 | Commissariat Energie Atomique | Procede de fabrication d'un dispositif microelectronique dote de zones semi-conductrices sur isolant a gradient horizontal de concentration en ge. |
JP5058277B2 (ja) * | 2010-02-26 | 2012-10-24 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP5454984B2 (ja) | 2010-03-31 | 2014-03-26 | 株式会社東芝 | 半導体装置の製造方法 |
US8816429B2 (en) | 2011-07-07 | 2014-08-26 | Fairchild Semiconductor Corporation | Charge balance semiconductor devices with increased mobility structures |
US8828851B2 (en) * | 2012-02-01 | 2014-09-09 | Stmicroeletronics, Inc. | Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering |
JP2014187259A (ja) | 2013-03-25 | 2014-10-02 | Toshiba Corp | 半導体装置の製造方法 |
US9219150B1 (en) * | 2014-09-18 | 2015-12-22 | Soitec | Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures |
DE102015205458B3 (de) * | 2015-03-25 | 2016-06-09 | Globalfoundries Inc. | Verfahren zum Herstellen einer Halbleitervorrichtungsstruktur |
US9818875B1 (en) * | 2016-10-17 | 2017-11-14 | International Business Machines Corporation | Approach to minimization of strain loss in strained fin field effect transistors |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07106434A (ja) | 1993-10-05 | 1995-04-21 | Mitsubishi Electric Corp | 半導体記憶装置及びその製造方法 |
JP3372158B2 (ja) | 1996-02-09 | 2003-01-27 | 株式会社東芝 | 半導体装置及びその製造方法 |
US5847419A (en) * | 1996-09-17 | 1998-12-08 | Kabushiki Kaisha Toshiba | Si-SiGe semiconductor device and method of fabricating the same |
JPH11238860A (ja) | 1998-02-19 | 1999-08-31 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2001160594A (ja) | 1999-09-20 | 2001-06-12 | Toshiba Corp | 半導体装置 |
US6555874B1 (en) * | 2000-08-28 | 2003-04-29 | Sharp Laboratories Of America, Inc. | Method of fabricating high performance SiGe heterojunction bipolar transistor BiCMOS on a silicon-on-insulator substrate |
JP3547419B2 (ja) * | 2001-03-13 | 2004-07-28 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7022530B2 (en) * | 2001-04-03 | 2006-04-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
JP4034627B2 (ja) * | 2001-09-28 | 2008-01-16 | テキサス インスツルメンツ インコーポレイテツド | 集積回路及びその製造方法 |
JP3934537B2 (ja) | 2001-11-30 | 2007-06-20 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP3825688B2 (ja) | 2001-12-25 | 2006-09-27 | 株式会社東芝 | 半導体装置の製造方法 |
JP2003258212A (ja) | 2001-12-27 | 2003-09-12 | Toshiba Corp | 半導体装置 |
JP2003243528A (ja) | 2002-02-13 | 2003-08-29 | Toshiba Corp | 半導体装置 |
JP3782021B2 (ja) * | 2002-02-22 | 2006-06-07 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、半導体基板の製造方法 |
JP3597831B2 (ja) | 2002-07-01 | 2004-12-08 | 株式会社東芝 | 電界効果トランジスタ及びその製造方法 |
JP2004247341A (ja) * | 2003-02-10 | 2004-09-02 | Renesas Technology Corp | 半導体装置 |
US6963078B2 (en) * | 2003-03-15 | 2005-11-08 | International Business Machines Corporation | Dual strain-state SiGe layers for microelectronics |
JP4413580B2 (ja) * | 2003-11-04 | 2010-02-10 | 株式会社東芝 | 素子形成用基板の製造方法 |
US7262087B2 (en) * | 2004-12-14 | 2007-08-28 | International Business Machines Corporation | Dual stressed SOI substrates |
-
2004
- 2004-06-08 JP JP2004170403A patent/JP4157496B2/ja active Active
-
2005
- 2005-06-07 US US11/146,071 patent/US7675115B2/en active Active
-
2010
- 2010-01-28 US US12/656,411 patent/US7985634B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20050269595A1 (en) | 2005-12-08 |
JP2005353701A (ja) | 2005-12-22 |
US7675115B2 (en) | 2010-03-09 |
US7985634B2 (en) | 2011-07-26 |
US20100136752A1 (en) | 2010-06-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7985634B2 (en) | Semiconductor device and method for manufacturing the same | |
US7538390B2 (en) | Semiconductor device with PMOS and NMOS transistors | |
JP4639172B2 (ja) | 半導体デバイス | |
KR100495023B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US7319258B2 (en) | Semiconductor-on-insulator chip with<100>-oriented transistors | |
JP2003060076A (ja) | 半導体装置及びその製造方法 | |
JP2000243854A (ja) | 半導体装置及びその製造方法 | |
TW200406881A (en) | Semiconductor device structure including multiple FETs having different spacer widths | |
KR20120022552A (ko) | 반도체 장치 및 그 제조 방법 | |
JP2008117963A (ja) | 電界効果トランジスタおよび半導体装置、ならびにそれらの製造方法 | |
US20130285117A1 (en) | CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION | |
JPWO2006137371A1 (ja) | 半導体装置 | |
JP2000031491A (ja) | 半導体装置,半導体装置の製造方法,半導体基板および半導体基板の製造方法 | |
US10658387B2 (en) | Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation | |
JP2006100600A (ja) | 半導体装置およびその製造方法 | |
JP2010118500A (ja) | 半導体装置及びその製造方法 | |
JP3311940B2 (ja) | 半導体装置及びその製造方法 | |
US20080173950A1 (en) | Structure and Method of Fabricating Electrical Structure Having Improved Charge Mobility | |
JP2004193166A (ja) | 半導体装置 | |
JP2005079277A (ja) | 電界効果トランジスタ | |
JP2004247341A (ja) | 半導体装置 | |
US20070187669A1 (en) | Field effect transistor and a method for manufacturing the same | |
US7718497B2 (en) | Method for manufacturing semiconductor device | |
US20100264471A1 (en) | Enhancing MOSFET performance with stressed wedges | |
JP2007173356A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060421 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060523 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060714 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071030 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080104 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080708 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080711 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110718 Year of fee payment: 3 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 4157496 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110718 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120718 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130718 Year of fee payment: 5 |