WO2012041038A1 - 半导体器件以及形成应变半导体沟道的方法 - Google Patents
半导体器件以及形成应变半导体沟道的方法 Download PDFInfo
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- WO2012041038A1 WO2012041038A1 PCT/CN2011/071310 CN2011071310W WO2012041038A1 WO 2012041038 A1 WO2012041038 A1 WO 2012041038A1 CN 2011071310 W CN2011071310 W CN 2011071310W WO 2012041038 A1 WO2012041038 A1 WO 2012041038A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 62
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims description 48
- 230000008569 process Effects 0.000 claims description 37
- 229910052732 germanium Inorganic materials 0.000 claims description 13
- 238000000206 photolithography Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 246
- 229910052751 metal Inorganic materials 0.000 description 26
- 239000002184 metal Substances 0.000 description 26
- 238000004519 manufacturing process Methods 0.000 description 18
- 239000011248 coating agent Substances 0.000 description 12
- 238000000576 coating method Methods 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 125000006850 spacer group Chemical group 0.000 description 10
- 238000000137 annealing Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000011282 treatment Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 238000005253 cladding Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910010038 TiAl Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052772 Samarium Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
Definitions
- the present invention relates to the field of semiconductors, and more particularly to semiconductor devices and methods of fabricating the same, and more particularly to a method of forming a strained semiconductor channel and a semiconductor device fabricated by the method. Background technique
- the composition of the SiGe relaxation layer is expressed in the form of S - x Ge x , xe [0, 1].
- Fig. 1A shows a schematic diagram of an atomic lattice of a tensile strained Si layer structure disposed on a SiGe relaxed layer
- Fig. 1B shows an energy level structure of a tensile strained Si layer structure disposed on a SiGe relaxed layer.
- the conduction band in the tensile strained Si layer is lower than that in the SiGe relaxation layer due to the large biaxial tensile stress in the tensile strained Si layer.
- a very high electronic in-plane mobility will be obtained in the tensile strained Si layer.
- Figures 2A and 2B show theoretical results of the effect of strain on hole mobility, see K. Sawano et al. Applied Physics Letters (Vol. 87, p. 192102, 2005). The above studies show that the compressive strain in the Ge channel on SiGe helps to improve the hole mobility.
- FIG. 3A, 3B and 3C respectively show three conventional strain Si channel formation methods
- Fig. 3A shows a strained Si/body SiGe MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure
- Fig. 3B shows SGOI ( S iGe-On-Insulator ) M0SFBT structure
- FIG. 3C shows the SSD0I (Stra ined Si Direct ly On Insulator) MOSFET structure.
- strain Si must be formed on the SiGe layer (or buried oxide) before the device fabrication process (for example, shallow trench isolation (STI), gate formation, etc.) Cladding.
- the strained Si coating may be damaged during the device fabrication process, for example, pad oxidation treatment in the STI process, sacrificial oxidation before the gate formation process Treatment, various wet chemical cleaning treatments, etc., may cause loss of the strained Si coating;
- the strained Si coating may relax during the high temperature step (stress is released), for example, to activate the source/ Drain dopant Annealing may cause stress in the strained Si coating to be released. Summary of the invention
- the present invention proposes a strained semiconductor channel forming method in which a strained semiconductor channel (a channel including a tensile strained Si layer and a trench including a compressive strained Ge layer) is formed after the dummy gate is removed. Channel), thereby avoiding the source/drain annealing process in which the strained semiconductor channel is exposed to high temperature, and avoiding the loss of strained semiconductor material by reducing the processing steps to be experienced by straining the semiconductor channel, and at the same time, The ground maintains the stress in the channel.
- a tensile strained Si layer and a compressive strained Ge layer are integrated on a SiGe substrate.
- the tensile strained Si layer can improve the electron mobility in the NMOS transistor, and the compressive strained Ge layer can improve the hole mobility in the PMOS transistor, thereby providing double strain in a semiconductor device including a wake-up transistor and a PMOS transistor ( Pull strain and compressive strain). Further, the present invention also proposes a semiconductor device manufactured by the method.
- a method of forming a strained semiconductor channel comprising the steps of: forming a SiGe relaxation layer on a semiconductor substrate; forming a NMOS transistor and a PMOS transistor on the SiGe relaxation layer Semiconductor structure, the NMOS transistor and the PMOS transistor respectively comprise a dummy gate stack composed of a dielectric and a dummy gate; the dummy gate stack is removed to form an opening; and a pull is formed in the opening of the NMOS transistor A strained epitaxial layer is formed, and a compressive strain epitaxial layer is formed in the opening of the PMOS transistor.
- a lattice constant 'J of a material forming the tensile strain epitaxial layer in a relaxed state, a lattice constant of the SiGe relaxed layer, and a material forming the compressive strain epitaxial layer are relaxed
- the lattice constant in the state is greater than the lattice constant of the SiGe relaxed layer.
- the material forming the tensile strain epitaxial layer and the material forming the compressive strain epitaxial layer both comprise SiGe, and the percentage of Ge atoms in the tensile strain epitaxial layer is smaller than the percentage of Ge atoms in the SiGe relaxation layer, And, the percentage of Ge atoms in the compressive strain epitaxial layer is greater than the percentage of Ge atoms in the SiGe relaxed layer.
- the material forming the tensile strain epitaxial layer is Si
- the material forming the compressive strain epitaxial layer is Ge
- the material forming the tensile strain epitaxial layer comprises Si:c.
- the step of forming the tensile strain epitaxial layer and the compressive strain epitaxial layer comprises: forming a mask and performing photolithography, covering the opening on the PMOS transistor side, exposing the opening on the side of the OS transistor; at the opening Performing epitaxial growth of the selective tensile strained material to form the tensile strained epitaxial layer; forming a mask and performing photolithography to cover the opening on the side of the NMOS transistor, exposing the opening on the side of the PMOS transistor; Epitaxial growth of a selective compressive strain material is performed in the opening to form the compressive strain epitaxial layer.
- the strained semiconductor channel forming method further comprises the following steps of: etching the S iGe relaxation layer in the opening, A space for epitaxial growth of tensile strained materials and/or epitaxial growth of compressive strained materials is etched.
- a semiconductor device comprising: a semiconductor substrate; a S iGe relaxation layer on the semiconductor substrate; a wake-up OS transistor on the SiGe relaxation layer; and a PMOS a transistor, located on the S iGe relaxation layer, wherein the NMOS transistor comprises: a strained epitaxial layer on the S iGe relaxation layer or embedded in the S iGe relaxation layer;
- the leg OS transistor includes: a compressive strain epitaxial layer on the SiGe relaxation layer or embedded in the SiGe relaxation layer.
- both the leg OS transistor and the PMOS transistor comprise a gate stack formed by a replacement gate process, the gate stack being composed of a gate and a dielectric.
- a lattice constant 'J of a material forming the tensile strain epitaxial layer in a relaxed state, a lattice constant of the S iGe relaxed layer, and a material forming the compressive strain epitaxial layer are in a state
- the lattice constant in the Henan state is greater than the lattice constant of the S iGe relaxed layer.
- the material forming the tensile strain epitaxial layer and the material forming the compressive strain epitaxial layer both include S iGe, and the percentage of Ge atoms in the tensile strain epitaxial layer is smaller than the Ge atom in the S iGe relaxation layer And a percentage of Ge atoms in the compressive strain epitaxial layer is greater than a percentage of Ge atoms in the SiGe relaxed layer.
- the material forming the tensile strain epitaxial layer is Si
- the material forming the compressive strain epitaxial layer is Ge.
- the material forming the tensile strain epitaxial layer comprises Si: C.
- the etch stop layer is further included in the SiGe relaxation layer.
- the etch stop layer has a different percentage of Ge atoms than the SiGe relaxed layer.
- it is not necessary to form a tensile strained Si coating and a compressive strained Ge coating on the SiGe layer (or buried oxide) before the device fabrication process, but instead of using the replacement gate process, after removing the replacement gate Forming a strained semiconductor layer, thereby avoiding exposure of the strained semiconductor channel to a high temperature source/drain annealing process, and avoiding the loss of the strained semiconductor material by reducing the processing steps to be experienced by straining the semiconductor channel, and at the same time, Goodly maintain the stress in the channel.
- 1A is a schematic view showing an atomic lattice of a tensile strained Si layer structure disposed on a SiGe relaxed layer;
- FIGS. 1B shows the energy level structure of a tensile strained Si layer structure disposed on a SiGe relaxed layer
- FIGS. 2A and 2B show theoretical results of the effect of strain on hole mobility
- FIGS. 3A, 3B, and 3C Three conventional strain Si channel forming methods are respectively shown
- FIGS. 4-19 are schematic views showing respective steps of the semiconductor device manufacturing method proposed by the first embodiment of the present invention, wherein FIG. 19 shows A semiconductor device manufactured by the method of manufacturing a semiconductor device proposed by the first embodiment of the invention
- FIGS. 4 to 9 and 20 to 28 are schematic views showing respective steps of a method of fabricating a semiconductor device according to a second embodiment of the present invention, wherein Fig. 28 shows a fabrication of a semiconductor device according to a second embodiment of the present invention. The method of fabricating a completed semiconductor device.
- FIG. Figure 19 is a schematic view showing a semiconductor device in which a semiconductor device manufacturing method is completed according to a first embodiment of the present invention.
- the semiconductor device manufactured according to the process of the first embodiment of the present invention mainly comprises: a substrate 300 (Si wafer, SOI, etc.), a SiGe relaxation layer 200 (Ge atom% is as shown in FIG. The bottom-up direction, from 20% to 100%), the interlayer dielectric layer 250 (thickness of 15 to 50 legs), the NMOS transistor side and the PMOS transistor side, wherein the SiGe relaxation layer 200 is formed on the substrate 300
- the interlayer dielectric layer 250 is deposited on the SiGe relaxation layer 200.
- the OS transistor side includes: a Si epitaxial layer 260n (thickness of 5 to 10 faces), a high germanium dielectric layer 320, (thickness of 1 to 3 nm), a metal gate 330!, and a Si 3 N 4 sidewall 240n (width of 10) ⁇ 40 legs), an NMOS transistor gate structure composed of a Si 3 N 4 sidewall 240n, a Si epitaxial layer 260 ⁇ , a germanium dielectric layer 320, and a metal gate 331 ⁇ is formed on the SiGe relaxation layer 200;
- the electrical layer 250 surrounds the outer periphery of the Si 3 N 4 sidewall spacer 240 n of the gate structure of the NMOS transistor; the Si epitaxial layer 260 n is formed on the SiGe relaxation layer 200 and embedded in the SiGe relaxation layer 200; the high K dielectric layer 320 Deposited on the entire surface of the Si epitaxial layer 260n and formed into a hollow cylindrical shape having a bottom surface; a metal gate
- the PM0S transistor side includes: a Ge epitaxial layer 260p (thickness of 5 to 10 legs), a high-k dielectric layer 320 2 (thickness of 1-3 nm), a metal gate 330 2, and a Si sidewall 240p (width of 10 to 40 legs).
- a PMOS transistor gate structure composed of a Si 3 N 4 sidewall 240p, a Ge epitaxial layer 260p, a high dielectric layer 320 2 , and a metal gate 330 2 is formed on the SiGe relaxation layer 200;
- the interlayer dielectric layer 250 surrounds The periphery of the Si spacer 240p of the gate structure of the PMOS transistor;
- Ge outside The extension layer 260p is formed on the SiGe relaxation layer 200 and embedded in the SiGe relaxation layer 200;
- the high K dielectric layer 320 2 is deposited on the entire surface of the Ge epitaxial layer 260p, and is formed into a hollow column having a bottom surface;
- the gate 330 2 is filled inside the hollow cylindrical shape formed by the high-k dielectric layer 320 2 ;
- the sidewall spacer 240p is formed on the SiGe relaxed layer 200 around the outer periphery of the high-k dielectric layer 320 2 .
- shallow trench isolation STI may be disposed between the gate structure of the NMOS transistor and the gate structure of the PMOS transistor.
- the first embodiment of the present invention it is not necessary to form a tensile strain S i cladding layer and a compressive strain Ge cladding layer on the SiGe relaxation layer 200 before the device fabrication process, particularly before forming the source/drain regions.
- the S i epitaxial layer 260n and the Ge epitaxial layer 260p are formed after the dummy gate is removed and the source/drain regions are formed, thereby avoiding the strained Si channel and the strained Ge channel being exposed to the high temperature source/
- the drain annealing process and due to the processing steps to be experienced by reducing the strained Si channel and the strained Ge channel, the loss of the Si epitaxial layer 260n and the Ge epitaxial layer 260p is avoided, and the stress in the channel can be better maintained.
- a SiGe relaxation layer 200 is formed on a substrate 300 (Si wafer, SOI, etc.).
- the Ge atom % that is, the number of Ge atoms as a percentage of the total number of atoms, is in the direction from bottom to top as shown in FIG. 4 (from the vicinity of the substrate 300 to the direction away from the substrate 300). ), for example, from 20°/.
- the gradual change to 100% that is, the x in the composition of Si x Ge x gradually changes from 0.2 to 1.
- the specific numerical values of the composition of the S iGe relaxation layer 200 are for illustrative purposes only, and those skilled in the art can select an appropriate other composition according to actual needs (ie, reselect the range of variation of X), and gradually
- the change can be a variety of variations such as linear changes, Han curve changes, and exponential changes.
- an etch stop layer eg, a change in Ge atomic % may be formed in the SiGe relaxed layer 200, so that the depth of the etch to be performed in the step shown in FIG. 10 can be controlled.
- the control of the etching depth can be achieved by forming a laminated structure of the relaxation layer/etch stop layer/relaxation layer in the SiGe relaxation layer 200 as needed.
- a surface OS transistor dummy gate structure (dielectric layer 220, dummy gate 230) is formed on the SiGe relaxation layer 200.
- the polysilicon gate 230 15 is also illustrated as an alternative power.
- Other materials known in the art surrounding and covering dielectric layer 220, and polysilicon gate 230, Si ⁇ sidewall spacer 240n and S i cap layer 241n) and PMOS transistor dummy gate structure (dielectric layer 220 2 dummy gate 230 2 (illustration For polysilicon gate 230 2 , other materials known in the art can also be used, S i 3 1 surrounding and covering dielectric layer 220 2 and polysilicon gate 230 2 , and wall 24 Op and S i cap layer 241p ).
- the dielectric layers 220, and 220 2 have a thickness of 1 to 3, and the thickness of the polysilicon gates 230! and 230 2 is 20 to 70 nm, and the width of the Si ⁇ sidewall spacers 240n and 240p in the horizontal direction shown is 10 ⁇ 40 nm, the thickness of the Si 3 N 4 cap layers 241n and 241p is 15 40 nm.
- This step is also part of the conventional process, there is formed a polysilicon gate 230 and dummy gate 2302 as an alternative to the metal gate.
- a source/drain region is formed by a conventional method (for example, by performing ion and high temperature annealing) (in the figure) Not shown), and after forming a shallow trench isolation STI between the NMOS OS transistor dummy gate structure and the PMOS transistor dummy gate structure, as shown in FIG. 6, after the awake OS transistor dummy gate structure and the PMOS transistor dummy gate structure have been formed
- An interlayer dielectric layer (Inter Layer Die) layer 250 is deposited on the S iGe relaxation layer 200.
- undoped silicon oxide Si0 2
- various doped silicon oxides such as borosilicate glass, borophosphosilicate glass, etc.
- silicon nitride Si 3 NJ or the like
- the constituent materials can be used as the interlayer dielectric layer 250 The constituent materials.
- the interlayer dielectric layer 250 is subjected to a chemical mechanical planarization (CMP) process to expose the dummy gate structure of the Si 3 N 4 cap layers 241 ⁇ and 241p.
- CMP chemical mechanical planarization
- an additional CMP process or a reactive ion etching (RIE) process for S i 3 N 4 is performed to remove the Si cap layers 241n and 241p, exposing the dummy gate structure of the 0S transistor and the PMOS transistor dummy.
- RIE reactive ion etching
- the polysilicon gate 230 is removed by wet etching or dry etching, and 230 2
- the SiGe relaxed layer 200 is etched by wet etching or dry etching to etch a space for Si epitaxial growth and Ge epitaxial growth (etching depth is 5 ⁇ 10 dishes).
- an etch stop layer e.g., a change in Ge atom% may be formed in the SiGe relaxation layer 200 so that the etching depth can be controlled.
- an epitaxial barrier layer 465 is deposited on the entire surface of the structure shown in FIG. 10, and the epitaxial barrier layer includes, for example, a S i0 2 or S i 3 N 4 film, and here, a S i0 2 film is used.
- the epitaxial barrier layer includes, for example, a S i0 2 or S i 3 N 4 film, and here, a S i0 2 film is used.
- a mask lithography process is performed on the S iOJ 465 to remove the SiO 2 film 465 on the NMOS transistor side while leaving the S i0 2 film 465 on the PMOS transistor side (labeled as 465p).
- the opening formed by etching on the NMOS transistor side
- selective Si epitaxial growth is performed to form an Si epitaxial layer 260n embedded in the SiGe relaxation layer 200, and the Si epitaxial layer 260n
- the top surface may be on the same plane as the top surface of the S iGe relaxation layer 200 (as shown in FIG. 13) or may not be on the same plane (not shown).
- the SiO 2 film 475n is formed to cover the NMOS transistor side, and the SiO 2 465p on the PMOS transistor side is removed.
- the opening (PM0S transistor side) formed by etching selective Ge epitaxial growth is performed to form a Ge epitaxial layer 260p embedded in the SiGe relaxation layer 200, and a top surface of the Ge epitaxial layer 260p It may be on the same plane as the top surface of the SiGe relaxation layer 200 (as shown in FIG. 15), or may not be on the same plane (not shown).
- the SiO 2 film 475n covering the side of the NMOS transistor is removed.
- a high-k dielectric layer 320 is deposited on the surface of the structure shown in Fig. 16, and the deposition thickness is in the range of 1 to 3 legs.
- the metal layer for constituting the metal gates 330, and 330 2 is deposited on the surface of the high-k dielectric layer 320.
- the metal layer may include a plurality of conductive layers, for example, first deposition
- the TiN layer is then deposited with a TiAl layer.
- a planarization process (for example, CMP process, etc.) is performed on the formed metal layer and the high-k dielectric layer 320, and the interlayer dielectric layer 250 and the S i 3 N 4 side wall are removed.
- the poly gate is used as a dummy gate.
- 230 2 has been completely replaced by metal grid 330 2 .
- a semiconductor fabrication process such as formation of a source region silicide/drain silicide or the like can be performed in accordance with a conventional method.
- the order of the above steps can be changed.
- the pole annealing treatment, and the processing steps to be experienced by reducing the strained S i channel and the strained Ge channel avoids the loss of the Si epitaxial layer 26011 and the Ge epitaxial layer 260p, and can better maintain the stress in the channel.
- FIG. Figure 28 is a schematic view showing a semiconductor device in which a semiconductor device manufacturing method is completed according to a second embodiment of the present invention.
- the semiconductor device manufactured by the process according to the second embodiment of the present invention mainly comprises: a substrate 300 (Si wafer, SOI, etc.), and a SiGe relaxation layer 200 (Ge atom% is as shown in FIG. The bottom-up direction, from 20% to 100%), the interlayer dielectric layer 250 (thickness 15 to 50 sides), the NMOS transistor side and the PMOS transistor side, wherein the S iGe relaxation layer 200 is formed on the substrate At 300, an interlayer dielectric layer 250 is deposited over the SiGe relaxed layer 200.
- the transistor side of the OS includes: a Si epitaxial layer 260n (thickness of 5 to 10 bodies), a high-k dielectric layer 320, (thickness of 1 to 3 legs), a metal gate 330!, and a Si 3 i wall 240n (width of 10) - 40 legs), a gate electrode structure of the OS transistor formed by the S i sidewall 240n, the Si epitaxial layer 260n, the high K dielectric layer 320, and the metal gate 330 is formed on the SiGe relaxation layer 200; interlayer dielectric The layer 250 surrounds the outer circumference of the Si 3 N 4 sidewall spacer 240 n of the gate electrode structure of the NMOS; the Si epitaxial layer 26011 is located on the top surface of the S iGe relaxation layer 200; the samarium dielectric layer 320 is deposited on the S i The entire surface of the epitaxial layer 260ii is formed into a hollow cylindrical shape having a bottom surface; the metal gate 330 is filled in
- the PM0S transistor side includes: Ge epitaxial layer 260p (thickness 5 ⁇ 10 let), high K dielectric layer 320 2 (thickness 1 ⁇ 3 legs), metal gate 330 2 and S i 3 N 4 side wall 240p (width is 10 to 40 legs), a PMOS transistor gate structure composed of a Si 3 N 4 spacer 240p, a Ge epitaxial layer 260p, a high K dielectric layer 320 2 and a metal gate 330 2 is formed on the S iGe relaxation layer 200; Dielectric The layer 250 surrounds the outer circumference of the Si side wall 240p of the PMOS transistor gate structure; the Ge epitaxial layer 260p is located on the top surface of the SiGe relaxation morning 200; the high K dielectric layer 320 2 is deposited on the entire surface of the Ge epitaxial layer 260p And formed as a hollow cylindrical shape having a bottom surface; the metal gate 330 2 is filled inside the hollow cylindrical shape formed by the high-k dielectric layer 320 2 ; the S
- shallow trench isolation STI may be disposed between the gate structure of the NMOS transistor and the gate structure of the PMOS transistor.
- the S i epitaxial layer 260n and the Ge epitaxial layer 260p are formed after the dummy gate is removed and the source/drain regions are formed, thereby avoiding the strained Si channel and the strain Ge channel being exposed to the high temperature source.
- FIGS. 4 to 9 are the same as those of the first embodiment of the present invention. For the sake of clarity, detailed descriptions of FIGS. 4 to 9 are omitted herein. For details, refer to the detailed description in the first embodiment.
- the polysilicon gate 230, and 2302 have been removed by wet etching or dry etching.
- an epitaxial barrier layer 365 is deposited on the entire surface of the structure shown in FIG. 9, and the epitaxial barrier layer includes, for example, a S0O 2 or S iA film, where the S i0 2 film is used as an unrestricted example.
- Si0 2 film 365 is removed Videos OS transistor side and leaving the Si0 2 film 365 of the PMOS transistor side (labeled 365p) 0
- S i epitaxial growth is performed directly on the SiGe relaxation layer 200 in the opening surrounded by the Si 3 N 4 spacer 240 ⁇ to form the S iGe relaxation layer 200.
- S i of the top surface of the epitaxial layer 260n, 260n thickness of the epitaxial layer SI is 5 ⁇ 10nm o
- S i0 2 film is formed to cover Korea 375 ⁇ OS transistor side, removing PM0S transistor side of Si0 2 Membrane 365p. Then, as shown in FIG.
- selective Ge epitaxial growth is performed directly on the Si i relaxation layer 200 in the opening surrounded by the Si 3 N 4 spacer 240p to form a top surface of the SiGe relaxation layer 200.
- the Ge epitaxial layer 260p, the Ge epitaxial layer 26 Op has a thickness of 5 to 10 faces.
- a high-k dielectric layer 320 is deposited on the surface of the structure shown in Fig. 25, and the deposition thickness is in the range of 1 to 3.
- the metal layer for constituting the metal gates 330, and 330 2 is deposited on the surface of the high-k dielectric layer 320.
- the metal layer may include a plurality of conductive layers, for example, first deposition
- the TiN layer is then deposited with a TiAl layer.
- a planarization process (for example, CMP process, etc.) is performed on the formed metal layer and the high-k dielectric layer 320, and the interlayer dielectric layer 250 and the Si 3 N 4 side wall are removed.
- the high germanium dielectric layer 320 and the metal layer on top of 240 ⁇ and 240 ⁇ form a high germanium dielectric layer 320, and 320 2 and a metal gate 330, and 330 2 .
- the polysilicon gate 230 2 as a dummy gate has been completely replaced by the metal gates 330, and 330 2 .
- the semiconductor fabrication process can be performed in accordance with a conventional method, such as formation of a source region silicide/drain region silicide or the like.
- the order of the above steps can be changed.
- the second embodiment of the present invention it is not necessary to form a tensile strained Si coating and a compressive strained Ge coating on the SiGe relaxation layer 200 before the device fabrication process, particularly before the source/drain regions are formed.
- the S i epitaxial layer 260n and the Ge epitaxial layer 260p are formed after the dummy gate is removed and the source/drain regions are formed by using a replacement gate process, thereby avoiding the exposure of the strained S i channel and the strained Ge channel to a high temperature source.
- the material for forming the tensile strain epitaxial layer is not limited to the above-described Si epitaxial layer 260n, and other materials having a lattice constant smaller than the lattice constant of the SiGe relaxation layer 200 in the relaxed state may be selected.
- the material for forming the compressive strain epitaxial layer is not limited to the above Ge epitaxial layer 260p, and other materials having a lattice constant greater than the lattice constant of the SiGe relaxation layer 200 in the relaxed state may be selected.
- a SiGe epitaxial layer such as a Ge atomic percentage greater than a Ge atomic percentage in the SiGe relaxed layer 200.
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US20070023795A1 (en) * | 2005-07-15 | 2007-02-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
US20080079084A1 (en) * | 2006-09-28 | 2008-04-03 | Micron Technology, Inc. | Enhanced mobility MOSFET devices |
CN101405865A (zh) * | 2006-03-17 | 2009-04-08 | 艾康技术公司 | 具有弹性边缘弛豫的应变硅 |
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US20050205929A1 (en) * | 2004-03-16 | 2005-09-22 | Hajime Nagano | Semiconductor substrate, manufacturing method therefor, and semiconductor device |
US20070023795A1 (en) * | 2005-07-15 | 2007-02-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
CN101405865A (zh) * | 2006-03-17 | 2009-04-08 | 艾康技术公司 | 具有弹性边缘弛豫的应变硅 |
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