TW550997B - Module with built-in components and the manufacturing method thereof - Google Patents

Module with built-in components and the manufacturing method thereof Download PDF

Info

Publication number
TW550997B
TW550997B TW091123553A TW91123553A TW550997B TW 550997 B TW550997 B TW 550997B TW 091123553 A TW091123553 A TW 091123553A TW 91123553 A TW91123553 A TW 91123553A TW 550997 B TW550997 B TW 550997B
Authority
TW
Taiwan
Prior art keywords
component
electrical insulation
insulation layer
aforementioned
patent application
Prior art date
Application number
TW091123553A
Other languages
English (en)
Inventor
Toshiyuki Asahi
Yasuhiro Sugaya
Shingo Komatsu
Yoshiyuki Yamamoto
Seiichi Nakatani
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Application granted granted Critical
Publication of TW550997B publication Critical patent/TW550997B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401Structure
    • H01L2224/2402Laminated, e.g. MCM-L type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8121Applying energy for connecting using a reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009Pre-treatment of the connector or the bonding area
    • H01L2224/8203Reshaping, e.g. forming vias
    • H01L2224/82047Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01009Fluorine [F]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01012Magnesium [Mg]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19042Component type being an inductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30105Capacitance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10378Interposers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10636Leadless chip, e.g. chip capacitor or resistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06Lamination
    • H05K2203/061Lamination of previously made multilayered subassemblies
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Description

550997 A7 r--"- 五、發明說明(I ) 〔技術領域〕 本發明係關於電路元件配置於電氣絕緣層的內部之電 路元件內藏模組及其製造方法。 〔習知技術〕 於近年來之電子機器的高性能化、小型化的潮流之中 ’更加要求著電路元件的高密度、高機能化。於搭載電路 元件之模組中,須要求能因應高密度、高機能化之需求。 作爲電路元件之高密度地構裝的方法,目前,配線基板有 朝向多層化之傾向。於習知的玻璃布-環氧樹脂含浸基板中 ,係使用藉由鑽頭之貫穿的穿孔構造而達成多層化,可靠 性雖高,但並不適於高密度構裝。因此之故,作爲最能夠 謀求電路元件的高密度化之方法,藉由內導通孔連接之多 層配線基板亦被採用著。藉由內導通孔連接,可使LSI間 或元件間的配線圖案以最短距離連接,可只對必要的各層 作連接,於電路元件的構裝性方面亦優異。又,在配線圖 案的微細化與高密度構裝上所不可或缺的技術之線寬線距 (line and space)年年益趨減小。而且,在基板內形成被動 元件之3維構裝也正在開發中。 然而,爲了在基板內部形成被動元件,於材料開發、 形成精度、設備投資等方面有待克服的課題甚多,致開發 速度緩慢。 又,本案申請人亦曾提案在基板內部內藏被動元件者( 特開平1 1(1999)_220262號公報、美國專利第6,038,133號 公報)。然而,依據此提案之實施例,由於係於將元件埋設 —____4______ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) ----訂---------線 »· 550997 A7 B7—_____ 五、發明說明(2/ ) 至基板內部之後再形成配線’故於內藏前’無法進行對半 導體等之元件之構裝檢查或特性檢查’是其問題。又,由 於並非將配線基板一體化再行埋設,故強度並不高,亦爲 問題。 〔發明之槪要〕 本發明爲解決前述習知的問題’其目的係提供於內藏 前可進行半導體等的元件之構裝檢查或特性檢查、可提高 良率、提高強度、生產性高、可尚密度構裝的元件內藏模 組。 爲達成上述之目的,本發明之元件內藏模組,係含有 .:電氣絕緣層、在前述電氣絕緣層的兩表面上一體化形成 之配線、及用以連接前述配線間之導通孔,於前述電氣絕 緣層的內部,埋設有選自電子元件及半導體之至少一種元 件所成者,其特徵在於:前述配線之至少一方,係形成於 配線基板的表面之配線;埋設於前述電氣絕緣層的內部之 元件,係於埋設之前搭載於前述配線基板上且構成一體化 〇 又,本發明之元件內藏模組之製造方法,該元件內藏 模組係含有:電氣絕緣層、在前述電氣絕緣層的兩表面上 一體化形成之配線、及用以連接前述配線間之導通孔,於 前述電氣絕緣層的內部,埋設有選自電子元件及半導體之 至少一種元件所成者,其特徵在於包含··前述配線之至少 一方’係形成於配線基板的表面之配線;在前述配線基板 上構裝選自電子元件及半導體之至少一種元件;沿著由半 _______5___ 私紙張尺度剌中關家標準(CNS)A4規格(21Q χ 297公爱)' ""^ {請先閱讀背面之注意事項再填寫本頁) 裝 訂! 線· 550997 A7 -------2Z------— 五、發明說明(h ) 硬化狀態的熱硬化性樹脂所構成之電氣絕緣層的厚度方向 形成導通孔;以前述配線基板在外側的方式/將前述元件埋 設至前述電氣絕緣層;使前述電氣絕緣層硬化。 〔圖式之簡單說明〕 圖1爲本發明之實施形態1之元件內藏模組的截面圖 0 圖2A〜E爲本發明之實施形態2之元件內藏模組的製 程的截面圖。 圖3爲本發明之實施形態3之元件內藏模組的截面圖 〇 圖4爲本發明之實施形態4之元件內藏模組的截面圖 〇 圖5爲本發明之實施形態5之元件內藏模組的截面圖 〇 圖6爲本發明之實施形態6之元件內藏模組之製程的 截面圖。 圖7A〜C爲本發明之實施形態7之元件內藏模組的截 面圖。 圖8爲本發明之實施形態8之元件內藏模組的截面圖 〇 圖9爲本發明之實施形態9之元件內藏模組的截面圖 〇 圖10爲本發明之實施形態10之元件內藏模組的截面 圖。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐1 -------------裝—— (請先閱讀背面之注意事項再填寫本頁) ^-r«»J. 線 _6_______ 550997 A7 ____B7____________ 五、發明說明(W ) 圖11爲本發明之實施形態11之元件內藏模組之製程 的截面圖。 圖12爲本發明之實施形態12之元件內藏模組之製程 的截面圖。 〔發明之詳細說明〕 本發明,爲一種元件內藏模組,其係含有··電氣絕緣 層、在前述電氣絕緣層的兩表面上一體化形成之配線、及 用以連接前述配線間之導通孔,於前述電氣絕緣層的內部 ,埋設有選自電子元件及半導體之至少一種元件所成者。 前述配線之至少一方,係配線基板;埋設於前述電氣絕緣 層的內部之元件,係於埋設之前搭載於前述配線基板上且 構成一體化。藉此,於內藏前可對半導體等之元件作構裝 檢查或特性檢查。其結果,可提高良率。又,由於係使配 線基板一體化後埋設,故強度可提高。且可提供生產性高 、並可高密度構裝的元件內藏模組。於前述中所謂之埋設 ,係謂完全埋設到前述電氣絕緣層的內部。 本發明之前述配線基板以兩面基板或多層配線基板爲 佳。藉此,可容易地形成複雜的配線。 又,於本發明中,以將前述電氣絕緣層內部的電子元 件及/或半導體(以下,總稱爲「元件」)構裝到前述電氣絕 緣層的兩主平面的配線圖案及/或配線基板爲佳。藉由將元 件構裝到兩主平面上,且內藏於電氣絕緣層,可提供元件 內藏層爲更高密度的模組。 又,於本發明中,以使前述元件對於前述電氣絕緣層 7 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁} I · I I I---—訂·--------線· 550997 A7 -------B7___ 五、發明說明(5 ) 的主平面之法線方向爲錯開而配置爲佳。藉此,可較構裝 機的元件構裝間隔,更高密度地配置元件。且可減低電氣 絕緣層的厚度,而有益於高密度化。 又’以在配置於前述電氣絕緣層內部、構裝於前述電 氣絕緣層的兩主平面之配線圖案及/或配線基板的元件間插 入遮蔽層爲佳。藉此,可使內藏之元件間的干涉、來自外 部對內藏元件的干涉、自內藏元件往外部的放射之任一者 或全部減低,可提升模組的特性。 又’前述遮蔽層,以金屬箔配線圖案或電磁遮蔽材爲 佳。於使用金屬箔配線圖案的場合,可用與形成配線圖案 的相同製程來形成遮蔽層,容易進行生產。於使用電磁遮 蔽材的場合’只要變更電氣絕緣層的材質即可作成,製程 不須改變而可使干涉減低。 又,以在與前述配線圖案及/或配線基板的前述電氣絕 緣層的相反側之主平面構裝元件爲佳。藉此,不僅在電氣 絕緣層,在相反側的主平面亦可構裝元件,可謀求高密度 化。 又,前述電子元件以分立(discrete)元件爲佳。藉此, 內藏之元件不須新開發,可提高模組本身的開發速度。且 可利用現有的分立元件的可靠性與精度’而提升模組的特 性。前述所謂之分立元件,係例如電感器、電容器、電阻 等之泛用晶片元件。於後文中,將電感器、電容器及電阻 統稱爲「LCR」。 又,前述半導體以半導體裸晶片爲佳。藉此’與半導 _ _ 8__—________ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) I------------ (請先閱讀背面之注意事項再填寫本頁) 訂_ -線· 550997 A7 _____Β7______ 五、發明說明(b ) 體封裝體比較,可用更低面積作成模組,而可提供高密度 的模組。 又,前述半導體裸晶片,以藉由倒裝片接合方式連接 至前述配線圖案及/或配線基板爲佳。藉此,可謀求短配線 化與高密度構裝化。 又,前述半導體裸晶片,以經硏削或硏磨加工爲佳。 藉此,可減低半導體的厚度,具有降低模組高度的效果。 前述製造方法中,於使前述電氣絕緣層硬化之製程後 ,以含有將元件構裝到配線圖案及/或配線基板之製程爲佳 。藉此,可有效率地製造本發明之元件內藏模組。 又,於構裝前述半導體之前,以將半導體晶圓施以硏 削及/或硏磨爲佳。藉此,可使半導體的薄型化於晶圓狀態 一倂進行,而可提高生產性。 又,於構裝前述半導體後,以將配線板固定及輸送來 進行硏削及/或硏磨爲佳。藉此,不須處理薄型化之半導體 即可製造本發明之元件內藏模組。 又,將前述元件埋設到電氣絕緣層之製程,與使前述 電氣絕緣層硬化之製程以同時進行爲佳。藉此,可減少製 程數而製造本發明之元件內藏模組。 又,前述遮蔽層之形成製程,以藉由形成銅箔配線圖 案來進行爲佳。藉此,可有效率地製造本發明之元件內藏 模組。 又,前述遮蔽層之形成製程,以藉由進行電磁遮蔽層 之積層來進行爲佳。藉此,可有效率地製造本發明之元件 9 中國國家標準(CNS)A4規格(210 X 297公ϋ ' — (請先閱讀背面之注意事項再填寫本頁) 訂· --線· 550997 A7 ___B7___ 五、發明說明(Ί) 內藏模組。 --------------裝--- <請先閱讀背面之注意事項再填寫本頁) 又,於本發明中,使元件於前述電氣絕緣層內部呈對 向配置亦可。尤其是’在高度高的元件與低的元件混合存 在之場合,若使高度低的元件呈對向配置,則可高密度地 塡充。 又,前述電氣絕緣層的厚度方向之熱膨脹係數設爲導 通孔的熱膨脹係數的1〇倍以下亦可。這樣做,則於元件內 藏模組的外側進一步搭載元件之場合,例如,即使經過熔 焊製程,電氣絕緣層的厚度方向的膨脹率也不致於變成太 大,故不會破壞到導通孔的導通。 (實施形態1) 以下’就本發明之實施形態參照圖式加以說明。圖i 爲本發明之實施形態1之元件內藏模組的截面圖。於圖1 中’兀件內藏模組,具有:電氣絕緣層1〇1、配線圖案1〇2 、導通孔103、元件1〇4、與焊料1()5,並進一步包含兩面 基板109,具有配線圖案106、1〇8、與內導通孔1〇7。 電氣絕緣層101,可用例如,絕緣性樹脂、及塡料與 絕緣性樹脂的混合物等。電氣絕緣層,含有樹脂與塡料, 塡料含有量以50質量%〜95質量%爲佳。又,若有玻璃布 等之補強材料亦可。作爲絕緣性樹脂,可用熱硬化性樹脂 丄熱=性樹脂、光硬化性樹脂等,藉由使用耐熱性高的環 氧樹脂或酿酸樹脂、異氰酸酯樹脂,可提高電氣絕緣層 101的耐熱性。χ,藉由使用含有低介電觀因數的氟樹 脂例如聚四氟乙烯(pTFE樹脂)、PP〇(PGlyphenylene oxide 度適用中國- 550997 A7 五、發明說明(,?) •聚本酸)樹脂(亦稱爲PPE(Polyphenylene ether)樹脂)、液 晶聚合物,或將此等樹脂改質之樹脂,可提升電氣絕緣層 的局頻特性。作爲電氣絕緣層101,於使用塡料與絕緣性 樹脂的混合物之場合,藉由選擇塡料及絕緣性樹脂,可容 易地控制電氣絕緣層101的線膨脹係數、熱傳導度、介電 率等。例如,可使用氧化鋁、氧化鎂、氮化硼、氮化鋁、 氮化矽、聚四氟乙烯、及二氧化矽等作爲塡料。藉由使用 氧化鋁、氮化氟、氮化鋁,可製作成較習知的玻璃_環氧基 板熱傳導度爲高的基板,可使內藏之元件104的發熱有效 地進行放熱。又,氧化鋁具有成本低的優點。於使用二氧 化砍的场合’可製得介電率低的電氣絕緣層1 〇 1,由於比 重亦輕,以用作爲行動電話等之高頻用途爲佳。使用氮化 矽或聚四氟乙烯(例如,鐵氟龍(杜邦公司註冊商標))亦可形 成介電常數低的電氣絕緣層。又,藉由使用氮化硼,可減 低線膨脹係數。亦可更進一步含有分散劑、著色劑、耦合 劑或離型劑。藉由分散劑,可使絕緣性樹脂中的塡料均一 性良好地分散。藉由著色劑,由於可對電氣絕緣層著色, 可使自動辨識裝置的使用變得容易。藉由耦合劑,由於可 使絕緣性樹脂與塡料的接合強度提高,而可提高電氣絕緣 層101的絕緣性。藉由離型劑,由於可提高模具與混合物 的離型性,故可提高生產性。 配線圖案102,係由具有電傳導性之物質所構成,可 使用例如金屬箔或導電性樹脂組成物、以金屬板加工而成 之導線架。藉由使用金屬箔或導線架,可藉由蝕刻而容易 __ 11 _ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) ---1---!11! ^^ · I I (請先閲讀背面之注意事項再填寫本頁) · •線 550997 A7 ___B7____ 五、發明說明(1 ) (請先閱讀背面之注意事項再填寫本頁) 地作成微細的配線圖案。又,於金屬箔中,亦可藉由用離 型膜之轉印等來形成配線圖案。尤其以銅箔的成本低且電 傳導性高,爲較佳者。又,藉由在離型膜上形成配線圖案 ,使得配線圖案易於處理。又,藉由使用導電性樹脂組成 物,藉由網版印刷等之配線圖案的製作亦成爲可能。藉由 使用導線架,而可使用電阻低、有厚度之金屬。又,可使 用藉由蝕刻之微細圖案化或衝孔加工等之簡易的製造法。 又,藉由在此等配線圖案102的表面進行電鍍處理,可使 耐蝕性與電傳導性提高。又,藉由對配線圖案102與電氣 絕緣層101的接觸面之粗化,可提高與電氣絕緣層101的 接合性。又,亦可用配線圖案來形成耦合器或濾波器。配 線圖案102,亦可在表層側構裝半導體及/或電子元件。 -線_ 導通孔103具有連接配線圖案102之間的機能,係由 例如熱硬化性的導電性物質構成。作爲熱硬化性的導電性 物質,可使用例如,將金屬粒子與熱硬化性樹脂混合所成 之導電性樹脂組成物。作爲金屬粒子,可使用金、銀、銅 或鎳。金、銀、銅或鎳由於導電性高故爲較佳,尤以銅, 其導電性高且移動(migration)少,故特佳。即使使用銅以 銀被覆之金屬粒子,移動少且導電性高兩者的特性都可滿 足。作爲熱硬化性樹脂,可使用例如,環氧樹脂、酚醛樹 脂或異氰酸酯樹脂。環氧樹脂,因耐熱性高,尤其較佳。 又,導通孔103,可藉由於導通孔形成後進行電鍍來形成 。又,亦可藉由金屬與焊料的組合等來形成。 電子元件104,可使用例如,電容器、電感器、電阻 一 __12_______ 木紙張尺度適用中國國家標準(CNS)A4規袼(210 X 297公釐) 550997 A7 __ B7 __ 五、發明說明(ιϋ) (LCR)等之晶片兀件,或二極體、熱敏電阻、開_等。因 係將分立元件內藏,不須新開發內藏元件。又,按照精度 及溫度特性等用途,元件可使用現有的元件’有益於可靠 性的提高。又,亦可形成印刷電阻或薄膜電容器·電感器 等。 焊料105,係用以將電子元件104構裝到配線圖案102 上。於使用高溫焊料之場合,可防止將模組藉由瑢焊進行 構裝之際之焊料的再熔融。又,由於使用無鉛焊料,環境 的負荷可得以減輕。於本實施形態中係使用焊料,惟,亦 可使用導電性黏著劑等。 作爲兩面基板109,可由:使玻璃織物含浸環氧樹脂 而成之基板(玻璃_環氧樹脂基板)、使芳族聚醯胺纖維不織 布含浸環氧樹脂而成之基板(芳族聚醯胺-環氧樹脂基板)、 使紙含浸酚醛樹脂而成之基板(紙酚醛基板)、陶瓷基板等 之任意的基板,依目的而選擇使用。 例如將使用玻璃-環氧樹脂基板之兩面基板上搭載元件 ,進行檢查,然後,埋設電氣絕緣層所成之元件內藏模組( 實施形態1),和不使用基板而將元件以單體埋設電氣絕緣 層,然後,在表面形成配線圖案所成之模組,作兩者的強 度之比較,其結果雖因基板的種類、複合成分之陶瓷的種 類、量、厚度等而異,平均而言,實施形態1方面的彎曲 強度約高達1.3倍。 (實施形態2) 於此實施形態2,係就圖1所示之元件內藏模組的製 (請先閱讀背面之注意事項再填寫本頁) 訂: -·線· _13__ 紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公f ) 550997 A7 __B7______ 五、發明說明(·Λ ) (請先閱讀背面之注意事項再填寫本頁} 造方法之一實施形態加以說明。於實施形態2中所用的材 料,係於實施形態1中所說明者。圖2A〜圖2D爲顯示元 件內藏模組的製程的一實施形態之截面圖。如圖2A所示 般,在未硬化的電氣絕緣層201上形成貫通孔207。作爲 電氣絕緣層201,可使用絕緣性樹脂、或絕緣性樹脂與塡 料的混合物。首先,將塡料與絕緣性樹脂混合,藉由攪拌 ’來製作糊狀的絕緣性樹脂混合物。亦可對絕緣性樹脂混 合物添加用以調整黏度之溶劑。藉由將此絕緣性樹脂混合 物成形爲片材形狀,可形成電氣絕緣層201。作爲成形爲 片材形狀的方法,可藉由刮刀(doctor blade)法等,在薄膜 上作成。電氣絕緣層201,藉由在硬化溫度以下使其乾燥 ’可降低黏著性。藉由此熱處理,板狀的電氣絕緣層的黏 著性會喪失,故可容易地與薄膜剝離。藉由作成爲半硬化 狀態(B階),操作會變得容易。貫通孔207的形成,可藉 由例如’雷射加工或鑽孔加工、衝孔加工來製作。雷射加 工’可形成微細間距的導通孔,且不會產生切削屑,故爲 較佳。於雷射加工的場合,可使用二氧化碳雷射、YAG雷 射或準分子雷射等。又,於鑽孔加工、衝孔加工的場合, 可使用泛用性的現有設備容易地形成貫通孔。由於係使用 未硬化狀態的電氣絕緣層201,加工變得容易。 另外’備妥於載體206上形成有配線圖案202者。配 線圖案202 ’可使用蝕刻、印刷之類的方法來形成。尤其 Μ用纟虫刻法時’可利用微影工法等微細的配線圖案之形成 法。作爲載體,可用ΡΕΤ(聚對苯二甲酸乙二醇酯)或PPS( _______14_
幸、紙張尺度適用中國國家標準(CNS)A4規格( 公H 550997 A7 _ B7 ___ _------------ 五、發明說明(\>) 聚苯硫)之類的樹脂薄膜,及其他之銅泊、錯泊之類的金屬 箔。藉由使用載體206,配線圖案202的利用會變得容易 。又,在配線圖案202與載體206之間亦可設有用以使配 線圖案202容易剝離之剝離層。 在兩面配線基板211(具有連接配線圖案208、210及 其間之內導通孔209)上之配線圖案208,將兀件204藉由 焊料205構裝於其上,然後,完成選自構裝檢查及特性檢 查之至少一種的檢查。於配線圖案21 〇的下側預先以保護 膜被覆212亦可。 其次,對圖2A中所作成的貫通孔207充塡導電性導 通孔糊料。導電性導通孔糊料爲導電性粉末與樹脂的混合 物,可用金、銀、銅、鎳等之金屬粉’或碳粉與熱硬化性 樹脂或光硬化性樹脂的混合物。於使用銅之場合’導電性 高,且移動性小,故較佳。又,亦可使用將粉末以銅被覆 所成之導電性粉末。作爲樹脂,可使用熱硬化性樹脂,例 如,環氧樹脂、酚醛樹脂、異氰酸酯樹脂、聚苯醚等。尤 以環氧樹脂因耐熱性高爲特佳。又,亦可使用光硬化性樹 脂。導通孔糊料的塡充,可用藉由印刷或注入的方法。尤 其是於印刷的場合,亦可進行配線圖案的形成。由於形成 導通孔203,配線圖案202與208間可得以連接。又,亦 可預先形成用以在電氣絕緣層201內藏電子元件204的空 間。藉由空間之形成,可抑制導通孔203之變形。 作爲將元件204構裝到兩面配線基板211(具有連接配 線圖案208、210及其間之內導通孔209)上之配線圖案208 _______ 15 木紙張尺度適用中國國家標準(CNS)A4規格(21〇 χ 297公釐) ----I------------ (請先閱讀背面之注意事項再填寫本頁) •irOJ· 線· 550997 A7 __ ___B7 _____ 五、發明說明(A ) 的方法,除了使用焊料205之焊料構裝(膏狀焊料之印刷或 焊球)之外,亦可使用導電性黏著劑,例如,將金、銀、銅 、銀-鈀合金等以熱硬化性樹脂混練而成者。又,於所構裝 之電子元件204與兩面配線基板211之間,亦可注入密封 劑。藉由密封劑之注入,在後續製程中將電子元件204埋 設到電氣絕緣層201之時,可防止間隙之產生。密封樹脂 ,可用通常於倒裝片接合中所使用之底塡(under fill)樹脂 。構裝後,藉由檢查構裝狀態,可進行修復或不良原因的 解析。 將具有塡充有導電性導通孔糊料的導通孔203之電氣 絕緣層201配置於中央,於上側配置形成於載體206上之 配線圖案202,於下側配置構裝有電子元件204的兩面基 板211,將此等以圖2B所示般對位進行積層。 於圖2B的積層後,如圖2C所示般,可藉由加壓,將 電子元件204埋設到電氣絕緣層201中。於絕緣性樹脂使 用熱硬化性樹脂之場合,於加壓後,藉由加熱,可使電氣 絕緣層201中的熱硬化性樹脂硬化,可形成埋設有電子元 件204之板狀的電氣絕緣層201。加熱,可於熱硬化性樹 脂之硬化溫度以上的溫度進行。藉由此製程,電氣絕緣層 2〇1與元件204會機械性地強固地接合。又,於藉由加熱 使熱硬化性樹脂硬化之際,藉由一邊加熱一邊施加 l〇〇g/mm2〜2kg/mm2的壓力,可提高半導體裝置的機械強度 。又,亦可不使用片材形狀的電氣絕緣層,而於加工成粉 末或粒狀之後,使其熔融流入模具中。又,亦可於粉末的 16___— 一 木紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --------------裝--- (請先閱讀背面之注意事項再填寫本頁) 訂: 線· 550997 A7 ____B7 __ 五、發明說明(K ) 狀態流入之後,進行熔融成形。作爲絕緣性樹脂層之注入 方法,可使用傳遞模塑(transfer mold)或射出成形。 於電氣絕緣層201硬化後,將載體206剝離,成爲內 藏有電子元件204之電氣絕緣層201,可形成如於實施形 態1中所說明般之由兩面基板211 —體化所成之半導體裝 置。 (實施形態3) 於實施形態3,就元件內藏模組的一實施形態加以說 明。以下,就本發明之實施形態,參照圖3加以說明。有 關本實施形態之元件內藏模組,除了半導體306、突塊307 、3層配線基板308諸部分以外,係與上述之實施形態1 相同。因而,實施形態3中所使用之材料,只要是未另加 說明係與實施形態1、2相同。於圖3中,元件內藏模組, 具有電氣絕緣層301、配線圖案302、導通孔303、電子元 件304、導電性黏著劑305、半導體306、突塊307及3層 配線基板308。 半導體306係與電子元件304同樣地構裝於配線基板 308上。藉由將半導體306內藏於電氣絕緣層301中,可 謀求模組之高機能化。半導體306,可用例如,電晶體、 1C、LSI等之半導體元件。半導體306,可爲封裝體,亦可 爲半導體裸晶片。又,半導體306,亦可使用密封樹脂, 將半導體306,或半導體306與突塊307、配線基板308的 連接部之至少一部份密封。藉由密封樹脂的注入,可於將 半導體306埋設於電氣絕緣層301時,防止半導體306與 ____17_____ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ----I--I--I------ (請先閱讀背面之注意事項再填寫本頁) · ;線· 550997 A7 ______B7__ 五、發明說明(A ) (請先閱讀背面之注意事項再填寫本頁) 配線基板308之間產生間隙。密封樹脂,可使用通常使用 於倒裝片接合時所使用之底塡樹脂。配線基板308與半導 體306的連接,作爲倒裝片接合用者,可用導電性黏著劑 、異向性導電膜(ACF)、非導電性膜(NCF)與突塊。又,由 於係使用晶片尺寸封裝體(CSP),故構裝變得容易。 突塊307係連接半導體306與配線基板308。可使用 例如,金或銅、焊料等之金屬。突塊307,可藉由引線接 合、電鍍、印刷等來形成。 -·線- 配線基板308,係一般的配線基板之玻璃環氧樹脂基 板或陶瓷基板所構成之兩面基板、合成基板或以內導通孔 連接的多層板等,爲由電氣絕緣層與配線圖案及導通孔所 構成。電氣絕緣層’爲絕緣性樹脂、或塡料與絕緣性樹脂 的混合物、陶瓷,此外,亦可加入玻璃布等之補強劑。又 ,實施形態1、2爲相同材料亦可。有關配線圖案及導通孔 亦同。由於係使用與電氣絕緣層301相同的材料,熱膨脹 係數爲相同數値’故可提高可靠性。又,於埋設電氣絕緣 層之前,須先對配線基板308與半導體306及電子元件 304的構裝狀態加以檢查。藉此,製品的良率可提高,且 可進行修復或不良的原因解析。於將電子元件304與半導 體306雙方構裝後,進行檢查之場合,可確認半導體306 的動作,是有效的方法。藉由配線基板308,對於複雜的 電路的適應’或半導體裝置的再配線變得容易,可作成爲 適合於複雜的機能之模組的構造。 又,於本實施形態中,配線基板的配線圖案雖係作成 ___ _____18 本紙張尺度適用中國國家標準(CNS)A4規格(210x 297公釐)_ ' 一 "~ 550997 A7 ___ B7__ 五、發明說明(丄) 爲3層,惟,並非用以限定層數,而可使用任意的層數。 (請先閱讀背面之注意事項再填寫本頁) 例如,於用玻璃-環氧樹脂基板之3層基板上搭載元件 ’進行檢查,然後,對埋設於電氣絕緣層的元件內藏模組( 實施形態3),與未使用基板而將元件單體埋設到電氣絕緣 層,然後,再於表面形成配線圖案之模組,作兩者的強度 之比較,其結果雖因基板的種類、複合成分之陶瓷的種類 、量、厚度等而異,平均而言,實施形態3方面的彎曲強 度約高達1.3倍。 (實施形態4) 於實施形態4,係就元件內藏模組的一實施形態加以 說明。以下,就本發明之實施形態,參照圖4加以說明。 有關本實施形態之元件內藏模組,除了兩面係使用3層配 線基板408,電子元件304與半導體306係作成爲呈對向 配置之外,係與上述實施形態1〜3相同。因而,於本實施 形態中,有關未特別加以說明者,係與實施形態1〜3爲相 同,有關同樣名稱的構成零件及製造法,只要未特別加以 說明者,係具有同樣的機能。 配線基板408,與實施形態3相異之處在於作成上下 兩方配置,使其對於複雜的配線的適應及半導體的再配線 等變得容易,可作成爲適合於複雜的機能之模組的構造。 又,只要在通常的模組作成之將半導體及電子元件構裝到 配線基板上的製程後,附加以將半導體及電子元件內藏之 製程,即可形成高密度的元件內藏模組。 (實施形態5) _____19 __ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 550997 A7 __B7____ 五、發明說明(1) 於實施形態5,就元件內藏模組的一實施形態加以說 明。以下,就本發明之實施形態,參照圖5加以說明。有 關本實施形態之元件內藏模組,除了構裝於表層之電子元 件510、半導體506、與元件內藏層有關諸部分以外,係與 上述實施形態1〜4相同。因而,於本實施形態中,有關未 特別加以說明者,係與實施形態1〜4爲相同,有關同樣名 稱的構成零件及製造法,只要未特別加以說明者,係具有 同樣的機能。 電氣絕緣層501內之電子元件504,與實施形態4同 樣地係於通常的模組作成之構裝製程中構裝,用以構裝電 子元件504之安裝性能上,無論如何,須於電子元件與電 子元件之間設置間隔。於本實施形態中,考量到相對向之 配線基板508上之元件的構裝間隔,而將電子元件504的 位置錯開配置。藉此,在同一面積可構裝的元件數可增大 ,同時可將內藏層的厚度方向作薄,可作成適合於更高密 度構裝之構造。509爲非導電性膜(NCF)。 構裝於表層之電子元件510、半導體506,可在與通常 之模組作成之相同製程構裝,由於構裝面之增加,可更高 密度地構裝,作成適合於多機能的模組之構造。 (實施形態6) 於實施形態6,就元件內藏模組的一實施形態加以說 明。以下,就本發明之實施形態,參照圖6加以說明。有 關本實施形態之元件內藏模組,除了構裝於表層之電子元 件610、612、半導體611、613、與元件內藏層有關諸部分 ___20_ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) -裝--------訂---------線 _· 550997 A7 _____B7 ____ 五、發明說明((g ) 以外,係與上述實施形態1〜5相同。因而,於本實施形態 中,有關未特別加以說明者,係與實施形態1〜5爲相同’ 有關同樣名稱的構成零件及製造法,只要未特別加以說明 者,係具有同樣的機能。 電氣絕緣層601內之電子元件604、半導體606 ’與實 施形態4、5同樣地係於通常的模組作成之構裝製程中構裝 ,惟,於對半導體606進行倒裝片構裝之際,必須要有用 以進行再配線之空間,無論如何,是不易接近地配置電子 元件。於本實施形態中,由於係將電子元件604構裝到呈 對向配置之配線基板608,故半導體606之接近地配置成 爲可能。藉此,在同一面積可構裝的元件數可增加,可作 成適合於更高密度構裝之構造。609係密封樹脂。 構裝於表層之電子元件610、半導體606,可於與通常 的模組作成之構裝製程之相同製程中構裝。由於係構裝於 兩表層面,可更高密度地構裝,作成適合於多機能的模組 之構造。 (實施形態7) 於實施形態7,就元件內藏模組的一實施形態加以說 明。以下,就本發明之實施形態,參照圖7A〜C加以說明 。實施形態7中所用之材料,有關未特別加以說明者,係 與上述之實施形態相同,有關同樣名稱的構件及製法,只 要未特別加以說明者’係具有同樣的機能。 圖7A〜圖7C爲表示元件內藏模組之製造製程的一實 施形態之截面圖。如圖7A般’將構裝有半導體706、電子 21 度適用中國國家標準(CNS)A4規格(21Gx 297公釐) " " ---------I----· I I (請先閱讀背面之注意事項再填寫本頁) 一5J» . •線· 550997 A7 ----B7_____ 五、發明說明(J ) 元件704之配線基板708,與形成有導通孔703、空隙710 之電氣絕緣層701對位且進行積層。配線基板708,於構 裝後,作構裝檢查,亦可進行修復。藉由使形成於電氣絕 緣層701上之空隙710作成爲與內藏之半導體706、電子 元件704的體積相同或以下,可防止內藏時產生間隙。 其次,如圖7B所示般,於積層後,藉由加壓,可將 半導體706、電子元件704埋設於電氣絕緣層701。埋設後 ,進行加熱,使電氣絕緣層701硬化。且,使配線圖案 702間以導通孔703連接。 於使電氣絕緣層701硬化後,如圖7C所示般,藉由 將半導體711 ' 713及電子元件714、712構裝到表層,可 提供元件內藏模組。 (實施形態8) 於實施形態8,就元件內藏模組的一實施形態加以說 明。以下,就本發明之實施形態,參照圖8加以說明。有 關本實施形態之元件內藏模組,除了關於元件內藏之部分 以外,係與上述實施形態1〜7相同。因而,於本實施形態 中,有關未特別加以說明者,係與實施形態1〜7爲相同, 有關同樣名稱的構成零件及製造法,只要未特別加以說明 者,係具有同樣的機能。 電氣絕緣層801內之電子元件804與半導體806,係 於通常的模組作成之構裝製程中構裝,惟,藉由構裝於配 線基板808的兩面,可容易地增加元件內藏層。亦即,於 3層配線基板808的上側,透過配線圖案802連接電子元 _22_ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) ----訂---------線 550997 A7 ___B7____ 五、發明說明(/ ) 件810、半導體811,於3層配線基板808的下側亦連接埋 設有電子元件之電氣絕緣層’再將電子元件812連接到其 表面。 藉此,可增加在同一面積之可構裝的元件數,可作成 適合於更高密度構裝之構造。 (實施形態9) 於實施形態9,就元件內藏模組的一實施形態加以說 明。以下,就本發明之實施形態,參照圖9加以說明。有 關本實施形態之元件內藏模組,除了關於半導體之薄型化 之部分以外,係與上述實施形態1〜8相同。因而’於本實 施形態中,有關未特別加以說明者,係與實施形態1〜8爲 相同,有關同樣名稱的構成零件及製造法,只要未特別加 以說明者,係具有同樣的機能。 藉由將半導體906薄型化,可減低元件內藏模組的厚 度。薄型化,可使用在半導體晶圓施以硏磨後進行構裝的 方法,或於將半導體構裝於配線基板908後之硏削/硏磨方 法來達成。於前者之場合,由於可將半導體906以晶圓單 位進行加工,故於生產性方面有利。於後者之場合,由於 不須處理經薄型化之半導體906,故作業性可提高。又, 半導體906不只是構裝於表層,構裝於內部亦可。 (實施形態10) 於此實施形態10,就元件內藏模組的一實施形態加以 說明。以下,就本發明之實施形態,參照圖10加以說明。 有關本實施形態之元件內藏模組,除了形成遮蔽電極之部 ^氏張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ----------------- (請先閱讀背面之注意事項再填寫本頁) · 550997 A7 _B7______ 五、發明說明(Μ) 分以外,係與上述實施形態1〜9相同。因而,於本實施形 態中,有關未特別加以說明者,係與實施形態1〜9爲相同 ,有關同樣名稱的構成零件及製造法’只要未特別加以說 明者,係具有同樣的機能。1〇〇9爲異向性導電膜(ACF)。 遮蔽電極1010,可藉由與配線圖案1002之同樣的材 料、製程來形成。藉由形成遮蔽電極1010 ’可減低內藏之 半導體1006及電子元件1004間的電磁波的干涉。藉由將 遮蔽電極1010作成爲接地電位,可謀求模組的安定化。又 ,遮蔽電極並非限定於1層。 (實施形態11) 於實施形態11,就元件內藏模組的一實施形態加以說 明。以下,就本發明之實施形態,參照圖11加以說明。有 關本實施形態之元件內藏模組,除了形成電磁遮蔽層1110 之部分以外,係與上述實施形態1〜1〇相同。因而’於本實 施形態中,有關未特別加以說明者,係與實施形態1〜10爲 相同,有關同樣名稱的構成零件及製造法’只要未特別加 以說明者,係具有同樣的機能。 電磁遮蔽層1110,僅藉由變更電氣絕緣層1101的塡 料,即可減低內藏之半導體1106及電子元件1104間的電 磁波的干涉。作爲塡料,可使用導磁率的複數成分高、且 可吸收電波(轉換成熱)之材料。例如,可用鐵氧體的粉末 等。於與電氣絕緣層1101之相同的製程中,可追加賦予遮 蔽機能。又,電磁遮蔽層並非限定爲1層。 (實施形態12) _____24___ 衣紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ----I--— — — — — — — I I (請先閱讀背面之注意事項再填寫本頁) · ;線· 550997 A7 __________B7 _____ 五、發明說明(yv) 於實施形態12,就元件內藏模組的一實施形態加以說 明。以下,就本發明之實施形態,參照圖12加以說明。有 關本實施形態之元件內藏模組,除了關於電氣絕緣層1201 內的電子元件1204a、1204b之部分以外,係與上述實施形 態1〜11相同。因而,於本實施形態中,有關未特別加以說 明者’係與實施形態1〜1相同,有關同樣名稱的構件及製 法’只要未特別加以說明者,係具有同樣的機能。 電氣絕緣層1201內之電子元件1204a、1204b,與實 施形態4同樣地,係於通常的模組作成之構裝製程中構裝 ,惟’由於例如電容器等之容量,電子元件的尺寸非爲均 一的情形甚多。於本實施形態中,有效地利用電子元件 1204a、1204b的高度之差異,可提高構裝密度。如圖12 般’將高度低的電子元件1204a的元件相對向構裝,可有 效地利用通常會被浪費掉的電子元件1204a的上部空間, 可作成適合於更高密度構裝的構造。構裝於表層之電子元 件1204、半導體1206,可藉由與通常之模組作成之相同的 製程來構裝,由於構裝面之增加,可更高密度地構裝,作 成適合於多機能的模組之構造。 如上述說明般,依據本發明,可提供一種元件內藏模 組’其係含有:電氣絕緣層、在前述電氣絕緣層的兩主平 面上形成之配線圖案、及用以連接前述配線圖案間之導通 孔,並將構裝於前述配線圖案之電子元件及/或半導體配置 於前述電氣絕緣層的內部所成者,藉此,可提供將電子元 件及/或半導體內藏於電氣絕緣層,厚度可作薄、可高密度 ___25 _ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝 訂· i線- 550997 A7 _ B7____ 五、發明說明(Ί) 構裝之元件內藏模組。 (實施例1) 於本實施例中,將電氣絕緣層以下述的製程製作。將 熱硬化性的液狀環氧樹脂與作爲塡料之Si〇2,將塡料以質 量比70%的比例秤量,藉由攪拌混合機’製作成混合糊料 。將製作成之混合糊料,使用刮刀法在聚對苯二甲酸乙二 醇酯(PET)的離型膜(厚度:75μ m)上,加工成700μ m厚 度的片材形狀。於加工成片材狀之後,經過l〇5°C的乾燥 製程,作成未硬化狀態的電氣絕緣層。液狀環氧樹脂與塡 料的質量比,可選擇爲可維持片材的形狀之96%(塡料的質 量比)以下。片材的厚度,以易於進行乾燥製程之200μ m 以下爲佳,惟,按照內藏元件的高度,來形成厚的片材, 或於片材形成後藉由積層可得到所要的厚度。 其次,在對應於內導通孔之位置,使用二氧化碳雷射 形成貫通孔(直徑φ150μ m)。於形成貫通孔後,以銅粉(粒 徑:小於7μ m)與熱硬化性樹脂的混合物之導通孔糊料進 行印刷塡充。印刷塡充係使用擠壓棒,以PET膜作爲遮罩 。貫通孔徑,以較小者較適合於高密度構裝,實用上可使 用600μ m以下的尺寸者。 與上述製程並行,於PET載體膜(厚度:75μ m)上藉 由黏著劑黏合15μ m厚的銅箔(單面粗化)以疊合機 (laminator)貼合,藉由紫外線曝光、顯影、使用氯化亞鐵 之蝕刻,形成配線圖案。作爲配線設計規則,係使最小 L/S(線寬/線距)作成爲1〇〇/ι〇〇(μ m),L/s亦以較小者適合 __ 26_ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱)--- (請先閱讀背面之注意事項再填寫本頁) 裝 -l5J· -線 550997 A7 ___ —_B7 五、發明說明(、斗) 於高密度構裝,於構裝半導體裸晶片之場合,以2〇〇/2〇〇 /z m以下爲妥。 --I I I I I I I I--I I I (請先閱讀背面之注意事項再填寫本頁) 再將電子元件及/或半導體構裝於配線圖案上。電子元 件之構裝係使用導電性黏著劑。將導電性黏著劑藉由網版( 網目:#400/吋)塗布於配線圖案上,配置1〇〇5尺寸的電子 元件後,使用乾燥機(溫度:150°C)進行硬化。作爲電子元 件,係按照所要構成之模組,使用LCR等之晶片元件與熱 敏電阻或二極體。內藏之電子元件的尺寸亦以較小者適合 於高密度構裝,以1.6mm(3216尺寸)以下爲佳。半導體之 構裝,於封裝體之場合,係與電子元件同樣地使用導電性 黏著劑。又,於裸晶片之場合,係形成金突塊,再進行倒 裝片構裝。又,於配線基板亦同樣地構裝電子元件及/或半 導體。 --線· 對構裝好之電子元件,進行外觀檢查,對於有構裝缺 失(元件脫離或元件突出)的處所加以修復。亦對構裝好之 半導體藉由電氣連接之檢查來確認其構裝狀態。然後,進 行電路區塊的機能檢查,確認半導體本身的特性。對特性 不良的處所,進行元件之交換。 將上述製程中製作之構裝有電氣絕緣層及/或半導體之 配線圖案,以辨識標記爲基準可進行對位,加以積層、並 加壓。藉由加壓(5MPa)可將電氣絕緣層、電子元件及/或半 導體埋設到電氣絕緣層。於埋設後,在同壓力下,一邊加 熱,一邊以溫度:200°C、時間:2小時,進行加熱’使電 氣絕緣層硬化之同時將配線圖案轉印。 _27 _____ 木紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 550997 A7 ___B7 _____ 五、發明說明(/) (請先閱讀背面之注意事項再填寫本頁) 於電氣絕緣層的硬化後,將PET載體剝離,形成元件 內藏模組。此元件內藏模組,在表層具有用以構裝電子兀 件及/或半導體之空間,於內部亦配置有電子元件及/或半 導體,若將本實施例之元件內藏模組與通常的2維(表面) 構裝品以同樣面積加以比較,則本實施例的模組可構裝約 2倍的元件。反之,於欲構裝和通常的2維(表面)構裝品之 同數目的元件之場合,本實施例的模組’約一半的大小即 可。 (實施例2) 於本實施例中,以圖12所示般的構造製作成試料。其 係在內藏有電子元件之電氣絕緣層的上下配置配線基板之 構造,以導通孔連接上下的配線基板間。電子元件’係用 0603尺寸的晶片元件。電氣絕緣層,係以Si〇2作爲塡料 ,藉由質量比之調整,製作成使熱膨脹係數變化之試料。 電氣絕緣層的厚度爲400//m。配線基板係用玻璃環氧樹脂 基板(A基板),以及與電氣絕緣層爲相同材料所形成之配 線基板(B基板)。配線基板的厚度爲400〆m °導通孔係銅 粉與樹脂的混合物。導通孔與電氣絕緣餍(僅電氣絕緣層) 、構造體的電氣絕緣層之熱膨脹係數如表1所7^ ° _____ 28 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 550997 A7 五、發明說明(; 試料編號 配線基板
A
B 導通孔 僅電氣絕緣 層 20 構造體的電 氣絕緣層 43 17 電氣絕緣層 /導通孔 1.43 0.57 A 47 98 3.27 4 5 6 7 8 9 10 B A B A B A 30 100 150 200 45 190 101 301 155 488 200 •50 6.33 3.37 10.0 5.17 16.3 6.67 與電氣絕緣層爲相同材料所形成之配線基板⑺基板)時, 於作成構造體時的熱膨脹係數爲不相同。由於電氣絕緣層 及B基板並未摻入補強材料,故在χγζ方向顯示相同的 熱膨脹係數,而玻璃環氧樹脂基板由於摻入有玻璃布,故 於ΧΥ方向與Ζ方向的熱膨脹係數有相當的差異。前述A 基板之熱膨脹係數於χγ方向爲10ppm,於Z方向爲 150ppm的材料。作成構造體之場合,由於電氣絕緣層係黏 合固定於配線基板,故會受到楊氏模量高的配線基板(A基 板)所強制固定住。因此,無法朝χγ方向延展,致Z方向 的熱膨脹係數增加。以同樣材料之B基板用於配線基板之 場合’當然,熱膨脹係數不會有變化。對所製作之試料施 加熱循環試驗(-50〜270°C)時的導通孔的電阻値(斷開數)作 調查(表2)。 29 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) --—II--— — — — — — — · I I (請先閱讀背面之注意事項再填寫本頁} --線· 550997 A7B7 五、發明說明(^) 表2 試料編號 1 2 3 4 5 6 7 8 9 10 電氣絕緣層 /導通孔 1.43 0.57 3.27 1.50 6.33 3.37 10.0 5.17 16.3 6.67 斷開數 (/1000) 0 0 0 1 0 0 0 2 195 1 實驗的結果,試料編號9的試料發生了多數的斷開。 其原因,據推測係導通孔的熱膨脹係數與電氣絕緣層的熱 膨脹係數之差所導致者。即使電氣絕緣層爲相同材料,於 作成構造體時的熱膨脹係數的差,也會對導通孔的可靠性 有影響,藉由將熱膨脹係數之比設爲10倍以內,可提供可 靠性高的元件內藏模組。 〔元件符號說明〕 ----------------- (請先閱讀背面之注意事項再填寫本頁) · 101 、 201 、 301 電氣絕緣層 102 、 202 ' 302 配線圖案 103 、 203 、 303 導通孔 104 、 204 、 304 、 612 電子元件 105 、 205 、 305 焊料 106 、 108 配線圖案 107 內導通孔 109 、 211 兩面基板 206 載體 207 貫通孔 306 、 611 、 613 半導體 307 突塊 30 i線- 木紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 550997 A7 B7 五、發明說明(4 ) 308 、 408 、 508 、 608 708 、 808 、 908 509 609 710 1009 1010 1110 配線基板 非導電性膜(NCF) 密封樹脂 空隙 異向性導電膜(ACF) 遮蔽電極 電磁遮蔽層 (請先閱讀背面之注意事項再填寫本頁) 31 衣紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)

Claims (1)

  1. 550997 A8B8C8D8 六、申請專利範圍 (請先閱讀背面之注意事項再塡寫本頁) I一種元件內藏模組,係含有··電氣絕緣層、在前述 電氣絕緣層的兩表面上一體化形成之配線、及用以連接前 述配線間之導通孔,於前述電氣絕緣層的內部,埋設有選 自電子元件及半導體之至少一種元件所成者,其特徵在於 前述配線之至少一方,係形成於配線基板的表面之配 線, 埋設於前述電氣絕緣層的內部之元件,係於埋設之前 搭載於前述配線基板上且構成一體化。 2.如申請專利範圍第1項之元件內藏模組,其係更進 一步在前述配線基板的外側主平面上構裝選自電子元件及 半導體之至少一種元件。 % 3·如申請專利範圍第1項之元件內藏模組,其中,前 述配線基板係選自兩面配線基板及多層配線基板之至少一 種的基板。 4. 如申請專利範圍第1項之元件內藏模組,其係於將 前述元件埋設至前述電氣絕緣層內部之前,已完成選自構 裝檢查及特性檢查之至少一種檢查。 5. 如申請專利範圍第1項之元件內藏模組,其係將前 述兀件沿前述電氣絕緣層的截面方向錯開而配置者。 6·如申請專利範圍第1項之元件內藏模組,其係在配 置於前述電氣絕緣層內部、且構裝於前述電氣絕緣層的兩 主平面之配線基板上的元件之至少一種之間插入遮蔽層。 7·如申請專利範圍第6項之元件內藏模組,其中,前 ____1 —___ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公缝) 550997 as C8 D8 六、申請專利範圍 述遮蔽層,爲金屬箔配線圖案,或爲電磁遮蔽材。 (請先閱讀背面之注意事項再塡寫本頁) 8. 如申請專利範圍第1項之元件內藏模組,其中,前 述電子元件爲分立元件。 9. 如申請專利範圍第1項之元件內藏模組,其中,前 述半導體爲半導體裸晶片。 10. 如申請專利範圍第9項之元件內藏模組,其中,前 述半導體裸晶片係以倒裝片接合方式連接至前述配線上。 11. 如申請專利範圍第9項之元件內藏模組,其中,前 述半導體裸晶片係經硏削或硏磨加工。 12. 如申請專利範圍第1項之元件內藏模組,其中,前 述元件係於前述電氣絕緣層內部呈對向配置。 13. 如申請專利範圍第1項之元件內藏模組,其中,前 述電氣絕緣層的厚度方向之熱膨脹係數,爲導通孔的熱膨 脹係數之10倍以下。 14. 如申請專利範圍第1項之元件內藏模組,其中,前 述電氣絕緣層,係含有樹脂與塡料,塡料含有量爲50質量 %〜95質量%。 15. —種元件內藏模組之製造方法,該元件內藏模組係 含有:電氣絕緣層、在前述電氣絕緣層的兩表面上一體化 形成之配線、及用以連接前述配線間之導通孔,於前述電 氣絕緣層的內部,埋設有選自電子元件及半導體之至少一 種元件所成者; 前述配線之至少一方,係形成於配線基板的表面之配 線; 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 550997 A8 B8 C8 D8 六、申請專利範圍 硏磨。 23. 如申請專利範圍第15項之元件內藏模組之製造方 法,其係於前述半導體構裝後,對前述半導體施以硏削或 硏磨。 24. 如申請專利範圍第15項之元件內藏模組之製造方 法,其係於將選自前述半導體及電子元件之至少一種埋設 至前述電氣絕緣層時,且在埋設的同時進行前述電氣絕緣 層的硬化。 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
TW091123553A 2001-10-18 2002-10-14 Module with built-in components and the manufacturing method thereof TW550997B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001320704 2001-10-18

Publications (1)

Publication Number Publication Date
TW550997B true TW550997B (en) 2003-09-01

Family

ID=19138050

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091123553A TW550997B (en) 2001-10-18 2002-10-14 Module with built-in components and the manufacturing method thereof

Country Status (7)

Country Link
US (2) US6975516B2 (zh)
EP (2) EP1304742B1 (zh)
JP (1) JP4272693B2 (zh)
KR (1) KR20030032892A (zh)
CN (1) CN1293790C (zh)
DE (1) DE60232572D1 (zh)
TW (1) TW550997B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8592689B2 (en) 2010-09-30 2013-11-26 Dai Nippon Printing Co., Ltd. Voltage conversion module

Families Citing this family (198)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100636259B1 (ko) * 2001-12-07 2006-10-19 후지쯔 가부시끼가이샤 반도체 장치 및 그 제조 방법
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW517361B (en) * 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
FI119215B (fi) * 2002-01-31 2008-08-29 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja elektroniikkamoduuli
US8455994B2 (en) * 2002-01-31 2013-06-04 Imbera Electronics Oy Electronic module with feed through conductor between wiring patterns
US20040012935A1 (en) * 2002-07-16 2004-01-22 Matsushita Electric Industrial Co., Ltd. Printed wiring board
US6844505B1 (en) * 2002-11-04 2005-01-18 Ncr Corporation Reducing noise effects in circuit boards
US20040156177A1 (en) * 2003-02-12 2004-08-12 Matsushita Electric Industrial Co., Ltd. Package of electronic components and method for producing the same
FI119583B (fi) * 2003-02-26 2008-12-31 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
DE10320646A1 (de) * 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
US7248482B2 (en) 2003-05-16 2007-07-24 Matsushita Electric Industrial Co., Ltd. Module with built-in circuit component and method for producing the same
US7294533B2 (en) * 2003-06-30 2007-11-13 Intel Corporation Mold compound cap in a flip chip multi-matrix array package and process of making same
TW200507131A (en) * 2003-07-02 2005-02-16 North Corp Multi-layer circuit board for electronic device
US7141884B2 (en) * 2003-07-03 2006-11-28 Matsushita Electric Industrial Co., Ltd. Module with a built-in semiconductor and method for producing the same
FI20031341A (fi) 2003-09-18 2005-03-19 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
EP1523228A3 (en) * 2003-10-09 2008-03-05 Matsushita Electric Industrial Co., Ltd. Mobile terminal, circuit board, circuit board design aiding apparatus and method, design aiding program, and storage medium having stored therein design aiding program
JP2005203674A (ja) * 2004-01-19 2005-07-28 Nitto Denko Corp 電子部品内蔵基板の製造方法
JP4841806B2 (ja) * 2004-02-02 2011-12-21 新光電気工業株式会社 キャパシタ装置とそれを備えた半導体装置、及びキャパシタ装置の製造方法
DE102004009825A1 (de) * 2004-02-28 2005-09-22 Eads Deutschland Gmbh Leiterplatte
WO2005099331A1 (ja) * 2004-03-30 2005-10-20 Matsushita Electric Industrial Co., Ltd. モジュール部品およびその製造方法
JP4339739B2 (ja) * 2004-04-26 2009-10-07 太陽誘電株式会社 部品内蔵型多層基板
FI20041680A (fi) * 2004-04-27 2005-10-28 Imbera Electronics Oy Elektroniikkamoduuli ja menetelmä sen valmistamiseksi
US7441329B2 (en) * 2004-06-07 2008-10-28 Subtron Technology Co. Ltd. Fabrication process circuit board with embedded passive component
TWI236124B (en) * 2004-06-30 2005-07-11 Airoha Tech Corp Multilayer leadframe module with embedded passive components and method of producing the same
WO2006011320A1 (ja) * 2004-07-30 2006-02-02 Murata Manufacturing Co., Ltd. 複合型電子部品及びその製造方法
TWI315648B (en) * 2004-11-17 2009-10-01 Phoenix Prec Technology Corp Circuit board structure with embeded adjustable passive components and method for fabricating the same
JP2006165252A (ja) * 2004-12-07 2006-06-22 Shinko Electric Ind Co Ltd チップ内蔵基板の製造方法
TWI245384B (en) * 2004-12-10 2005-12-11 Phoenix Prec Technology Corp Package structure with embedded chip and method for fabricating the same
JP4602208B2 (ja) * 2004-12-15 2010-12-22 新光電気工業株式会社 電子部品実装構造体及びその製造方法
US7515434B2 (en) * 2004-12-20 2009-04-07 Nortel Networks Limited Technique for enhancing circuit density and performance
JP3914239B2 (ja) 2005-03-15 2007-05-16 新光電気工業株式会社 配線基板および配線基板の製造方法
KR100716826B1 (ko) * 2005-05-10 2007-05-09 삼성전기주식회사 전자부품이 내장된 기판의 제조방법
KR100722647B1 (ko) * 2005-06-25 2007-05-28 삼성전기주식회사 몰딩된 전자부품 패키지를 내장한 기판의 제조방법
KR100714196B1 (ko) * 2005-07-11 2007-05-02 삼성전기주식회사 전기소자를 내장한 인쇄회로기판 및 그 제조방법
JP4508193B2 (ja) * 2005-07-13 2010-07-21 パナソニック株式会社 実装基板、実装体とそれを用いた電子機器
US8959762B2 (en) 2005-08-08 2015-02-24 Rf Micro Devices, Inc. Method of manufacturing an electronic module
US20070041680A1 (en) * 2005-08-18 2007-02-22 Stmicroelectronics S.A. Process for assembling passive and active components and corresponding integrated circuit
JP4701942B2 (ja) * 2005-09-14 2011-06-15 Tdk株式会社 半導体ic内蔵モジュール
JP2007103466A (ja) * 2005-09-30 2007-04-19 Toshiba Corp 多層プリント配線板、多層プリント配線板の製造方法、電子機器
KR100722553B1 (ko) * 2005-11-18 2007-05-28 엘지전자 주식회사 인쇄회로기판 및 그 제조방법
KR100656751B1 (ko) * 2005-12-13 2006-12-13 삼성전기주식회사 전자소자 내장 인쇄회로기판 및 그 제조방법
CN101331605A (zh) * 2005-12-15 2008-12-24 松下电器产业株式会社 电子部件内置模块和其制造方法
JP5114041B2 (ja) * 2006-01-13 2013-01-09 日本シイエムケイ株式会社 半導体素子内蔵プリント配線板及びその製造方法
JP2007234697A (ja) * 2006-02-28 2007-09-13 Toshiba Corp 部品内蔵プリント配線板、部品内蔵プリント配線板の製造方法および電子機器
DE102006009723A1 (de) 2006-03-02 2007-09-06 Siemens Ag Verfahren zum Herstellen und planaren Kontaktieren einer elektronischen Vorrichtung und entsprechend hergestellte Vorrichtung
US8026129B2 (en) * 2006-03-10 2011-09-27 Stats Chippac Ltd. Stacked integrated circuits package system with passive components
CN101480116B (zh) * 2006-04-27 2013-02-13 日本电气株式会社 电路基板、电子器件配置及用于电路基板的制造工艺
KR20130023362A (ko) * 2006-05-24 2013-03-07 다이니폰 인사츠 가부시키가이샤 부품 내장 배선판, 부품 내장 배선판의 제조 방법
JP2007324354A (ja) * 2006-05-31 2007-12-13 Sony Corp 半導体装置
JP2007324550A (ja) * 2006-06-05 2007-12-13 Denso Corp 多層基板
JP5168838B2 (ja) * 2006-07-28 2013-03-27 大日本印刷株式会社 多層プリント配線板及びその製造方法
TWI302732B (en) * 2006-08-03 2008-11-01 Unimicron Technology Corp Embedded chip package process and circuit board with embedded chip
CN101512761A (zh) * 2006-09-01 2009-08-19 株式会社村田制作所 电子部件装置及其制造方法与电子部件组件及其制造方法
JP4274290B2 (ja) * 2006-11-28 2009-06-03 国立大学法人九州工業大学 両面電極構造の半導体装置の製造方法
JP5326269B2 (ja) * 2006-12-18 2013-10-30 大日本印刷株式会社 電子部品内蔵配線板、及び電子部品内蔵配線板の放熱方法
US7504283B2 (en) * 2006-12-18 2009-03-17 Texas Instruments Incorporated Stacked-flip-assembled semiconductor chips embedded in thin hybrid substrate
US8178982B2 (en) * 2006-12-30 2012-05-15 Stats Chippac Ltd. Dual molded multi-chip package system
JP4073945B1 (ja) * 2007-01-12 2008-04-09 新光電気工業株式会社 多層配線基板の製造方法
US9466545B1 (en) 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
US20100328913A1 (en) * 2007-03-30 2010-12-30 Andreas Kugler Method for the producing an electronic subassembly, as well as electronic subassembly
JP2008294381A (ja) * 2007-05-28 2008-12-04 Panasonic Corp 電子部品モジュール及び電子部品モジュールの製造方法
TWI376774B (en) * 2007-06-08 2012-11-11 Cyntec Co Ltd Three dimensional package structure
US9601412B2 (en) * 2007-06-08 2017-03-21 Cyntec Co., Ltd. Three-dimensional package structure
JP5012896B2 (ja) * 2007-06-26 2012-08-29 株式会社村田製作所 部品内蔵基板の製造方法
TWI455672B (zh) * 2007-07-06 2014-10-01 Murata Manufacturing Co A method for forming a hole for connecting a conductor for a layer, a method for manufacturing a resin substrate and a component-mounted substrate, and a method of manufacturing a resin substrate and a component
JP4752825B2 (ja) * 2007-08-24 2011-08-17 カシオ計算機株式会社 半導体装置の製造方法
KR100869832B1 (ko) * 2007-09-18 2008-11-21 삼성전기주식회사 반도체칩 패키지 및 이를 이용한 인쇄회로기판
US7834464B2 (en) * 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
CN101843181B (zh) * 2007-11-01 2014-05-28 大日本印刷株式会社 内置元件电路板
JP2009117450A (ja) * 2007-11-02 2009-05-28 Rohm Co Ltd モジュールおよびその製造方法
JP5230997B2 (ja) * 2007-11-26 2013-07-10 新光電気工業株式会社 半導体装置
US20090154127A1 (en) * 2007-12-18 2009-06-18 Ting-Hao Lin PCB Embedded Electronic Elements Structure And Method Thereof
US8350367B2 (en) 2008-02-05 2013-01-08 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8212339B2 (en) 2008-02-05 2012-07-03 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US7989928B2 (en) * 2008-02-05 2011-08-02 Advanced Semiconductor Engineering Inc. Semiconductor device packages with electromagnetic interference shielding
US8022511B2 (en) 2008-02-05 2011-09-20 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US20100327044A1 (en) * 2008-02-25 2010-12-30 Panasonic Corporation Method for manufacturing electronic component module
JP2009246104A (ja) * 2008-03-31 2009-10-22 Kyushu Institute Of Technology 配線用電子部品及びその製造方法
JP5005599B2 (ja) * 2008-03-31 2012-08-22 Tdk株式会社 電子部品及び電子部品モジュール
US8093704B2 (en) * 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
US8125766B2 (en) 2008-06-13 2012-02-28 Kemet Electronics Corporation Concentrated capacitor assembly
US7888184B2 (en) * 2008-06-20 2011-02-15 Stats Chippac Ltd. Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof
TWI453877B (zh) * 2008-11-07 2014-09-21 Advanced Semiconductor Eng 內埋晶片封裝的結構及製程
DE102008040488A1 (de) * 2008-07-17 2010-01-21 Robert Bosch Gmbh Elektronische Baueinheit und Verfahren zu deren Herstellung
US8410584B2 (en) 2008-08-08 2013-04-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
WO2010018708A1 (ja) * 2008-08-12 2010-02-18 株式会社村田製作所 部品内蔵モジュールの製造方法及び部品内蔵モジュール
US20100110656A1 (en) 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US7993941B2 (en) * 2008-12-05 2011-08-09 Stats Chippac, Ltd. Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant
JP2010141098A (ja) * 2008-12-11 2010-06-24 Shinko Electric Ind Co Ltd 電子部品内蔵基板及びその製造方法
JP4972633B2 (ja) * 2008-12-11 2012-07-11 日東電工株式会社 半導体装置の製造方法
FI20095110A0 (fi) 2009-02-06 2009-02-06 Imbera Electronics Oy Elektroniikkamoduuli, jossa on EMI-suoja
US8110902B2 (en) * 2009-02-19 2012-02-07 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
JP4760930B2 (ja) * 2009-02-27 2011-08-31 株式会社デンソー Ic搭載基板、多層プリント配線板、及び製造方法
US8003445B2 (en) * 2009-03-26 2011-08-23 Stats Chippac Ltd. Integrated circuit packaging system with z-interconnects having traces and method of manufacture thereof
JP5285144B2 (ja) 2009-03-26 2013-09-11 シャープ株式会社 チップ部品実装構造、チップ部品実装方法および液晶表示装置
JP5300558B2 (ja) * 2009-03-27 2013-09-25 日東電工株式会社 半導体装置の製造方法
US8110920B2 (en) * 2009-06-05 2012-02-07 Intel Corporation In-package microelectronic apparatus, and methods of using same
US9355962B2 (en) * 2009-06-12 2016-05-31 Stats Chippac Ltd. Integrated circuit package stacking system with redistribution and method of manufacture thereof
US8212340B2 (en) 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
TWI405306B (zh) * 2009-07-23 2013-08-11 Advanced Semiconductor Eng 半導體封裝件、其製造方法及重佈晶片封膠體
JP2011060875A (ja) * 2009-09-08 2011-03-24 Panasonic Corp 電子部品内蔵基板及びその製造方法とこれを用いた半導体装置
US20110084406A1 (en) * 2009-10-13 2011-04-14 Sony Corporation Device and interconnect in flip chip architecture
US20110084372A1 (en) * 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
KR20110041179A (ko) * 2009-10-15 2011-04-21 한국전자통신연구원 패키지 구조
US8368185B2 (en) 2009-11-19 2013-02-05 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8030750B2 (en) 2009-11-19 2011-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
CN102088824B (zh) * 2009-12-03 2012-12-26 鸿骐新技股份有限公司 印刷电路板上的微小化无源元件的修复方法及其系统
JP5665020B2 (ja) * 2009-12-22 2015-02-04 国立大学法人九州工業大学 配線用電子部品の製造方法
TWI408785B (zh) * 2009-12-31 2013-09-11 Advanced Semiconductor Eng 半導體封裝結構
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8372689B2 (en) * 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
JP5521584B2 (ja) 2010-01-28 2014-06-18 Tdk株式会社 Pbフリーはんだ及び電子部品内蔵モジュール
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
TWI419283B (zh) 2010-02-10 2013-12-11 Advanced Semiconductor Eng 封裝結構
JP5115573B2 (ja) * 2010-03-03 2013-01-09 オムロン株式会社 接続用パッドの製造方法
KR101043328B1 (ko) * 2010-03-05 2011-06-22 삼성전기주식회사 전자소자 내장형 인쇄회로기판 및 그 제조방법
KR101104210B1 (ko) * 2010-03-05 2012-01-10 삼성전기주식회사 전자소자 내장형 인쇄회로기판 및 그 제조방법
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8624374B2 (en) * 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8677613B2 (en) * 2010-05-20 2014-03-25 International Business Machines Corporation Enhanced modularity in heterogeneous 3D stacks
KR20120004777A (ko) * 2010-07-07 2012-01-13 삼성전기주식회사 전자 부품 모듈 및 이의 제조방법
TWI540698B (zh) 2010-08-02 2016-07-01 日月光半導體製造股份有限公司 半導體封裝件與其製造方法
CN102378464A (zh) * 2010-08-12 2012-03-14 环鸿科技股份有限公司 电路板模块
WO2012023332A1 (ja) * 2010-08-18 2012-02-23 株式会社 村田製作所 電子部品及びその製造方法
US8518746B2 (en) * 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
TWI451546B (zh) 2010-10-29 2014-09-01 Advanced Semiconductor Eng 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8835226B2 (en) 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US8487426B2 (en) 2011-03-15 2013-07-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with embedded die and manufacturing methods thereof
US9142502B2 (en) * 2011-08-31 2015-09-22 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits
US8916421B2 (en) * 2011-08-31 2014-12-23 Freescale Semiconductor, Inc. Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits
JP5100878B1 (ja) * 2011-09-30 2012-12-19 株式会社フジクラ 部品内蔵基板実装体及びその製造方法並びに部品内蔵基板
US8597983B2 (en) 2011-11-18 2013-12-03 Freescale Semiconductor, Inc. Semiconductor device packaging having substrate with pre-encapsulation through via formation
CN104094679B (zh) 2012-02-17 2017-08-29 株式会社村田制作所 元器件内置基板
JP5743922B2 (ja) * 2012-02-21 2015-07-01 日立オートモティブシステムズ株式会社 熱式空気流量測定装置
US8901730B2 (en) 2012-05-03 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices
US8704341B2 (en) 2012-05-15 2014-04-22 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal dissipation structures and EMI shielding
US8653634B2 (en) 2012-06-11 2014-02-18 Advanced Semiconductor Engineering, Inc. EMI-shielded semiconductor devices and methods of making
JP5737478B2 (ja) * 2012-07-05 2015-06-17 株式会社村田製作所 部品内蔵基板
US9406552B2 (en) 2012-12-20 2016-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive via and manufacturing process
US10840005B2 (en) 2013-01-25 2020-11-17 Vishay Dale Electronics, Llc Low profile high current composite transformer
CN203206586U (zh) * 2013-02-27 2013-09-18 奥特斯(中国)有限公司 用于生产印制电路板的半成品
KR101514518B1 (ko) * 2013-05-24 2015-04-22 삼성전기주식회사 전자부품 내장 인쇄회로기판 및 그 제조방법
US9807890B2 (en) * 2013-05-31 2017-10-31 Qorvo Us, Inc. Electronic modules having grounded electromagnetic shields
KR102157551B1 (ko) * 2013-11-08 2020-09-18 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US10219384B2 (en) 2013-11-27 2019-02-26 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Circuit board structure
AT515101B1 (de) 2013-12-12 2015-06-15 Austria Tech & System Tech Verfahren zum Einbetten einer Komponente in eine Leiterplatte
US9196586B2 (en) * 2014-02-13 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including an embedded surface mount device and method of forming the same
US11523520B2 (en) 2014-02-27 2022-12-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board
AT515447B1 (de) 2014-02-27 2019-10-15 At & S Austria Tech & Systemtechnik Ag Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte
TWI517775B (zh) * 2014-03-06 2016-01-11 相互股份有限公司 印刷電路板及其製法
US10681821B2 (en) * 2014-10-16 2020-06-09 The Charles Stark Draper Laboratory, Inc. Methods and devices for improved space utilization in wafer based modules
US10433424B2 (en) * 2014-10-16 2019-10-01 Cyntec Co., Ltd Electronic module and the fabrication method thereof
CN107006138B (zh) * 2014-12-12 2019-07-05 名幸电子有限公司 模制电路模块及其制造方法
US9583472B2 (en) * 2015-03-03 2017-02-28 Apple Inc. Fan out system in package and method for forming the same
CN104735914B (zh) * 2015-04-15 2018-04-27 四川英创力电子科技股份有限公司 用AlN陶瓷基片作为基板制备线路板的方法
US10054473B2 (en) 2015-12-03 2018-08-21 International Business Machines Corporation Airflow sensor for a heat sink
JP6406235B2 (ja) * 2015-12-16 2018-10-17 オムロン株式会社 電子装置及びその製造方法
DE112015007232T5 (de) * 2015-12-23 2019-02-28 Intel IP Corporation Auf eplb/ewlb basierendes pop für hbm oder kundenspezifischer gehäusestapel
US9874415B2 (en) * 2016-02-15 2018-01-23 International Business Machines Corporation Airflow sensor for a heat sink
EP3792960A3 (en) 2016-04-11 2021-06-02 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Batch manufacture of component carriers
US10998124B2 (en) 2016-05-06 2021-05-04 Vishay Dale Electronics, Llc Nested flat wound coils forming windings for transformers and inductors
EP3507816A4 (en) 2016-08-31 2020-02-26 Vishay Dale Electronics, LLC INDUCTANCE COIL COMPRISING A HIGH CURRENT COIL HAVING LOW DIRECT CURRENT RESISTANCE
MY192051A (en) * 2016-12-29 2022-07-25 Intel Corp Stacked dice systems
DE102017209249A1 (de) * 2017-05-31 2018-12-06 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur herstellung eines packages und package
CN110800101B (zh) * 2017-06-30 2023-09-15 株式会社村田制作所 电子部件模块
US10468384B2 (en) 2017-09-15 2019-11-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same
US10446533B2 (en) * 2017-09-29 2019-10-15 Intel Corporation Package on package with integrated passive electronics method and apparatus
KR101982061B1 (ko) * 2017-12-19 2019-05-24 삼성전기주식회사 반도체 패키지
US11088066B2 (en) * 2018-03-19 2021-08-10 Tactotek Oy Multilayer structure and related method of manufacture for electronics
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
EP3609066B1 (en) * 2018-08-07 2021-02-24 Mahle International GmbH Electric power inverter
TWI671572B (zh) * 2018-10-22 2019-09-11 友達光電股份有限公司 顯示面板及其製造方法
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
JP7192523B2 (ja) * 2019-01-23 2022-12-20 富士通株式会社 半導体パッケージ及び電子装置
KR20200099686A (ko) 2019-02-15 2020-08-25 엘지이노텍 주식회사 회로기판
US11515282B2 (en) 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules
CN112020199B (zh) * 2019-05-29 2022-03-08 鹏鼎控股(深圳)股份有限公司 内埋式电路板及其制作方法
CN112020222A (zh) * 2019-05-30 2020-12-01 鹏鼎控股(深圳)股份有限公司 内埋电路板及其制作方法
CN112533349B (zh) * 2019-09-18 2022-07-19 宏启胜精密电子(秦皇岛)有限公司 电路板及其制作方法
DE102019219238A1 (de) 2019-12-10 2021-06-10 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Mehrlagiges 3D-Folienpackage
KR20210076585A (ko) * 2019-12-16 2021-06-24 삼성전기주식회사 전자부품 내장기판
JP7528763B2 (ja) * 2020-12-11 2024-08-06 株式会社村田製作所 積層セラミック電子部品および樹脂電極用導電性ペースト
USD1034462S1 (en) 2021-03-01 2024-07-09 Vishay Dale Electronics, Llc Inductor package
CN115148712A (zh) * 2021-03-29 2022-10-04 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
US11581233B2 (en) * 2021-05-04 2023-02-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical circuit pattern within encapsulant of SIP module
US11948724B2 (en) 2021-06-18 2024-04-02 Vishay Dale Electronics, Llc Method for making a multi-thickness electro-magnetic device
KR20230047812A (ko) * 2021-10-01 2023-04-10 삼성전기주식회사 전자부품 내장기판
DE102022113639A1 (de) 2022-05-31 2023-11-30 Rolls-Royce Deutschland Ltd & Co Kg Elektrisches Modul
FR3138594A1 (fr) * 2022-07-26 2024-02-02 Safran Electronics & Defense Procédé d’assemblage d’un composant électronique dans un circuit imprimé, procédé de fabrication d’un circuit imprimé multicouche et circuit imprimé obtenu par ce procédé

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02222598A (ja) * 1989-02-23 1990-09-05 Fujitsu Ltd 半導体装置モジュール
JPH05259372A (ja) 1992-01-14 1993-10-08 Sony Corp ハイブリッドic
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JPH06350211A (ja) 1993-06-08 1994-12-22 Hitachi Chem Co Ltd 印刷配線板用エポキシ樹脂組成物
JP3687506B2 (ja) * 1993-06-25 2005-08-24 富士電機機器制御株式会社 多層金属プリント基板
US5353195A (en) 1993-07-09 1994-10-04 General Electric Company Integral power and ground structure for multi-chip modules
JPH0758488A (ja) * 1993-08-20 1995-03-03 Cmk Corp 磁性塗膜及び電磁波シールド層を有するプリント配線板 とその製造方法
DE69419219T2 (de) * 1993-09-03 2000-01-05 Kabushiki Kaisha Toshiba, Kawasaki Leiterplatte und Verfahren zur Herstellung solcher Leiterplatten
JP3527766B2 (ja) 1993-11-30 2004-05-17 京セラ株式会社 積層回路基板の製造方法及び積層回路基板
JP3288840B2 (ja) * 1994-02-28 2002-06-04 三菱電機株式会社 半導体装置およびその製造方法
JP2917812B2 (ja) 1994-05-10 1999-07-12 住友金属工業株式会社 多層セラミックパッケージ及び該多層セラミックパッケージにおける外部露出導電体部分のメッキ処理方法
US5491612A (en) * 1995-02-21 1996-02-13 Fairchild Space And Defense Corporation Three-dimensional modular assembly of integrated circuits
US5564181A (en) * 1995-04-18 1996-10-15 Draper Laboratory, Inc. Method of fabricating a laminated substrate assembly chips-first multichip module
US5552633A (en) * 1995-06-06 1996-09-03 Martin Marietta Corporation Three-dimensional multimodule HDI arrays with heat spreading
JP3229525B2 (ja) 1995-07-26 2001-11-19 株式会社日立製作所 Lsi内蔵型多層回路板およびその製法
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
CN1094717C (zh) 1995-11-16 2002-11-20 松下电器产业株式会社 印刷电路板的安装体
US5567657A (en) * 1995-12-04 1996-10-22 General Electric Company Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US5880530A (en) * 1996-03-29 1999-03-09 Intel Corporation Multiregion solder interconnection structure
US5874770A (en) 1996-10-10 1999-02-23 General Electric Company Flexible interconnect film including resistor and capacitor layers
JP3754171B2 (ja) 1997-04-08 2006-03-08 富士通株式会社 回路基板及びその製造方法
JP3687041B2 (ja) * 1997-04-16 2005-08-24 大日本印刷株式会社 配線基板、配線基板の製造方法、および半導体パッケージ
JPH11103147A (ja) 1997-09-26 1999-04-13 Toshiba Corp 回路モジュール及び回路モジュールを内蔵した電子機器
JPH11126978A (ja) 1997-10-24 1999-05-11 Kyocera Corp 多層配線基板
JP3375555B2 (ja) 1997-11-25 2003-02-10 松下電器産業株式会社 回路部品内蔵モジュールおよびその製造方法
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
JP2870533B1 (ja) 1997-11-27 1999-03-17 日本電気株式会社 半導体装置およびその製造方法
WO1999036957A1 (fr) * 1998-01-19 1999-07-22 Citizen Watch Co., Ltd. Boitier de semiconducteur
JP2000004071A (ja) 1998-06-16 2000-01-07 Alps Electric Co Ltd 電子回路ユニット
SE513341C2 (sv) * 1998-10-06 2000-08-28 Ericsson Telefon Ab L M Arrangemang med tryckta kretskort samt metod för tillverkning därav
US6239485B1 (en) 1998-11-13 2001-05-29 Fujitsu Limited Reduced cross-talk noise high density signal interposer with power and ground wrap
US6429386B2 (en) * 1998-12-30 2002-08-06 Ncr Corporation Imbedded die-scale interconnect for ultra-high speed digital communications
JP2000208662A (ja) 1999-01-11 2000-07-28 Sumitomo Bakelite Co Ltd 半導体搭載用基板とその製造方法及び半導体チップの実装方法
JP3640560B2 (ja) * 1999-02-22 2005-04-20 日本特殊陶業株式会社 配線基板、コンデンサ内蔵コア基板、及びこれらの製造方法
JP3213292B2 (ja) 1999-07-12 2001-10-02 ソニーケミカル株式会社 多層基板、及びモジュール
JP3619395B2 (ja) 1999-07-30 2005-02-09 京セラ株式会社 半導体素子内蔵配線基板およびその製造方法
JP2001060602A (ja) 1999-08-23 2001-03-06 Fuji Electric Co Ltd フリップチップ実装構造及びその製造方法
KR100335121B1 (ko) * 1999-08-25 2002-05-04 박종섭 반도체 메모리 소자 및 그의 제조 방법
JP2001102749A (ja) 1999-09-17 2001-04-13 Internatl Business Mach Corp <Ibm> 回路基板
JP2001111232A (ja) * 1999-10-06 2001-04-20 Sony Corp 電子部品実装多層基板及びその製造方法
US6428942B1 (en) 1999-10-28 2002-08-06 Fujitsu Limited Multilayer circuit structure build up method
JP3503133B2 (ja) 1999-12-10 2004-03-02 日本電気株式会社 電子デバイス集合体と電子デバイスの接続方法
JP3670917B2 (ja) * 1999-12-16 2005-07-13 新光電気工業株式会社 半導体装置及びその製造方法
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
JP3598060B2 (ja) 1999-12-20 2004-12-08 松下電器産業株式会社 回路部品内蔵モジュール及びその製造方法並びに無線装置
JP2001210776A (ja) 2000-01-24 2001-08-03 Fujitsu Ltd 半導体装置とその製造方法及びリードフレームとその製造方法
JP3772066B2 (ja) 2000-03-09 2006-05-10 沖電気工業株式会社 半導体装置
TW569424B (en) * 2000-03-17 2004-01-01 Matsushita Electric Ind Co Ltd Module with embedded electric elements and the manufacturing method thereof
US6949822B2 (en) 2000-03-17 2005-09-27 International Rectifier Corporation Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance
US6570469B2 (en) 2000-06-27 2003-05-27 Matsushita Electric Industrial Co., Ltd. Multilayer ceramic device including two ceramic layers with multilayer circuit patterns that can support semiconductor and saw chips
TW511415B (en) 2001-01-19 2002-11-21 Matsushita Electric Ind Co Ltd Component built-in module and its manufacturing method
JP2002319658A (ja) 2001-04-20 2002-10-31 Matsushita Electric Ind Co Ltd 半導体装置
US20020175402A1 (en) * 2001-05-23 2002-11-28 Mccormack Mark Thomas Structure and method of embedding components in multi-layer substrates
EP2315510A3 (en) * 2001-06-05 2012-05-02 Dai Nippon Printing Co., Ltd. Wiring board provided with passive element
JP3840921B2 (ja) * 2001-06-13 2006-11-01 株式会社デンソー プリント基板のおよびその製造方法
US6537852B2 (en) 2001-08-22 2003-03-25 International Business Machines Corporation Spacer - connector stud for stacked surface laminated multichip modules and methods of manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8592689B2 (en) 2010-09-30 2013-11-26 Dai Nippon Printing Co., Ltd. Voltage conversion module

Also Published As

Publication number Publication date
KR20030032892A (ko) 2003-04-26
CN1293790C (zh) 2007-01-03
JP4272693B2 (ja) 2009-06-03
US20030090883A1 (en) 2003-05-15
CN1418048A (zh) 2003-05-14
EP2056349A1 (en) 2009-05-06
DE60232572D1 (de) 2009-07-23
EP1304742A2 (en) 2003-04-23
EP1304742A3 (en) 2006-03-29
US7294587B2 (en) 2007-11-13
EP1304742B1 (en) 2009-06-10
JP2008294475A (ja) 2008-12-04
US6975516B2 (en) 2005-12-13
US20050269681A1 (en) 2005-12-08

Similar Documents

Publication Publication Date Title
TW550997B (en) Module with built-in components and the manufacturing method thereof
US6955948B2 (en) Method of manufacturing a component built-in module
JP2003197849A (ja) 部品内蔵モジュールとその製造方法
US7849591B2 (en) Method of manufacturing a printed wiring board
JP3553043B2 (ja) 部品内蔵モジュールとその製造方法
JP3375555B2 (ja) 回路部品内蔵モジュールおよびその製造方法
JP4279893B2 (ja) 回路部品内蔵モジュールの製造方法
TW511405B (en) Device built-in module and manufacturing method thereof
JP2002134653A (ja) 半導体装置とその製造方法
JP2003188340A (ja) 部品内蔵モジュールとその製造方法
JP2004311788A (ja) シート状モジュールとその製造方法
JP2010278414A (ja) 配線板用材料、積層板、多層板及び配線基板
JP2006210870A (ja) 部品内蔵モジュール及びその製造方法
JP4606685B2 (ja) 回路部品内蔵モジュール
JP2001308470A (ja) 回路部品モジュール及びその製造方法
JP2011233915A (ja) 複合配線基板およびその製造方法、ならびに電子部品の実装体および製造方法
JP2007194516A (ja) 複合配線基板およびその製造方法、ならびに電子部品の実装体および製造方法
JP2004055967A (ja) 電子部品内蔵基板の製造方法
JP2004363566A (ja) 電子部品実装体及びその製造方法
JP2005005692A (ja) 回路部品内蔵モジュールおよびその製造方法
WO2007037086A1 (ja) 部品内蔵基板及びその製造方法
JP2005051204A (ja) 電気部品実装モジュールおよびその製造方法
JP2007221117A (ja) 部品内蔵基板およびその製造方法
JP2008205071A (ja) 電子部品内蔵基板とこれを用いた電子機器、およびその製造方法
JP2004193392A (ja) 回路部品内蔵モジュールおよびその製造方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees