JP5524567B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5524567B2 JP5524567B2 JP2009243799A JP2009243799A JP5524567B2 JP 5524567 B2 JP5524567 B2 JP 5524567B2 JP 2009243799 A JP2009243799 A JP 2009243799A JP 2009243799 A JP2009243799 A JP 2009243799A JP 5524567 B2 JP5524567 B2 JP 5524567B2
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- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H—ELECTRICITY
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Description
図1(A)に駆動回路に用いる第1の薄膜トランジスタ430と、画素部に用いる第2の薄膜トランジスタ170とを同一基板上に設ける例を示す。なお、図1(A)は表示装置の断面図の一例である。
実施の形態1では駆動回路の薄膜トランジスタとして一つの薄膜トランジスタを説明したが、ここでは、2つのnチャネル型の薄膜トランジスタを用いて駆動回路のインバータ回路を構成する例を基に以下に説明する。図2(A)に示す薄膜トランジスタは、実施の形態1の図1(A)に示した薄膜トランジスタ430と同一であるため、同じ部分には同じ符号を用いて説明する。
本実施の形態では、表示装置について、ブロック図等を参照して説明する。
本実施の形態では、実施の形態1に示した第2の薄膜トランジスタ170を含む表示装置の作製工程について、図9乃至図16を用いて説明する。
本実施の形態では、半導体装置として電子ペーパーの例を示す。
本実施の形態では、半導体装置として発光表示装置の例を示す。表示装置の有する表示素子としては、ここではエレクトロルミネッセンスを利用する発光素子を用いて示す。エレクトロルミネッセンスを利用する発光素子は、発光材料が有機化合物であるか、無機化合物であるかによって区別され、一般的に、前者は有機EL素子、後者は無機EL素子と呼ばれている。
本実施の形態では、半導体装置の一形態に相当する液晶表示パネルの上面及び断面について、図21(A1)、図21(A2)、図21(B)を用いて説明する。図21(A1)、図21(A2)は、第1の基板4001上に形成された実施の形態1で示したIn−Ga−Zn−O系非単結晶膜を半導体層として含む薄膜トランジスタ4010、4011、及び液晶素子4013を、第2の基板4006との間にシール材4005によって封止した、パネルの上面図であり、図21(B)は、図21(A1)、図21(A2)のM−Nにおける断面図に相当する。
開示した発明に係る半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。
ここでは、ソース配線(またはドレイン配線)と半導体層との間に第2の酸化物半導体層(n+層)を有する構成の薄膜トランジスタを有する表示装置の例を図26に示す。なお、図26において、図1(A)と同一の箇所には同じ符号を用いて説明する。
101 ゲート電極
102 ゲート絶縁層
103 酸化物半導体層
104a、104b n+層
105a ソース電極層
105b ドレイン電極層
107 保護絶縁層
108 容量配線
109 酸化物半導体膜
110 画素電極
111 酸化物半導体膜
120 接続電極
121 端子
122 端子
125 コンタクトホール
126 コンタクトホール
127 コンタクトホール
128 透明導電膜
129 透明導電膜
131 レジストマスク
132 導電膜
150 端子
151 端子
152 ゲート絶縁層
153 接続電極
154 保護絶縁膜
155 透明導電膜
156 電極
170 第2の薄膜トランジスタ
400 基板
401 第1のゲート電極
402 ゲート電極
403 第1のゲート絶縁層
404 コンタクトホール
405 酸化物半導体層
407 酸化物半導体層
409 配線
410 配線
411 配線
412 第2のゲート絶縁層
430 薄膜トランジスタ
431 薄膜トランジスタ
432 薄膜トランジスタ
433 薄膜トランジスタ
440 基板
441 ゲート電極
442 ゲート電極
443 ゲート絶縁層
444 コンタクトホール
445 酸化物半導体層
447 酸化物半導体層
449 第1配線
450 第2配線
451 第3配線
452 保護層
453 接続配線
460 薄膜トランジスタ
461 薄膜トランジスタ
470 第2のゲート電極
471 電極
472 第1の電極
473 絶縁層
474 第2の電極
475 発光層
476 電極
581 薄膜トランジスタ
585 絶縁層
587 電極層
588 電極層
589 球形粒子
594 キャビティ
595 充填材
Claims (7)
- 第1のトランジスタと、第2のトランジスタと、を有し、
前記第1のトランジスタは、第1のゲート電極と、前記第1のゲート電極と重なる第1の酸化物半導体層と、第1のソース電極と、第1のドレイン電極と、を有し、
前記第2のトランジスタは、第2のゲート電極と、前記第2のゲート電極の上方の第2の酸化物半導体層と、前記第2の酸化物半導体層の上方の第3のゲート電極と、第2のソース電極と、第2のドレイン電極と、を有し、
前記第3のゲート電極は、前記第2の酸化物半導体層を間に挟んで前記第2のゲート電極と重なり、
前記第3のゲート電極は、前記第2の酸化物半導体層のチャネル長方向の幅よりも広く、且つ前記第2のゲート電極のチャネル長方向の幅よりも広く、
前記第2のソース電極及び前記第2のドレイン電極は、前記第2の酸化物半導体層の下方に有し、
前記第1のトランジスタまたは前記第2のトランジスタの一方は、エンハンスメント型トランジスタとして機能させることができ、
前記第1のトランジスタまたは前記第2のトランジスタの他方は、デプレッション型トランジスタとして機能させることができることを特徴とする半導体装置。 - 画素部と、駆動回路と、を有し、
前記駆動回路は、第1のトランジスタと、第2のトランジスタと、を有し、
前記画素部は、第3のトランジスタを有し、
前記第1のトランジスタは、第1のゲート電極と、前記第1のゲート電極と重なる第1の酸化物半導体層と、第1のソース電極と、第1のドレイン電極と、を有し、
前記第2のトランジスタは、第2のゲート電極と、前記第2のゲート電極の上方の第2の酸化物半導体層と、前記第2の酸化物半導体層の上方の第3のゲート電極と、第2のソース電極と、第2のドレイン電極と、を有し、
前記第3のゲート電極は、前記第2の酸化物半導体層を間に挟んで前記第2のゲート電極と重なり、
前記第3のゲート電極は、前記第2の酸化物半導体層のチャネル長方向の幅よりも広く、且つ前記第2のゲート電極のチャネル長方向の幅よりも広く、
前記第2のソース電極及び前記第2のドレイン電極は、前記第2の酸化物半導体層の下方に有し、
前記第3のトランジスタは、第4のゲート電極と、前記第4のゲート電極と重なる第3の酸化物半導体層と、第3のソース電極と、第3のドレイン電極と、を有し、
前記第1のトランジスタまたは前記第2のトランジスタの一方は、エンハンスメント型トランジスタとして機能させることができ、
前記第1のトランジスタまたは前記第2のトランジスタの他方は、デプレッション型トランジスタとして機能させることができることを特徴とする半導体装置。 - 請求項2において、
前記画素部は、画素電極を有し、
前記画素電極は、前記第3のトランジスタと電気的に接続され、
前記第3のゲート電極と、前記画素電極とは、同じ材料を有することを特徴とする半導体装置。 - 請求項2において、
前記画素部は、画素電極を有し、
前記画素電極は、前記第3のトランジスタと電気的に接続され、
前記第3のゲート電極と、前記画素電極とは、異なる材料を有することを特徴とする半導体装置。 - 請求項1乃至請求項4のいずれか一において、
前記第2のゲート電極と前記第3のゲート電極には、同じ電位が与えられることを特徴とする半導体装置。 - 請求項1乃至請求項4のいずれか一において、
前記第2のゲート電極と前記第3のゲート電極には、異なる電位が与えられることを特徴とする半導体装置。 - 請求項1乃至請求項6のいずれか一において、
前記第1のソース電極または前記第1のドレイン電極は、前記第2のソース電極または前記第2のドレイン電極と電気的に接続され、
前記第1のゲート電極は、前記第1のソース電極または前記第1のドレイン電極と電気的に接続されることを特徴とする半導体装置。
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EP2172977A1 (en) | 2008-10-03 | 2010-04-07 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
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CN103928476A (zh) | 2008-10-03 | 2014-07-16 | 株式会社半导体能源研究所 | 显示装置及其制造方法 |
US8106400B2 (en) | 2008-10-24 | 2012-01-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
KR102251817B1 (ko) | 2008-10-24 | 2021-05-12 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 그 제조 방법 |
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WO2011010541A1 (en) * | 2009-07-18 | 2011-01-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
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JP5796760B2 (ja) * | 2009-07-29 | 2015-10-21 | Nltテクノロジー株式会社 | トランジスタ回路 |
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TWI834207B (zh) | 2008-07-31 | 2024-03-01 | 日商半導體能源研究所股份有限公司 | 半導體裝置及半導體裝置的製造方法 |
JP4623179B2 (ja) | 2008-09-18 | 2011-02-02 | ソニー株式会社 | 薄膜トランジスタおよびその製造方法 |
KR101623958B1 (ko) | 2008-10-01 | 2016-05-25 | 삼성전자주식회사 | 인버터 및 그의 동작방법과 인버터를 포함하는 논리회로 |
CN103928476A (zh) | 2008-10-03 | 2014-07-16 | 株式会社半导体能源研究所 | 显示装置及其制造方法 |
EP2172977A1 (en) | 2008-10-03 | 2010-04-07 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
WO2010038820A1 (en) | 2008-10-03 | 2010-04-08 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
JP5451280B2 (ja) | 2008-10-09 | 2014-03-26 | キヤノン株式会社 | ウルツ鉱型結晶成長用基板およびその製造方法ならびに半導体装置 |
US8106400B2 (en) | 2008-10-24 | 2012-01-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
KR102251817B1 (ko) | 2008-10-24 | 2021-05-12 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 그 제조 방법 |
KR101631454B1 (ko) | 2008-10-31 | 2016-06-17 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 논리회로 |
KR101522400B1 (ko) | 2008-11-10 | 2015-05-21 | 삼성전자주식회사 | 인버터 및 그를 포함하는 논리소자 |
KR101432764B1 (ko) | 2008-11-13 | 2014-08-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체장치의 제조방법 |
KR101291384B1 (ko) | 2008-11-21 | 2013-07-30 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
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KR101477597B1 (ko) | 2015-01-02 |
US20100102314A1 (en) | 2010-04-29 |
US9219158B2 (en) | 2015-12-22 |
KR20140057231A (ko) | 2014-05-12 |
JP2018190992A (ja) | 2018-11-29 |
US20150221778A1 (en) | 2015-08-06 |
KR101732866B1 (ko) | 2017-05-08 |
JP7529867B2 (ja) | 2024-08-06 |
KR101639180B1 (ko) | 2016-07-14 |
US8106400B2 (en) | 2012-01-31 |
JP2014170950A (ja) | 2014-09-18 |
JP2020127031A (ja) | 2020-08-20 |
JP2022084602A (ja) | 2022-06-07 |
CN101728434A (zh) | 2010-06-09 |
JP2016028435A (ja) | 2016-02-25 |
JP6694015B2 (ja) | 2020-05-13 |
JP2010123939A (ja) | 2010-06-03 |
TWI514569B (zh) | 2015-12-21 |
TW201034189A (en) | 2010-09-16 |
US9000431B2 (en) | 2015-04-07 |
JP2017147452A (ja) | 2017-08-24 |
KR20160086785A (ko) | 2016-07-20 |
JP2023169158A (ja) | 2023-11-29 |
JP6118861B2 (ja) | 2017-04-19 |
KR20100045922A (ko) | 2010-05-04 |
US20120104386A1 (en) | 2012-05-03 |
CN101728434B (zh) | 2014-08-06 |
CN104078512B (zh) | 2018-07-17 |
CN104078512A (zh) | 2014-10-01 |
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