TWI553754B - 用於藉由至密封表面之導線接合之疊合封裝組合之方法 - Google Patents

用於藉由至密封表面之導線接合之疊合封裝組合之方法 Download PDF

Info

Publication number
TWI553754B
TWI553754B TW102106326A TW102106326A TWI553754B TW I553754 B TWI553754 B TW I553754B TW 102106326 A TW102106326 A TW 102106326A TW 102106326 A TW102106326 A TW 102106326A TW I553754 B TWI553754 B TW I553754B
Authority
TW
Taiwan
Prior art keywords
wire
substrate
microelectronic
sealing layer
edge
Prior art date
Application number
TW102106326A
Other languages
English (en)
Other versions
TW201347059A (zh
Inventor
瑞拿杜 科
勞瑞 米卡瑞密
Original Assignee
英帆薩斯公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英帆薩斯公司 filed Critical 英帆薩斯公司
Publication of TW201347059A publication Critical patent/TW201347059A/zh
Application granted granted Critical
Publication of TWI553754B publication Critical patent/TWI553754B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45155—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1052—Wire or wire-like electrical connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Mechanical Engineering (AREA)

Description

用於藉由至密封表面之導線接合之疊合封裝組合之方法
本發明之實施例係關於製作可用於疊合封裝組合中之微電子封裝之各種結構及方式，且更特定而言，係關於併入導線接合作為該等疊合封裝連接之部分之此等結構。
相關申請案之交叉參考
本申請案係於2013年1月29日提出申請之美國專利申請案第13/752,485號之一接續案，美國專利申請案第13/752,485號係於2012年2月24日提出申請之美國專利申請案第13/405,125號、即2013年2月12日發佈之現在的美國專利第8,372,741號之一接續案，該等專利專利申請案之揭示內容以引用的方式併入本文中。
諸如半導體晶片之微電子裝置通常需要至其他電子組件之諸多輸入及輸出連接。一半導體晶片或其他相當裝置之輸入及輸出觸點通常安置成實質上覆蓋裝置之一表面之網格狀圖案(通常稱為一「區域陣列」)，或成可平行於且毗鄰裝置之前表面之每一邊緣或在該前表面之中心延伸之細長列。通常，諸如晶片之裝置必須物理安裝於諸如一印刷電路板之一基板上，且該裝置之觸點必須電連接至該電路板之導電特徵。
半導體晶片通常提供於在製造期間及在將晶片安裝於諸如一電 路板或其他電路面板之一外部基板上期間促進晶片之處置之封裝中。舉例而言，諸多半導體晶片係提供於適於表面安裝之封裝中。此一般類型之眾多封裝已經提議用於各種應用。最通常地，此等封裝包含一介電元件，其通常稱為一「晶片載體」，具有在該介電質上形成為經電鍍或經蝕刻金屬結構之端子。此等端子通常藉由諸如沿著晶片載體自身延伸之薄跡線之特徵及藉由在晶片之觸點與端子或跡線之間延伸的細引線或導線而連接至晶片自身之觸點。在一表面安裝操作中，將封裝放置至一電路板上，以使得該封裝上之每一端子與該電路板上之一對應接觸襯墊對準。將焊料或其他接合材料提供於端子與接觸襯墊之間。可藉由加熱該組合以便熔融或「迴銲」焊料或以其他方式活化接合材料而將封裝永久地接合於適當位置處。
諸多封裝包含附接至封裝之端子之呈焊料球(通常直徑約0.1 mm及約0.8 mm(5密耳及30密耳))形式之焊料塊。具有自其底表面突出之一焊料球陣列之一封裝通常稱為一球柵陣列或「BGA」封裝。其他封裝(稱為平臺柵格陣列或「LGA」封裝)係藉由由焊料形成之薄層或平臺固定至基板。此類型之封裝可相當緊湊。某些封裝(通常稱為「晶片尺度封裝」)佔用等於或僅稍微大於併入該封裝中之裝置之面積之電路板之一面積。此有利之處在於：其減小組合之總大小且准許基板上之各種裝置之間的短互連之使用，此繼而限制裝置之間的信號傳播時間且因此促進以高速度對組合之操作。
經封裝半導體晶片通常以「堆疊式」配置提供，其中一個封裝(舉例而言)提供於一電路板上，且另一封裝安裝於第一封裝之頂部上。此等配置可允許將若干個不同晶片安裝於一電路板上之一單個佔用面積內，且可進一步藉由提供封裝之間的一短互連而促進高速操作。通常，此互連距離僅稍微大於晶片自身之厚度。針對在一晶片封裝堆疊內達成之互連，必須在每一封裝(最頂部封裝除外)之兩個側上 提供用於機械及電連接之結構。舉例而言，此已藉由在晶片安裝至之基板之兩個側上提供接觸襯墊或平臺而完成，該等襯墊係藉由導電通孔或諸如此類透過基板連接。已使用焊料球或諸如此類來橋接一下部基板之頂部上之觸點與下一較高基板之底部上之觸點之間的間隙。焊料球必須高於晶片之高度以便連接觸點。美國專利申請公開案第2010/0232129號(「'129公開案」)中提供堆疊式晶片配置及互接合構之實例，該美國專利申請公開案之揭示內容以全文引用方式併入本文中。
呈細長支柱或插腳形式之微觸點元件可用於將微電子封裝連接至電路板及用於微電子封裝中之其他連接。在某些例項中，已藉由蝕刻包含一或多個金屬層之一金屬結構以形成微觸點來形成微觸點。蝕刻製程限制微觸點之大小。習用蝕刻製程通常不能形成具有一大的高與最大寬度之比率(在本文中稱為「縱橫比」)之微觸點。難以或不可能形成具有可觀高度及毗鄰微觸點之間的極小節距或間隔之微觸點陣列。此外，藉由習用蝕刻製程形成之微觸點之組態受限。
儘管所有以上所闡述內容在此項技術中進步，但製作及測試微電子封裝之更進一步改良將係所期望的。
一微電子組合可包含具有相對的一第一表面及一第二表面之一基板。一微電子元件可上覆於該第一表面上，且第一導電元件可暴露於該第一表面或該第二表面中之至少一者處。該等第一導電元件中之某些第一導電元件可電連接至該微電子元件。導線接合具有結合至該等導電元件之基底以及遠離該基板及該等基底之端表面。每一導線接合可界定在該基底與該端表面之間延伸的一邊緣表面。一密封層可自該第一表面延伸且填充該等導線接合之間的空間，以使得該等導線接合可藉由該密封層分離。該等導線接合之未經密封部分可由不被該密 封層覆蓋之該等導線接合之該等端表面之至少部分界定。
本文中揭示各種封裝結構，其併入有充當自一基板上之導電元件(例如，導電襯墊)向上延伸之垂直連接件之導線接合。此等導電接合可用於藉助上覆於一介電密封之一表面上之一微電子封裝來進行疊合封裝電連接。另外，本文中揭示用於製作一微電子封裝或一微電子組合之方法之各種實施例。
因此，一種根據本發明之一態樣製作一微電子封裝之方法可包含：a)自一接合工具之一毛細管饋出具有一預定長度之一金屬導線段；b)使用該接合工具將該金屬導線之一部分接合至暴露於一基板之一第一表面處之一導電元件，藉此在該導電元件上形成一導線接合之一基底；c)將該導線之一部分夾緊於該接合工具內；d)在該經夾緊部分與該基底部分之間的一位置處切割該金屬導線以至少部分地界定該導線接合之一端表面，該導電接合之一邊緣表面係界定於該基底與該端表面之間；e)重複步驟(a)至(d)以形成至該基板之複數個該等導電元件之複數個導線接合；及f)然後形成上覆於該基板之該表面上之一介電密封層，其中該密封層經形成以便至少部分地覆蓋該基板之該表面及該等導線接合之部分，以使得該等導線接合之未經密封部分由不被該密封層覆蓋的該等導線接合之一端表面或一邊緣表面中之至少一者之一部分界定。
因此，根據本發明之一態樣，可自一接合工具之一毛細管饋出具有一預定長度之一金屬導線段。該接合工具可用於將該金屬導線之一部分接合至暴露於一基板之一第一表面處之一導電元件。此接合可在該導電元件上形成該導線接合之一基底。該導線之一部分可在形成與導電元件之接合之後被夾緊。所夾緊之導線之部分可係在該接合工具內。可在所夾緊部分與該基底部分之間的一位置處切割該金屬導線，且切割該導線可至少部分地界定該導線接合之一端表面。該導線 接合之一邊緣表面可界定於該基底與該端表面之間。前述可經重複以形成至該基板之複數個該等導電元件之複數個導線接合。然後，可形成上覆於該基板之表面之一介電密封層。該密封層可經形成以便至少部分地覆蓋該基板之表面及該等導線接合之部分。該等導線接合之未經密封部分可由不被該密封層覆蓋的該等導線接合之一端表面或其一邊緣表面中之至少一者之一部分界定。
在一項實例中，可僅部分地穿過該金屬導線切割該金屬導線。可自基板之表面移開該接合工具同時導線之部分保持經夾緊。以此程序，可致使導線在切割之位置處斷裂。可藉由該切割及該斷裂形成一端表面。
在一項實例中，可沿實質上垂直於導線接合之邊緣表面之一方向完全穿過該導線段進行該切割。可藉由該切割形成該導線接合之一端表面。
在一項實例中，至少一個微電子元件可上覆於該基板之該第一表面上。該基板可具有一第一區及一第二區，且該微電子元件可位於該第一區內，例如上覆於該第一區上。該等導電元件可位於該第二區內，例如作為暴露於其中之第一表面處之導電元件。該等導電元件可電連接至該至少一個微電子元件。該介電密封層可經形成為在至少該基板之該第二區中上覆於該基板之第一表面上，但亦可上覆於該第一表面之至少一部分上在第一區以及第二區中。
在一項實例中，該封裝可經組態以使得該等導線接合中之一第一導線接合經調適用於攜載一第一信號電位，且該等導線接合中之一第二導線接合經調適用於同時攜載不同於該第一信號電位之一第二信號電位。
在一項實例中，可使用安裝於該接合工具上之一雷射來切割該金屬導線段。在此實例中，接合工具之毛細管可界定其藉以饋送該導 線段之一面。該雷射可安裝於該接合工具上或與其一起安裝以使得可將一切割光束引導至定位於該接合工具之面與導線接合之基底之間的導線段之一位置。
在一項實例中，該接合工具可包含界定其藉以饋送該導線段之一面之一毛細管。該毛細管可包含在其一側壁中之一開口，且該雷射可安裝於該接合工具上或與其一起安裝以使得一切割光束可通過該開口至定位於該毛細管內之導線段之一位置。
在一項實例中，該雷射可係以下各項中之一者：CO2、Nd：YAG或一Cu蒸氣雷射。
在一項實例中，可使用在毛細管內延伸之一切割刃來切割該金屬導線。在一項實例中，該切割刃可沿朝向該毛細管之與導線段對置之一壁之一方向延伸。在一項實例中，可使用該切割刃作為一第一切割刃且結合在該毛細管內延伸之一第二切割刃來切割該金屬導線。該第二切割刃可與該第一切割刃相對地定位。
在一項實例中，該毛細管可界定可藉以饋送該導線段之一面。可使用具有相對的第一切割刃及第二切割刃之一切割器具來切割該金屬導線。該切割器具可以使得可在定位於該接合工具之面與該導線接合之基底之間的一位置處切割該導線之一方式安裝於該接合工具上或與該接合工具一起安裝。
該方法之一項實例可包含將一模板定位於該基板上方。該模板可在其中具有上覆於且暴露該等導電元件之至少部分之複數個開口。該等開口可界定定位於該基板上方之一第一高度處之各別邊緣。可藉由導線抵靠模板開口之邊緣之橫向移動來切割該導線段。
一種根據本發明之一態樣製作一微電子封裝之方法可包含：將一模板定位於一製程中單元上，該製程中單元包含具有一第一表面及遠離該第一表面之一第二表面之一基板。一微電子元件可安裝至該基 板之第一表面。複數個導電元件可暴露於該第一表面處。在一實例中，該等導電元件中之至少某些導電元件可電連接至該微電子元件。該模板可在其中具有上覆於且暴露該等導電元件之至少部分之複數個開口。該等開口可界定定位於該基板上方之一第一高度處之各別邊緣。
根據此態樣，該方法可包含藉由包含以下步驟之一製程形成一導線接合：自一接合工具之一毛細管饋出一金屬導線以使得一預定長度延伸超過該毛細管之面且界定一金屬導線段。該導線段之一部分可結合至該複數個導電元件中之一導電元件以形成該導電接合之一基底。該金屬導線段之至少一部分可藉由導線抵靠模板開口之邊緣之橫向移動而自連接至該金屬導線段之導線之另一部分剪切，以分離該導線接合與該導線之一剩餘部分。該金屬導線之剪切可界定該導線接合之一端表面，該導線接合具有在該基底與該端表面之間延伸之一端表面。可使用該模板之一或多個開口複數次地重複如以上闡述之金屬導線之饋出、接合及其剪切，以在複數個該等導電元件上形成複數個導線接合。
在此方法之一實例中，可在該製程中單元上形成一介電密封層，其中該密封層經形成以便至少部分地覆蓋該第一表面及該等導線接合之部分。該等導線接合之未經密封部分可由不被該密封層覆蓋之該等導線接合之端表面或邊緣表面中之至少一者之一部分界定。
在此方法之一實例中，延伸超過該毛細管之一面且在該金屬導線之剪切之後剩餘的該金屬導線之一部分可係為足以至少形成一後續導線接合之一基底之一長度。
在該方法之一實例中，該模板可界定沿該等孔中之一者之一軸延伸之一方向(例如，沿背離該基板之一表面之一垂直方向)之一厚度。該等孔中之某些或全部可貫穿該模板之厚度具有一致或恆定直 徑。
在該方法之一實例中，該模板可界定沿該等孔或開口中之一者之一軸之一方向(例如，沿背離該基板之一表面之一垂直方向)之一厚度。該模板中之該等孔或開口中之某些或全部可自該開口內之一暴露邊緣處之一第一寬度或較小直徑漸變至在該孔或開口內且較接近該基板之另一位置處之一第二較大寬度或較大直徑。
在一項實例中，該模板可包含沿該基板之一或多個邊緣延伸之具有該基板之一厚度方向之一第一厚度之一邊緣部件。該第一厚度可界定一第一高度。一中心部分可包含該等孔或開口且可由該邊緣部件定界。該中心部分可具有背對該基板之一外部表面。該外部表面可安置於該第一高度處。該中心部分可具有小於該第一厚度之一厚度。
10‧‧‧微電子組合
10'‧‧‧微電子組合
10"‧‧‧微電子組合
10'''‧‧‧微電子組合
12‧‧‧基板
14‧‧‧第一表面
16‧‧‧第二表面
18‧‧‧第一區
20‧‧‧第二區
22‧‧‧微電子元件
24‧‧‧導線引線
26‧‧‧塊
28‧‧‧導電元件
30‧‧‧襯墊
32‧‧‧導線接合
32'‧‧‧導線環路之部分
34‧‧‧基底
36‧‧‧端/自由端
37‧‧‧邊緣表面
38‧‧‧端表面/端
40‧‧‧第二導電元件/導電元件
41‧‧‧通孔
42‧‧‧密封層/端表面
43‧‧‧小表面
44‧‧‧主表面/表面
52‧‧‧焊料塊
54‧‧‧再分佈層
56‧‧‧基板
58‧‧‧跡線
60‧‧‧接觸襯墊
61‧‧‧內部接觸襯墊
62‧‧‧表面
64‧‧‧腔
66‧‧‧介電底填充層
70‧‧‧圓形端部分
71‧‧‧邊緣表面
72‧‧‧柱形凸塊
74‧‧‧端之一部分
75‧‧‧鉤狀部分
76‧‧‧邊緣表面
78‧‧‧犧牲材料塊/塊
94‧‧‧第二基板/第二微電子組合
96‧‧‧接觸襯墊
98‧‧‧基板
110‧‧‧微電子組合
112‧‧‧基板
114‧‧‧第一表面
116‧‧‧第二表面
118‧‧‧第一區
122‧‧‧微電子元件
126‧‧‧焊料凸塊
128‧‧‧導電元件
132‧‧‧導線接合
132A‧‧‧導線接合
132B‧‧‧端
134‧‧‧基底
134B‧‧‧導線接合
136‧‧‧端
138‧‧‧端
138A‧‧‧端表面
138B‧‧‧端表面
142‧‧‧密封層
144‧‧‧表面
146‧‧‧角/第一平面展示角
210‧‧‧微電子子組合
232‧‧‧導線接合
234‧‧‧基底
236‧‧‧端
248‧‧‧彎曲部分
310‧‧‧微電子組合
312‧‧‧基板
322‧‧‧微電子元件
324‧‧‧引線
332A‧‧‧導線接合
332B‧‧‧導線接合
332Ci‧‧‧導線接合
332Cii‧‧‧導線接合
332D‧‧‧導線接合
334A‧‧‧基底
334B‧‧‧基底
334Ci‧‧‧基底
334Cii‧‧‧基底
336‧‧‧端
336B‧‧‧端
336Ci‧‧‧端
336Cii‧‧‧端
336D‧‧‧自由端
337A‧‧‧邊緣表面
337D‧‧‧邊緣表面
338‧‧‧端表面
342‧‧‧密封層/主表面
344‧‧‧表面
345‧‧‧凹入表面
348C‧‧‧彎曲部分
350‧‧‧微電子元件
382‧‧‧引線
384‧‧‧導線接合
386‧‧‧接觸表面
410‧‧‧微電子組合
412‧‧‧基板
421‧‧‧絕緣層
422‧‧‧微電子元件
426‧‧‧後表面
428‧‧‧導電元件
432‧‧‧導線接合
434‧‧‧基底
436‧‧‧端/未經密封表面
438‧‧‧端表面
440‧‧‧導電元件/接觸襯墊
448‧‧‧彎曲部分
452‧‧‧焊料球
488‧‧‧微電子組合/組合/封裝
489‧‧‧微電子元件
490‧‧‧印刷電路板
492‧‧‧觸點/襯墊
512‧‧‧基板
513‧‧‧引線
515‧‧‧銲盤
518‧‧‧第一區
520‧‧‧第二區
524‧‧‧導線接合
528‧‧‧導電元件
532‧‧‧導線接合
534‧‧‧基底
538‧‧‧端
612‧‧‧基板
616‧‧‧表面
622‧‧‧微電子元件
624‧‧‧導線接合
625‧‧‧導線接合
699‧‧‧外模製件
710‧‧‧微電子組合
711‧‧‧系統
713‧‧‧電子組件
715‧‧‧電子組件
717‧‧‧電路面板
719‧‧‧殼體
721‧‧‧導體
723‧‧‧透鏡
800‧‧‧導線/導線段
803‧‧‧夾具/切割刀片/導線夾具
804‧‧‧毛細管
805‧‧‧切割刀片/刀片
806‧‧‧面
807‧‧‧開口
809‧‧‧雷射/雷射頭
810‧‧‧微電子封裝/封裝
812‧‧‧基板
820‧‧‧微電子元件
821‧‧‧外部框架/框架
823‧‧‧腔/開放區域
824‧‧‧模板
826‧‧‧上部表面/表面/外部表面
828‧‧‧導電元件
828a‧‧‧導電元件
828b‧‧‧導電元件
829‧‧‧邊緣
832‧‧‧導線接合
834a‧‧‧基底
834b‧‧‧基底
837a‧‧‧邊緣表面部分
837b‧‧‧邊緣表面部分
839‧‧‧頂端
844‧‧‧表面
928‧‧‧導電元件
934a‧‧‧第一基底
934b‧‧‧第二基底
937a‧‧‧邊緣表面部分
937b‧‧‧邊緣表面部分
939‧‧‧頂端
944‧‧‧主表面
1428‧‧‧導電元件
1432‧‧‧導線接合
1439‧‧‧暴露部分
1444‧‧‧表面
1622‧‧‧下部微電子元件/第一微電子元件
1628‧‧‧導電元件
1650‧‧‧第二微電子元件
1688‧‧‧導線接合
1722‧‧‧第一微電子元件
1728‧‧‧導電元件
1750‧‧‧第二微電子元件
1788‧‧‧導線接合
1822‧‧‧第一微電子元件
1828‧‧‧導電元件
1850‧‧‧第二微電子元件
圖1展示根據本發明之一實施例之一微電子封裝；圖2展示圖1之微電子封裝之一俯視立面圖；圖3展示根據本發明之一替代實施例之一微電子封裝；圖4展示根據本發明之一替代實施例之一微電子封裝；圖5展示根據本發明之一替代實施例之一微電子封裝；圖6展示根據本發明之一實施例之包含一微電子封裝之一堆疊式微電子組合；圖7展示根據本發明之一替代實施例之一微電子封裝；圖8A至圖8E展示根據本發明之各種實施例之一微電子封裝之一部分之一詳細視圖；圖9展示根據本發明之一替代實施例之一微電子封裝之一部分之一詳細視圖；圖10A至圖10D展示根據本發明之各種實施例之一微電子封裝之一部分之一詳細視圖； 圖11至圖14展示根據本發明之一實施例在一微電子封裝之各種製作步驟期間之該微電子封裝；圖15展示根據本發明之一替代實施例在一製作步驟期間之一微電子封裝；圖16A至圖16C展示根據本發明之一實施例在一微電子封裝之各種製作步驟期間之該微電子封裝之一部分之一詳細視圖；圖17A至圖17C展示根據本發明之一替代實施例在一微電子封裝之各種製作步驟期間之該微電子封裝之一部分之一詳細視圖；圖18展示根據本發明之一替代實施例之一微電子封裝之一俯視立面圖；圖19展示根據本發明之一替代實施例之一微電子封裝之一部分之一俯視立面圖；圖20展示根據本發明之另一替代實施例之一微電子封裝之一俯視圖；圖21展示技術方案20之微電子封裝之一前立面圖；圖22展示根據本發明之另一替代實施例之一微電子封裝之一前立面圖；圖23展示根據本發明之另一實施例之一系統；圖24展示根據本發明之另一替代實施例之一微電子封裝之一前立面圖；圖25展示根據本發明之另一替代實施例之一微電子封裝之一前立面圖；圖26展示根據圖25之實施例之一變化形式之一微電子封裝之一俯視圖；圖27展示根據本發明之另一替代實施例之一微電子封裝之一前立面圖； 圖28展示根據圖27之實施例之一變化形式之一微電子封裝之一俯視圖；圖29係根據另一實施例之一微電子封裝之一剖視圖；圖30展示根據另一實施例之一微電子封裝之一剖視圖；圖31A至圖31C係展示根據另一些實施例之微電子封裝之實施例之實例之剖視圖；圖32A及圖32B展示根據本發明之另一實施例可用於在一方法之各種階段中形成各種導線接合通孔之一機器之一部分；圖33展示根據本發明之另一實施例可用於根據一方法形成各種導線接合通孔之一機器之一部分；且圖34A至圖34C展示根據本發明之一實施例可用於製作導線接合之一方法中之一器具之各種形式。
現在轉至圖，其中類似元件符號用於指示類似特徵，圖1中展示根據本發明之一實施例之一微電子組合10。圖1之實施例係呈一經封裝微電子元件之形式之一微電子組合，諸如用於電腦或其他電子應用中之一半導體晶片組合。
圖1之微電子組合10包含具有一第一表面14及一第二表面16之一基板12。基板12通常呈一介電元件(其係實質上扁平)之形式。該介電元件可係片狀且可係薄的。在特定實施例中，該介電元件可包含有機介電材料或複合介電材料之一或多個層，該等機介電材料或複合介電材料諸如(但不限於)：聚醯亞胺、聚四氟乙烯(「PTFE」)、環氧樹脂、環氧玻璃、FR-4、BT樹脂、熱塑性材料或熱固性塑膠材料。第一表面14及第二表面16較佳地實質上彼此平行且以界定基板12之厚度之垂直於表面14、16之一距離間隔開。基板12之厚度較佳地在本申請案大體可接受厚度之一範圍內。在一實施例中，第一表面14與第二表 面16之間的距離在約25 μm與500 μm之間。出於此論述之目的，第一表面14可闡述為與第二表面16對置或遠離第二表面16定位。此一闡述以及本文中所使用之涉及此等元件之一垂直或水平位置之元件相對位置之任何其他闡述係僅出於說明性目的而進行以符合圖內之元件之位置，且並非限制。
在一較佳實施例中，將基板12視為劃分成一第一區18及一第二區20。第一區18位於第二區20內且包含基板12之一中心部分且自其向外延伸。第二區20實質上包圍第一區18且自其向外延伸至基板12之外部邊緣。在此實施例中，基板自身不存在實體劃分兩個區之特定特性；然而，本文中出於論述之目的而將該等區相對於應用於其或含納於其中之處理或特徵加以區分。
一微電子元件22可安裝至基板12在第一區18內之第一表面14。微電子元件22可係一半導體晶片或另一相當裝置。在圖1之實施例中，微電子元件22係以稱為一習用或「面向上」方式之方式安裝至第一表面14。在此一實施例中，導線引線24可用於將微電子元件22電連接至暴露於第一表面14處之複數個導電元件28中之某些導電元件。導線引線24亦可結合至基板12內之繼而連接至導電元件28之跡線(未展示)或其他導電特徵。
導電元件28包含暴露於基板12之第一表面14處之各別「觸點」或襯墊30。如本闡述中所使用，當將一導電元件闡述為「暴露於」具有介電結構之另一元件之表面處時，指示該導電結構可用於與沿垂直於該介電結構之該表面之一方向自該介電結構外部朝向該介電結構之該表面移動之一理論點接觸。因此，暴露於一介電結構之一表面處之一端子或其他導電結構可自此表面突出；可與此表面齊平；或可相對於此表面凹入且透過該介電質中之一孔或凹部暴露。導電元件28可係其中襯墊30暴露於基板12之第一表面14處之扁平、薄元件。在一項實 施例中，導電元件28可係實質上圓形且可藉由跡線(未展示)在彼此之間互連或互連至微電子元件22。導電元件28可至少形成於基板12之第二區20內。另外，在某些實施例中，導電元件28亦可形成於第一區18內。此一配置當將微電子元件122(圖3)以稱為一「覆晶」組態之組態安裝至基板112時特別有利，其中微電子元件122上之觸點可藉由定位於微電子元件122下面之焊料凸塊126或諸如此類連接至第一區118內之導電元件128。在如圖22中所展示之另一組態中，微電子元件622面向下安裝於基板612上且藉由在基板612之一面向外表面(諸如表面616)上方延伸之導線引線624電連接至晶片上之一導電特徵。在所展示之實施例中，導線引線625通過基板612中之一開口625且可藉由一外模製件699密封。
在一實施例中，導電元件28由一固態金屬材料形成，諸如銅、金、鎳或此一申請案可接受之其他材料，包含各種合金(包含銅、金、鎳或其組合中之一或多者)。
導電元件28中之至少某些導電元件可互連至暴露於基板12之第二表面16處之對應第二導電元件40，諸如導電襯墊。可使用形成於基板12中之通孔41來完成此一互連，該等通孔可加襯或填充有可係為與導電元件28或40相同之材料之導電金屬。視情況地，導電元件40可藉由基板12上之跡線進一步互連。
微電子組合10進一步包含諸如在導電元件28之襯墊30上結合至該等導電元件中之至少某些導電元件之複數個導線接合32。導線接合32在其一基底34處結合至導電元件28且可延伸至遠離各別基底34且遠離基板12之一自由端36。由於導線接合32之端36不電連接或以其他方式結合至微電子組合10內之微電子元件22或繼而連接至微電子元件22之任何其他導電特徵，因此其表徵為係自由的。換言之，自由端36可用於直接地或間接地(如透過本文中所論述之一焊料球或其他特徵)電 子連接至組合10外部之一導電特徵。端36藉由(舉例而言)密封層42保持於一預定位置中或以其他方式結合或電連接至另一導電特徵之事實並不意味著其非如本文中所闡述之「自由」，只要任何此特徵不電連接至微電子元件22即可。相反地，如本文中所闡述，由於基底34直接地或間接地電連接至微電子元件22，因此其係不自由的。如圖1中所展示，基底34可係實質上圓形形狀，自基底34與端36之間所界定之導線接合32之一邊緣表面37向外延伸。基底34之特定大小及形狀可根據以下各項而變化：用於形成導線接合32之材料之類型，導線接合32與導電元件28之間的連接之所期望強度或用於形成導線接合32之特定製程。用於製作導線接合28之例示性方法闡述於Otremba之美國專利第7,391,121號及美國專利申請公開案第2005/0095835號(闡述可視為一種形式之導線接合之一楔接合步驟)中，該等文檔之揭示內容皆以全文引用方式併入本文中。替代實施例係可行的，其中，導線接合32(另外地或另一選擇係)結合至暴露於基板12之第二表面16上之導電元件40，從而背離其延伸。
導線接合32可由諸如銅、金、鎳、焊料、鋁或諸如此類之一導電材料製作。另外，導線接合32可由材料之組合製作，諸如由一導電材料(諸如銅或鋁)之一核心與施加於該核心上之一塗層一起製作。該塗層可係為一第二導電材料，諸如鋁、鎳或諸如此類。另一選擇係，該塗層可係為一絕緣材料，諸如一絕緣套。在一實施例中，用於形成導線接合32之導線可具有在約15 μm與150 μm之間的一厚度，亦即，橫切於線之長度之一尺寸。在包含其中使用楔接合之彼等導線接合之其他實施例中，導線接合32可具有高達約500 μm之一厚度。一般而言，一導線接合係使用此項技術中所習知之專門設備形成於一導電元件上，諸如導電元件28、一襯墊、跡線或諸如此類。一導線段之一引線端經加熱且壓抵該導線段接合至之接納表面，通常形成結合至導電 元件28之表面之一球或球狀基底34。自接合工具拉延用以形成導線接合之所期望長度之線段，該接合工具可然後在所期望長度處切割該導線接合。舉例而言，可用於形成鋁導線接合之楔接合係其中跨越接納表面拖曳導線之經加熱部分以形成大體平行於該表面伸展之一楔之一製程。該經楔接合之導線接合可然後向上彎折(視需要)，且在切割之前延伸至所期望長度或位置。在一特定實施例中，用於形成一導線接合之導線之剖面可係圓柱形。另外，自工具饋送以形成一導線接合或經楔接合之導線接合之導線可具有一多邊形剖面，諸如(舉例而言)矩形或梯形。
導線接合32之自由端36具有一端表面38。端表面38可在由複數個導線接合32之各別端表面38形成之一陣列中形成一觸點之至少一部分。圖2展示藉由端表面38形成之觸點之此一陣列之一例示性圖案。此一陣列可形成為一面陣列組態，可使用本文中所闡述之結構實施該組態之變化形式。此一陣列可用於將微電子組合10電及機械連接至另一微電子結構，諸如至一印刷電路板(「PCB」)，或至其他經封裝微電子元件(圖6中展示其一實例)。在此一堆疊式配置中，導線接合32及導電元件28及40可攜載通過其之多個電子信號，每一電子信號具有一不同信號電位以允許一單個堆疊中之不同微電子元件處理不同信號。焊料塊52可用於互連此一堆疊中之微電子組合，諸如藉由將端表面38電子及機械地附接至導電元件40。
微電子組合10進一步包含由一介電材料形成之一密封層42。在圖1之實施例中，密封層42形成於不被微電子元件22或導電元件28以其他方式覆蓋或佔用之基板12之第一表面14之部分上方。類似地，密封層42形成於不被導線接合32以其他方式覆蓋之導電元件28(包含其襯墊30)之部分上方。密封層42亦可實質上覆蓋微電子元件22、導線接合32(包含基底34及其邊緣表面37之至少一部分)。導線接合32之一 部分可保持不被密封層42覆蓋，此亦可稱為未經密封，藉此使導線接合可用於電連接至位於密封層42之外部之一特徵或元件。在一實施例中，導線接合32之端表面38保持在密封層42之主表面44內不被密封層42覆蓋。除了使端表面38保持不被密封層42覆蓋以外或作為其一替代方案，其中邊緣表面37之一部分不被密封層42覆蓋之其他實施例亦係可行的。換言之，密封層42可覆蓋自第一表面14以及往上之微電子組合10之全部，惟導線接合36之一部分(諸如端表面38、邊緣表面37或該兩者之組合)除外。在圖中所展示之實施例中，密封層42之一表面(諸如主表面44)可與基板12之第一表面14間隔開足夠大以覆蓋微電子元件22之一距離。相應地，其中導線接合32之端38與表面44齊平之微電子組合10之實施例將包含高於微電子元件22之導線接合32，及用於覆晶連接之任何下伏焊料凸塊。然而，密封層42之其他組態亦係可行的。舉例而言，密封層可具有帶不同高度之多個表面。在此一組態中，端38定位於其內之表面44可高於或低於微電子元件22位於其下方之一面向上表面。
密封層42用於保護微電子組合10內之其他元件，特定而言導線接合32。此允許較不可能被其測試或在運輸或裝配至其他微電子結構損壞之一較穩健結構。密封層42可由具有絕緣性質之一介電材料(諸如美國專利申請公開案第2010/0232129號中所闡述之材料)形成，該美國專利申請公開案以全文引用方式併入本文中。
圖3展示具有導線接合132之微電子組合110之一實施例，該等導線接合具有並非直接定位於其各別基底34上方之端136。亦即，將基板112之第一表面114視為沿兩個橫向方向延伸，以便實質上界定一平面，端136或導線接合132中之至少一者自基底134之一對應橫向位置沿此等橫向方向中至少一者位移。如圖3中所展示，導線接合132可係沿著其縱向軸實質上筆直(如在圖1之實施例中)，其中縱向軸相對於 基板112之第一表面114以一角146成角。儘管圖3之剖面圖僅透過垂直於第一表面114之一第一平面展示角146，但導線接合132亦可在垂直於彼第一平面及第一表面114兩者之另一平面中相對於第一表面114成角。此一角可實質上等於或不同於角146。亦即，端136相對於基底134之位移可係沿兩個橫向方向且可沿彼等方向中之每一者達相同或一不同距離。
在一實施例中，導線接合132中之各種者可沿不同方向位移且貫穿組合110達不同量。此一配置允許組合110具有與在基板12之層級上相比在表面144之層級上經不同組態之一陣列。舉例而言，與基板112之第一表面114處之彼陣列相比較，一陣列在表面144上可比在第一表面114層級處覆蓋一更小總面積或具有一更小節距。此外，某些導線接合132可具有定位於微電子元件122上方以適應不同大小之經封裝微電子元件之一堆疊式配置之端136。在圖19中所展示之另一實例中，導線接合132可經組態以使得一個導線接合132A之端表面138A實質上定位於另一導線接合132B之基底134B上方，彼導線接合132B之端表面138B定位於別處。此一配置可稱為與第二表面116上之一對應觸點陣列之位置相比較改變一觸點陣列內之一觸點端表面138之相對位置。在此一陣列內，取決於微電子組合之應用或其他要求，觸點端表面之相對位置可視需要改變或變化。
在圖30中展示之另一實例中，導線接合132可經配置以使得以具有其一節距之一第一圖案配置基底134。導線接合132可經組態以使得其未經密封部分139(包含端表面138)可以一圖案安置於密封層142之一主表面144處之位置處，該等位置具有大於附接至導電元件128之導電接合之各別毗鄰基底134之間的一最小節距之一最小節距。相應地，在密封表面146處之毗鄰導線接合之間的最小節距可大於該等導線接合附接至之基板之導電元件128之間的對應最小節距。
為達成此，該等導線接合可成角度(如圖30中所展示)或可如(舉例而言)圖4中所展示而彎曲，以使得端表面138沿一或多個橫向方向自基底134位移，如上文所論述。如圖30中進一步展示，導電元件128及端表面138可配置成各別列或行，且一個列中之端表面138之橫向位移可大於另一列中。為達成此，導線接合132可(舉例而言)相對於基板112之表面116成不同角146A、146B。
圖4展示具有導線接合232之一微電子子組合210之另一實施例，導線接合232具有在相對於基底234橫向位移之位置中之端236。在圖4之實施例中，導線接合132藉由其中包含一彎曲部分248而達成此橫向位移。彎曲部分248可在導線接合形成製程期間在一額外步驟中形成，且可發生(舉例而言)在導線部分經拉延至所期望長度時。可使用可用導線接合設備來實施此步驟，此可包含一單個機器之使用。
彎曲部分248可視需要呈現各種形狀以達成導線接合232之端236之所期望位置。舉例而言，彎曲部分248可經形成為各種形狀之S曲線(諸如圖4中所展示之S曲線)，或一較平滑形式之S曲線(諸如圖5中所展示之S曲線)。另外，彎曲部分248可經定位為較接近基底234而非端236，或反之亦然。彎曲部分248亦可呈一螺旋或環路形式，或可係複合的，包含沿多個方向或具有不同形狀或特性之曲線。
圖5展示具有導線接合332之一組合之一微電子封裝310之另一例示性實施例，導線接合332具有導致基底334與端336之間的各種相對橫向位移之各種形狀。導線接合332A中之某些導線接合係實質上筆直的，其中端336A定位於其各別基底334A上方，而其他導線接合332B包含導致端336B與基底334B之間的一稍微相對橫向位移之一略彎曲部分348B。進一步地，某些導線接合332C包含具有一大幅彎曲形狀之彎曲部分348C，此導致產生以大於端334B之彼距離之一距離自相對基底334C橫向位移之端336C。圖5亦展示一對例示性此等導線 接合332Ci及332Cii，其具有具有定位於一基板層級陣列之相同列中之基底334Ci及334Cii，及定位於一對應表面層級陣列之不同列中之端336Ci及336Cii。
一導線接合332D之另一變化形式展示為經組態以在其一側表面47上不被密封層342覆蓋。在所展示實施例中，自由端336D不被覆蓋，然而，另外地或另一選擇係，邊緣表面337D之一部分可不被密封層342覆蓋。此一組態可用於微電子組合10之接地(藉由電連接至一適當特徵)或用於機械或電連接至相對於微電子組合310橫向安置之其他特徵。另外，圖5展示密封層342之一區域，該區域已經蝕除、模製或以其他方式形成以界定經定位成較接近於基板12而非主表面342之一凹入表面345。一或多個導線接合(諸如導線接合332A)可在沿著凹入表面345之一區域內不被覆蓋。在圖5中所展示之例示性實施例中，端表面338A及邊緣表面337A之一部分不被密封層342覆蓋。此一組態可藉由允許焊料沿著邊緣表面337A芯吸(wick)且除結合至端表面338外亦結合至邊緣表面337A而提供至另一導電元件之一連接(諸如藉由一焊料球或諸如此類)。一導線接合之一部分可沿著凹入表面345不被密封層342覆蓋之其他組態亦係可行的，包含其中端表面與凹入表面345實質上齊平之組態或本文中展示之關於密封層342之任何其他表面之其他組態。類似地，導線接合332D之一部分沿著側表面347不被密封層342覆蓋之其他組態可類似於本文中別處關於密封層之主表面之變化形式所論述之彼等組態。
圖5進一步展示在一例示性配置中具有兩個微電子元件322及350之一微電子組合310，其中微電子元件350面向上堆疊於微電子元件322上。在此配置中，使用引線324以將微電子元件322電連接至基板312上之導電特徵。使用各種引線以將微電子元件350電子連接至微電子組合310之各種其他特徵。舉例而言，引線380將微電子元件350電 連接至基板312之導電特徵，且引線382將微電子元件350電連接至微電子元件322。進一步地，可使用在結構上類似於導線接合332之各種結構之導線接合384以在密封層342之表面344上形成電連接至微電子元件350之一接觸表面386。此可用於將另一微電子組合之一特徵自密封層342上方直接電連接至微電子元件350。亦可包含連接至微電子元件322之一引線，包含當在無貼附於其上之一第二微電子元件350之情況下存在此一微電子元件。一開口(未展示)可形成於密封層342中，該開口自該密封層之表面344延伸至沿著(舉例而言)引線380之一點，藉此提供對引線380之接達以藉由定位於表面344外部之一元件而電連接至其。一類似開口可形成於其他引線或導線接合332中之任何者上方，諸如在遠離其端336C之一點處之導線接合332C上方。在此一實施例中，端336C可定位於表面344下面，其中開口提供用於電連接至其之唯一接達。
圖6展示微電子組合410及488之一堆疊式封裝。在此一配置中，焊料塊452將組合410之端表面438電連接且機械連接至組合488之導電元件440。該堆疊式封裝可包含額外組合，且可最終附接至一PCB 490或諸如此類上之觸點492供用於一電子裝置中。在此一堆疊式配置中，導線接合432及導電元件430可攜載穿過其之多個電子信號，每一信號具有一不同信號電位以允許一單個堆疊中之不同微電子元件(諸如，微電子元件422或微電子元件489)處理不同信號。
在圖6中之例示性組態中，導線接合432經組態為具有一彎曲部分448，以使得導線接合432之端436中之至少某些端延伸至上覆於微電子元件422之一主表面424上之一區域中。此一區域可由微電子元件422之外部周邊界定且自其向上延伸。根據面朝向圖18中之基板412之第一表面414之一視圖展示此一組態之一實例，其中導線接合432上覆於微電子元件422之一後主表面上，微電子元件422在其一前面425處 覆晶接合至基板412。在另一組態中(圖5)，微電子元件422可面向上安裝至基板312，其中前面325背對基板312且至少一個導線接合336上覆於微電子元件322之前面上。在一項實施例中，此導線接合336不與微電子元件322電連接。接合至基板312之一導線接合336亦可上覆於微電子元件350之前面或後面上。圖18中所展示之微電子組合410之實施例使得導電元件428配置成形成一第一陣列之一圖案，其中導電元件428包圍微電子元件422配置成列及行且在個別導電元件428之間可具有一預定節距。導線接合432結合至導電元件428以使得其各別基底434沿循如藉由導電元件428所陳述之第一陣列之圖案。然而，導線接合432經組態以使得其各別端436可根據一第二陣列組態配置成一不同圖案。在所展示之實施例中，第二陣列之節距可不同於(且在某些情形下細於)第一陣列之節距。然而，其中第二陣列之節距大於第一陣列或其中導電元件428未定位於一預定陣列中但導線接合432之端436定位於該預定陣列中之其他實施例係可行的。此外，導電元件428可經組態成貫穿基板412定位之陣列組，且導線接合432可經組態以使得端436在不同陣列組中或在一單個陣列中。
圖6進一步展示沿著微電子元件422之一表面延伸之一絕緣層421。絕緣層421可在形成導線接合之前由一介電質或其他電絕緣材料形成。絕緣層421可保護微電子元件免於與在其上方延伸之導線接合423中之任何者接觸。特定而言，絕緣層421可避免導線接合之間的電短路及一導線接合與微電子元件422之間的短路。以此方式，絕緣層421可幫助避免由於一導線接合432與微電子元件422之間的非預期電接觸所致之故障或可能損壞。
在其中(舉例而言)微電子組合488及微電子元件422之相對大小原本不被准許之某些例項中，圖6及圖18中所展示之導線接合組態可允許微電子組合410連接至另一微電子組合(諸如，微電子組合488)。在 圖6之實施例中，微電子組合488經定大小以使得接觸襯墊440中之某些接觸襯墊係在小於微電子元件422之前表面424或後表面426之區域之一區域內呈一陣列。在具有實質上垂直導電特徵(諸如柱)替代導線接合432之一微電子組合中，導電元件428與襯墊440之間的直接連接將不可行。然而，如圖6中所展示，具有經適當組態之彎曲部分448之導線接合432可使端436位於適當位置中，以進行微電子組合410與微電子組合488之間的必需電子連接。此一配置可用於製作一堆疊式封裝，其中微電子組合418(舉例而言)係具有一預定襯墊陣列之一DRAM晶片或諸如此類，且其中微電子元件422係經組態以控制DRAM晶片之一邏輯晶片。由於導線接合432可使端436定位於必須與DRAM晶片進行所期望連接之任何位置處，因此此可允許一單個類型之DRAM晶片與不同大小之數種不同邏輯晶片(包含大於DRAM晶片之彼等晶片)一起使用。在一替代實施例中，微電子封裝410可以另一組態安裝於印刷電路板490上，其中導線接合432之未經密封表面436電連接至電路板490之襯墊492。進一步地，在此一實施例中，另一微電子封裝(諸如封裝488之一修改版本)可藉由結合至襯墊440之焊料球452安裝於封裝410上。
圖31A至圖31C中展示針對具有多個微電子元件之微電子封裝之額外配置。可結合(舉例而言)圖5中及下文進一步論述之圖6之堆疊式封裝配置中所展示之導線接合配置來使用此等配置。具體而言，圖31A展示其中一下部微電子元件1622覆晶接合至基板1612之表面1614上之導電元件1628之一配置。第二微電子元件1650面向上安裝於第一微電子元件1622之頂部上，且透過導線接合1688連接至額外導電元件1628。圖31B展示其中一第一微電子元件1722面向上安裝於表面1714上且透過導線接合1788連接至導電元件1728之一配置。第二微電子元件1750透過第二微電子元件1750之一組觸點1726覆晶安裝於第一微電 子元件1722之頂部上，該組觸點面向且結合至第一微電子元件1722之前面上之對應觸點。第一微電子元件1722上之此等觸點繼而可透過第一微電子元件1722之電路圖案連接且藉由導線接合1788中之某些導線接合連接至基板1712上之導電元件1728。
圖31C展示其中第一微電子元件1822及第二微電子元件1850並排安裝於基板1812之表面1814上之一配置。可以本文所闡述之面向上或覆晶組態安裝該等微電子元件中之任一者或兩者(及額外微電子元件)。進一步地，在此一配置中採用之微電子元件中之任一者可透過一個或兩個此等微電子元件上或基板上或兩者上之電路圖案而彼此連接，此電連接該等微電子元件電連接至之各別導電元件1828。
圖7展示圖1中所展示類型之一微電子組合10，其中一再分佈層54沿著密封層42之表面44延伸。如圖7中所展示，跡線58電連接至內部接觸襯墊61，內部接觸襯墊61電連接至導線接合32之端表面38且延伸穿過再分佈層54之基板56至暴露於基板56之表面62上之接觸襯墊60。一額外微電子組合可然後藉由焊料塊或諸如此類連接至接觸襯墊60。類似於再分佈層54之一結構可在稱為一扇出層(fan-out layer)之層中沿著基板12之第二表面16延伸。一扇出層可允許微電子組合10連接至不同於導電元件40陣列原本將准許之一組態的一組態之一陣列。
圖8A至圖8E展示可實施於類似於圖1至圖7之一結構中之導線接合32之端36之結構中或其附近之各種組態。圖8A展示其中一腔64形成於密封層42之一部分中以使得導線接合32之一端36在腔64處之密封層之一小表面43上方突出之一結構。在所展示之實施例中，端表面38定位於密封層42之主表面44下方，且腔64經結構化以在表面44處暴露端表面38以允許一電子結構連接至其。其中端表面38實質上與表面44相平或在表面44上方間隔開之其他實施例亦係可行的。進一步地，腔64可經組態以使得導線接合32之端36附近之其邊緣表面37之一部分可 不被腔64內之密封層42覆蓋。此可允許自端表面38及端36附近之邊緣表面37之未經覆蓋部分兩者進行自組合10之外部至導線接合32之一連接，諸如一焊料連接。此一連接展示於圖8B中且可使用一焊料塊52提供至一第二基板94之一較穩健連接。在一實施例中，腔64可在表面44下面具有約10 μm與50 μm之間的一深度，且可具有約100 μm與300 μm之間的一寬度。圖8B展示具有類似於圖8A之彼結構之一結構但具有錐形側壁65之一腔。進一步地，圖8B展示一第二微電子組合94，其在暴露於其一基板98之一表面處之一接觸襯墊96處藉由一焊料塊52電及機械連接至導線接合32。
腔64可藉由在腔64之所期望區域中移除密封層42之一部分來形成。此可藉由習知製程(包含雷射蝕刻、濕式蝕刻、研光或諸如此類)來完成。另一選擇係，在其中藉由注入模製來形成密封層42之一實施例中，可藉由在模具中包含一對應特徵來形成腔64。此一製程論述於美國專利申請公開案第2010/0232129號中，該美國專利申請公開案以全文引用方式併入本文中。圖8B中所展示之腔64之錐形形狀可係其形成中所使用之一特定蝕刻製程之結果。
圖8C及圖8E展示在導線接合32上包含一實質上圓形端部分70之端結構。圓形端部分70經組態以具有寬於基底34與端36之間的導線接合32之部分之剖面之一剖面。進一步地，圓形端部分70包含一邊緣表面71，該邊緣表面在其與導線接合32之邊緣表面37之間的過渡處自邊緣表面37向外延伸。一圓形邊緣部分70之併入可用於藉由提供一錨固特徵而將導線接合32固定於密封層42內，其中表面71之方向改變賦予密封層42在三個側上包圍端70之一位置。此可幫助防止導線接合32變得自基板12上之導電元件28鬆脫，從而導致一失敗電連接。另外，圓形端部分70可提供在可進行一電子連接之表面44內不被密封層42覆蓋之增加表面面積。如圖8E中所展示，圓形端部分70可在表面44上方延 伸。另一選擇係，如圖8C中所展示，圓形端部分70可進一步接地或以其他方式經平坦化以提供與表面44實質上齊平之一表面，且可具有大於導線接合32之剖面之一面積。
一圓形端部分70可藉由在用於進行導線接合32之導線之端處以一火焰或一火花形式施加局部熱量而形成。習知導線接合機器可經修改以實施此步驟，該步驟可在切割導線之後立即進行。在此製程中，熱量在導線之端處熔融該導線。液態金屬之此局部部分可藉由其表面張力變圓且當金屬冷卻時保持。
圖8D展示微電子組合10之一組態，其中導線接合32之端36包含在密封層42之主表面44上方間隔開之一表面38。特定而言，藉由提供與沿著邊緣表面37之在表面44上方不被密封層42覆蓋之部分芯吸之一焊料塊68之一較穩健連接，此一組態可呈現類似於以上關於腔64所論述之彼益處之若干益處。在一實施例中，端表面38可在表面42上方間隔開約10 μm與50 μm之間的一距離。另外，在圖8D之實施例及其中邊緣表面37之一部分在密封層42之一表面上方不被密封層42覆蓋之其他實施例中之任何實施例中，端可包含形成於其上之一保護層。此一層可包含氧化保護層，包含由金、氧化物塗層或一OSP製作之彼等氧化保護層。
圖9展示具有形成於導線接合32之端表面38上之一柱形凸塊72之微電子組合10之一實施例。柱形凸塊72可在製作微電子組合10之後藉由應用在端表面44之頂部上且視情況沿著表面44之一部分延伸之另一經修改導線接合而形成。在不拉延導線之一長度之情況下，在其基底附近切割或以其他方式切斷該經修改導線接合。含有某些金屬之柱形凸塊72可直接應用於端38而無需首先應用諸如一UBM之一接合層，因此提供形成至不可藉由焊料直接潤濕之接合襯墊之導電互連之方式。在導線接合32由一不可潤濕金屬製成時，此可係有利的。一般而 言，可以此方式應用基本上由銅、鎳、銀、鉑及金中之一或多者組成之柱形凸塊。圖9展示形成於柱形凸塊72上方之一焊料塊68以用於電子或機械連接至一額外微電子組合。
圖10A至圖10D展示包含一彎折或彎曲形狀之導線接合32之端36之組態。在每一實施例中，導線接合32之端36經彎折以使得其一部分74實質上平行於密封層42之表面44延伸，以使得邊緣表面76之至少一部分不被(舉例而言)主表面44覆蓋。邊緣表面37之此部分可在表面44之外部向上延伸，或可經研磨或以其他方式平坦化以便與表面44實質上齊平延伸。圖10A之實施例包含在端36之部分74處之導線接合32中之一突然彎折，該突然彎折平行於表面44且終止於實質上垂直於表面44之一端表面38。圖10B展示一端36，端36與圖10A中所展示相比在平行於表面44之端36之部分74附近具有一較平緩彎曲。其他組態亦係可行的，包含其中根據圖3、圖4或圖5中所展示之彼等導線接合之一導線接合之一部分包含其一部分實質上平行於表面44且使其邊緣表面之一部分不被表面44內之一位置處之密封層42覆蓋之一端之彼等組態。另外，圖10B之實施例包含在其端上之一鉤狀部分75，該鉤狀部分將端表面38定位於密封層42內在表面44下方。此可為端36提供較不可能變得自密封層42內變位之一較穩健結構。圖10C及圖10D展示分別類似於圖10A及圖10B中所展示之彼等結構但藉由形成於密封層42中之腔64在沿著表面44之一位置處不被密封層42覆蓋之結構。此等腔在結構上可類似於以上關於圖8A及圖8B所論述之彼等結構。包含端36(包含平行於表面44延伸之其一部分74)可藉助於細長的不被覆蓋邊緣表面75而為與其之連接提供增加的表面面積。此一部分74之長度可大於用於形成導線接合32之導線之剖面之寬度。
在圖29中展示之另一實例中，多個導線接合1432可結合於一單個導電元件1428上。此一導線接合1432群組可用於在密封層1442上方 製作額外連接點以便與導電元件1428電連接。共同結合之導線接合1432之暴露部分1439可一起編組於密封層1442之表面1444上，在(舉例而言)約為一導電元件1428自身大小之一區域中或近似用於與導線接合1432群組進行一外部連接之一接合塊之預期大小之另一區域中。此等導線接合1432可係導電元件1428上之球接合(如所展示)或邊緣接合(如上文所闡述)。在形成至一基板上之一導電元件之多個導線接合時可採用本文中所闡述用於在導線接合製程期間切斷金屬導線之各種技術(例如，藉由雷射或其他切割器具)。
圖11至圖15展示在一微電子組合10之一製作方法之各種步驟中之該微電子組合。圖11展示在其中微電子元件22已電連接且機械連接至基板12在其第一表面14上且在其第一區18內之一步驟處之微電子組合10'。微電子元件22在圖11中展示為以一覆晶配置安裝於基板12上，諸如透過微電子元件22上之面向且結合至基板之一對立表面14上之對應觸點之觸點。舉例而言，可透過諸如塊26(例如，一導電膏、導電基質材料、焊料塊)之導電材料製作微電子元件之觸點與基板之間的接頭，且該等觸點可係為諸如襯墊、支柱(例如，微柱、柱形凸塊等)以及其他之任何適合組態。本文中使用之「覆晶接合」意指諸如一微電子元件與一基板之對應觸點之間或一微電子元件與另一微電子元件之間的面對面電接合之配置。
另一選擇係，諸如圖1之實例中所見，可替代地使用微電子元件之觸點至基板之面向上導線接合。在圖11中所展示之方法步驟之實施例中，一介電底填充層66可提供於微電子元件22與基板12之間。
圖12展示具有應用於導電元件28之襯墊30上之導線接合32之微電子組合10"，該等襯墊暴露於基板12之第一表面14上。如所論述，可藉由以下方式來應用導線接合32：加熱一導線段之一端以軟化該端，從而使得當按壓至導電元件28時其形成至導電元件28之一沈積接 合，從而形成基底34。然後背離導電元件28拉延該導線且在切割或以其他方式切斷之前操縱(若期望)成一特定形狀以形成導線接合32之端36及端表面38。另一選擇係，可藉由楔接合由(舉例而言)一鋁導線形成導線接合32。楔接合係藉由加熱毗鄰導線端之導線之一部分且藉助施加至其之壓力沿著導電元件28拖曳其而形成。此一製程進一步闡述於美國專利第7,391,121號中，該美國專利之揭示內容以全文引用方式併入本文中。
在圖13中，已藉由以下步驟將密封層42添加至微電子組合10'''：將其應用於基板之第一表面14上方，自該第一表面向上且沿著導線接合32之邊緣表面37延伸。密封層42亦覆蓋底填充層66。密封層42可藉由在圖12中所展示之微電子組合10"上沈積一樹脂而形成。此可藉由將組合10"放置於具有可接納組合10'之呈所期望形狀之密封層42之一腔之一經適當組態之模具中而完成。此一模具及藉助其形成一密封層之方法可如美國專利申請公開案第2010/0232129號中所展示及闡述，該美國專利申請公開案之揭示內容以全文引用方式併入本文中。另一選擇係，密封層42可係由一至少部分順應性材料預製作成所期望形狀。在此組態中，介電材料之順應性質允許將密封層42按壓至導線接合32及微電子元件22上之位置中。在此一步驟中，導線接合32穿透至該順應材料中從而在其中形成各別孔，密封層42沿著該等孔接觸邊緣表面37。進一步地，微電子元件22可使順應材料變形以使得微電子元件22可被接納於其中。順應介電材料可經壓縮以在外表面44上暴露端表面38。另一選擇係，可自密封層移除任何過量的順應介電材料以形成導線接合32之端表面38在其上不被覆蓋或可形成在表面63內之一位置處顯露端表面38之腔64之一表面44。
在圖13中所展示之實施例中，密封層經形成以使得最初其表面44在導線接合32之端表面38上方間隔開。為暴露端表面38，可移除在 端表面38上方之密封層42之部分，從而暴露與端表面42實質上齊平之一新表面44'，如圖14中所展示。另一選擇係，可形成其中端表面38不被密封層42覆蓋之腔64，諸如圖8A及圖8B中所展示之彼等。在另一替代方案中，密封層42可經形成以使得表面44已與端表面48實質上齊平，或使得表面44定位於端表面48下方，如圖8D中所展示。密封層42之一部分之移除(視需要)可藉由研磨、乾式蝕刻、雷射蝕刻、濕式蝕刻、研光或諸如此類達成。若期望，亦可在相同或一額外步驟中移除導線接合32之端36之一部分以達成與表面44實質上齊平之實質上平面端表面38。若期望，亦可在此一步驟之後形成腔64，或亦可應用柱形凸塊(如圖10中所展示)。所得微電子組合10然後可貼附於一PCB上，或以其他方式併入另一組合(舉例而言，如圖6中所展示之一堆疊式封裝)中。
在圖15中所展示之一替代實施例中，導線接合32最初成對地形成為一導線環路86之部分32'。在此實施例中，環路86係以一導線接合之形式製作，如以上所論述。該導線段經向上拉延、然後沿使其至少一分量沿基板13之第一表面14之方向之一方向彎折及拉延且至實質上上覆於一毗鄰導電元件28上之一位置。然後在切割或以其他方式切斷該導線之前將其實質上向下拉延至毗鄰導電元件28附近之一位置。然後加熱該導線且藉由沈積接合或諸如此類將其連接至毗鄰導電元件28以形成環路86。然後形成密封層42以便實質上覆蓋環路86。然後藉由研磨、蝕刻或諸如此類藉由亦移除環路86之一部分以使得將該環路切斷且劃分成其兩部分32'之一製程來移除密封層42之一部分，藉此形成具有在沿著形成於密封層42上之表面44之一位置處不被密封層42覆蓋之端表面38之導線接合32。然後可將後續修整步驟應用於組合10，如上文所論述。
圖16A至圖16C展示在用於製作包圍導線接合32之端36之腔64(如 以上所論述)之一替代實施例中之步驟。圖16A展示以上關於圖1至圖6所論述之一般類型之一導線接合32。導線接合32具有應用於其端36上之一犧牲材料塊78。犧牲材料塊78之形狀可係實質上球形(此可由其形成期間之材料表面張力所致)，或係熟習此項技術者將瞭解之其他所期望形狀。可藉由將導線接合32之端36浸漬於焊料膏中以塗佈其該等端而形成犧牲材料塊78。在浸漬之前可調整焊料膏之黏度以控制芯吸及表面張力致使黏附至端36之焊料塊之量。相應地，此可影響施加於端36上之塊78之大小。另一選擇係，可藉由將一可熔材料沈積至導線接合32之端36上而形成塊78。其他可行塊78可係端上之個別焊料球或其他塊，或藉由其他手段使用在微電子組件製作中所使用之稍後可移除之其他材料，諸如銅或金閃鍍(flashing)。
在圖16B中，展示已添加至組合10之一介電層42，包含沿著導線接合32之邊緣表面37向上。該介電層亦沿著犧牲材料塊78之表面之一部分延伸，以使得其藉此與導線接合32之端36間隔開。隨後，移除犧牲材料塊78，諸如藉由在一溶劑中清洗或沖洗、熔融、化學蝕刻或其他技術，從而在移除塊78之前在介電層42中留下實質上呈塊78之負形之腔64，且暴露導線接合32之端36附近之邊緣表面37之一部分。
另一選擇係，犧牲材料塊78可經形成以藉由沿著導線接合32之邊緣表面37延伸而實質上塗佈所有導線接合32。在圖17A中展示此配置。此一塗佈可在形成於組合10上之後施加於導線接合32上方(如以上所論述)，或可作為一塗層施加至用於製作導線接合32之導線。此將基本上呈一經塗佈導線或一兩部分導線之形式，舉例而言，具有一銅內核及一焊料塗層。圖17B展示施加於導線接合32及犧牲塊78上方以便沿著犧牲塊78之邊緣表面79延伸之介電層42，藉此實質上沿著導線接合32之長度將介電層42與導線接合32間隔開。
圖17C展示由移除犧牲材料塊78之一部分以形成繞端36且暴露邊 緣表面37之一部分之腔64所致之結構。在此一實施例中，大多數犧牲材料塊78或其至少一部分可留在介電層42與導線接合32之間的適當位置中。圖17C進一步展示將導線接合32電連接且機械連接至另一微電子結構10A之一接觸襯墊40A之一焊料塊52。
在形成導線段及其至一導電元件之接合以形成一導線接合(特定而言為上文所論述之球接合類型)之後，隨之分離該導線接合(舉例而言，在圖1中為32)與毛細管(諸如圖32中之804)內之導線之一剩餘部分。此可在遠離導線接合32之基底34之任一位置處完成，且較佳地在遠離基底34達至少足以定義導線接合32之所期望高度之一距離之一位置處完成。此分離可由面806與導線接合32之基底34之間的安置於毛細管804內或安置於毛細管804外部之一機構實現。在一項方法中，可藉由在所期望分離點處有效地燒斷導線800來分離導線段800，此可藉由將一火花或火焰施加至其而達成。為達成導線接合高度之較大準確度，可實施不同形式之切割導線段800。如本文中所闡述，切割可用於闡述在一所期望位置處弱化導線之一部分切割，或用於導線接合32與剩餘導線段800之完全分離之完全切斷導線。
在圖32中所展示之一項實例中，可將一切割刀片805整合至接合頭組合中，諸如在毛細管804內。如所展示，一開口807可包含於切割刀片805可藉以延伸之毛細管804之側壁820中。切割刀片805可移動進出毛細管804之內部，以使得其可交替地允許導線800自由通過其或嚙合導線800。相應地，導線800可經拉延且導線接合32經形成及接合至一導電元件28，其中切割刀片805在毛細管內部之外的一位置中。在接合形成之後，可使用整合於接合頭組合中之一夾具803來夾緊導線段800以固定導線之位置。然後可將切割刀片803移動至導線段中以完全切割該導線或者部分切割或弱化該導線。一完全切割可形成導線接合32之端表面38，在此點處可自導線接合32移開毛細管804以(舉例 而言)形成另一導線接合。類似地，若導線段800藉由切割刀片805而弱化，則接合頭之移動(其中導線仍由導線夾具803固持)可藉由在藉由部分切割而弱化之區域處使導線800斷裂來致使分離。
切割刀片805之移動可藉由氣壓或藉由使用一偏置凸輪之一伺服馬達來致動。在其他實例中，可藉由一彈簧或一膜片來致動切割刀片805之移動。用於切割刀片805之致動之觸發信號可係基於自球接合之形成起倒數之一時間延遲，或可藉由毛細管804移動至導線接合基底34上方之一預定高度來致動。此一信號可連結至操作該接合機器之其他軟體，以使得可在任一後續接合形成之前重設切割刀片805位置。該切割機構亦可包含與刀片805對置地間隔開之一第二刀片(未展示)，以自其相反側切割該導線。
在另一實例中，一雷射809可裝配有接合頭單元且經定位以切割該導線段。如圖33中所展示，一雷射頭809可(諸如)藉由安裝至其或安裝至包含毛細管804之接合頭單元上之另一點而定位於毛細管804外部。該雷射可係在一所期望時間處致動，諸如上文關於圖32中之切割刀片805所論述之彼等方案，以切割導線800，從而在基底34上方之一所期望高度處形成導線接合32之端表面38。在其他實施方案中，雷射809可經定位以指引切割光束穿過或進入至毛細管804本身中且可在接合頭單元內部。在一實例中，可使用二氧化碳雷射，或作為一替代，可使用一Nd：YAG或一Cu蒸氣雷射。
在另一實施例中，如圖34A至圖34C中所展示之一模板824可用於分離導線接合32與剩餘的導線段800。如圖34A中所展示，模板824可係具有界定在導線接合32之所期望高度處或其附近之一上部表面826之一主體的一結構。模板824可經組態以接觸導電元件28或導電元件28之間的基板12之任何部分。該模板包含複數個孔828，該複數個孔可對應於導線接合32之所期望位置，諸如在導電元件28上方。孔828 可經定大小以將接合頭單元之毛細管804接受於其中，以使得毛細管可延伸至孔中到達相對於導電元件28之一位置，以將導線800接合至導電元件28以形成基底34，諸如藉由球接合或諸如此類。然後可將毛細管804垂直移動出孔828，同時將該導線段拉延至一所期望長度。一旦自孔828移出，該導線段即可(諸如)藉由夾具803夾緊於接合頭單元內，且毛細管804可沿一橫向方向(諸如平行於模板824之表面826)移動以將導線段800移動至與孔828之表面與模板824之外部表面826之交叉所界定之模板824之一邊緣829接觸。此移動可致使導線接合32與仍固持於毛細管804內之導線段800之一剩餘部分分離。此製程可經重複以在所期望位置中形成所期望數目個導線接合32。在一實施方案中，毛細管可在導線分離之前垂直移動以使得剩餘的導線段超過毛細管804之面806突出達足以形成一後續球接合之一距離802。圖34B展示模板824之一變化形式，其中孔828係錐形以使得其具有自表面826處之一第一直徑增加至背離表面826之一較大直徑的一直徑。在另一變化形式中，如圖34C中所展示，該模板可經形成為具有一外部框架821，該外部框架具有足以在距基板12之所期望距離處間隔開表面826。框架821可至少部分地圍繞經組態以毗鄰基板12定位之一腔823，其中模板824之一厚度在表面826與開放區域823之間延伸以使得當模板824定位於基板12上時包含孔828之模板824之部分與基板12間隔開。
圖20及圖21展示其中在一引線框架結構上形成導線接合532之一微電子組合510之另一實施例。引線框架結構之實例展示且闡述於美國專利第7,176,506號及第6,765,287號中，該等美國專利之揭示內容以引用方式併入本文中。一般而言，一引線框架係由一導電金屬(諸如銅)片形成之一結構，其經圖案化成包含複數個引線之段且可進一步包含一銲盤及一框架。該框架用於在組合之製作期間固定引線及銲 盤(若使用)。在一實施例中，一微電子元件(諸如一晶粒或晶片)可面向上結合至該銲盤且使用導線接合電連接至該等引線。另一選擇係，該微電子元件可直接安裝至該等引線上，該等引線可在該微電子元件下方延伸。在此一實施例中，微電子元件上之觸點可藉由焊料球或諸如此類電連接至各別引線。然後該等引線可用於形成至各種其他導電結構之電連接，以用於攜載一電子信號電位往返於該微電子元件。當該結構之裝配完成(此可包含在其上方形成一密封層)時，可自引線及引線框架之銲盤移除框架之臨時元件，以便形成個別引線。出於此揭示內容之目的，將個別引線513及銲盤515視為共同形成一基板512之分段部分，基板512在與其整體形成之部分中包含導電元件528。進一步地，在此實施例中，將銲盤515視為在基板512之第一區518內，且將引線513視為在第二區520內。導線接合524(其亦展示於圖21之立面圖中)將承載於銲盤515上之微電子元件22連接至引線515之導電元件528。導線接合532可進一步在其基底534處結合至引線515上之額外導電元件528。密封層542形成至組合510上，從而使導線接合532之端538在表面544內之位置處不被覆蓋。導線接合532可使其額外或替代部分在對應於關於本文中其他實施例所闡述之彼等結構之結構中不被密封層542覆蓋。
圖24至圖26展示具有閉合環路導線接合832之一微電子封裝810之另一替代實施例。此實施例之導線接合832包含可結合至毗鄰導電元件828a及828b之兩個基底834a及834b，如圖24中所展示。另一選擇係，基底834a、834b兩者皆可結合於一共同導電元件828上，如圖25及圖26中所展示。在此一實施例中，導線接合832界定在一環路中之兩個基底834a、834b之間延伸之一邊緣表面837，以使得邊緣表面837自該等基底在各別部分837a及837b中向上延伸至基板812上方之密封層842之一表面844處之一頂端839。密封層842沿著邊緣表面部分 837a、837b之至少某些邊緣表面部分延伸，從而使各別部分彼此分離，以及與封裝810中之其他導線接合832分離。在頂端839處，邊緣表面837之至少一部分不被密封層842覆蓋，以使得導線接合832可用於與另一組件(其可係另一微電子組件或其他組件，例如一離散元件，諸如一電容器或電感器)電互連。如圖24至圖26中所展示，導線接合832經形成以使得頂端839跨越基板812之表面沿至少一個橫向方向自導電元件828偏移。在一項實例中，頂端839可上覆於微電子元件820之一主表面上，或以其他方式上覆於微電子元件820與其對準之基板812之一第一區上。導線接合832之其他組態亦係可行的，包含其中頂端839定位於其他實施例中所論述之導線接合之端表面位置中之任何位置中之組態。進一步地，頂端839可在一孔中不被覆蓋，諸如圖8A中所展示。更進一步地，頂端839可係細長的且可在於其一長度上方延伸之表面844上不被覆蓋，如關於圖10A至圖10D中之邊緣表面所展示。藉由以包圍頂端839之未經覆蓋之邊緣表面837之形式提供一連接特徵(其係由在兩個基底834a、834b之間(而非一個)延伸的一導線接合832支援)，可達成沿主表面844所界定之方向之連接特徵之較準確放置。
圖27及圖28展示圖24至圖26中之實施例之一變化形式，其中使用接合帶934替代導線接合834。接合帶可係導電材料(諸如先前針對導線接合之形成所論述之材料中之任何者)之一大體扁平件。與一導線接合(其剖面可係大體圓形)相比，一接合帶結構之寬度可大於其厚度。如圖27中所展示，接合帶934各自包含一第一基底934a，該第一基底可經接合為沿著導電元件928之一部分延伸。帶接合932之一第二基底934b可結合至第一基底934a之一部分。邊緣表面937在基底934a與934b之間在兩個對應部分937a及937b中延伸至頂端939。在頂端939之區域中之邊緣表面之一部分沿著密封942之主表面944之一部分不被 密封942覆蓋。進一步變化形式亦係可行的，諸如關於本文中所揭示之其他實施例中所使用之導線接合所闡述之彼等變化形式。
以上所論述之結構可用於不同電子系統之構造。舉例而言，根據本發明之另一實施例之一系統711包含微電子組合710(如以上所闡述)以及其他電子組件713及715。在所繪示之實例中，組件713係一半導體晶片而組件715係一顯示螢幕，但亦可使用任何其他組件。當然，儘管為清晰圖解說明起見而在圖23中僅繪示兩個額外組件，但系統可包含任何數目個此等組件。如以上所闡述之微電子組合710可係(舉例而言)以上結合圖1所論述之一微電子組合，或如參考圖6所論述之併入有複數個微電子組合之一結構。組合710可進一步包含圖2至圖22中所論述之實施例中之任一者。在另一變化形式中，可提供多個變化形式，且可使用任何數目個此等結構。
微電子組合710以及組件713及715安裝於一共同殼體719(以虛線示意性繪示)中，且視需要彼此電互連以形成所期望電路。在所展示之例示性系統中，系統包含一電路面板717，諸如一撓性印刷電路板，且該電路面板包含使組件彼此互連之眾多導體721(圖23中僅繪示其中一者)。然而，此僅係例示性的；可使用適於進行電連接之任何結構。
殼體719經繪示為(舉例而言)可用於一蜂巢式電話或個人數位助理中之類型之一可攜式殼體，且螢幕715暴露於該殼體之表面處。在微電子組合710包含一光敏元件(諸如一成像晶片)之情況下，一透鏡723或其他光學裝置亦可提供用於將光路由至該結構。同樣，圖23中所展示之簡化系統僅係例示性的；可使用以上所論述之結構製作其他系統(包含通常視為固定結構之系統)，諸如桌上型電腦、路由器及諸如此類。
本發明之上述實施例及變化形式可以不同於以上具體闡述之方 式的方式來組合。其意欲覆蓋在本發明之範疇及精神內之所有此等變化形式。
儘管本文中已參考特定實施例闡述本發明，但應理解，此等實施例僅圖解說明本發明之原理及應用。因此，應理解，可在不背離如由隨附申請專利範圍所界定之本發明之精神及範疇之情況下對說明性實施例進行眾多修改並可設想出其他配置。
12‧‧‧基板
28‧‧‧導電元件
32‧‧‧導線接合
34‧‧‧基底
38‧‧‧端表面/端
800‧‧‧導線/導線段
803‧‧‧夾具/切割刀片/導線夾具
804‧‧‧毛細管
805‧‧‧切割刀片/刀片
807‧‧‧開口

Claims (30)

  1. 一種製作一微電子封裝之方法，其包括：a)自一接合工具之一毛細管饋出具有一預定長度之一金屬導線段；b)使用該接合工具將該金屬導線之一部分接合至暴露於一基板之一第一表面處之一導電元件，藉此在該導電元件上形成一導線接合之一基底；c)將該導線之一部分夾緊於該接合工具內；d)在該經夾緊部分與該基底部分之間的一位置處切割該金屬導線以至少部分地界定該導線接合之一端表面，該導線接合之一邊緣表面係界定於該基底與該端表面之間；e)重複步驟(a)至(d)以形成至該基板之複數個該等導電元件之複數個導線接合；及f)然後形成上覆於該基板之該表面上之一介電密封層，其中該密封層經形成以便至少部分地覆蓋該基板之該表面及該等導線接合之部分，以使得該等導線接合之未經密封部分由不被該密封層覆蓋的該等導線接合之一端表面或一邊緣表面中之至少一者之一部分界定g)將一模板定位於該基板上方，該模板在其中具有上覆於且暴露該等導電元件之至少部分之複數個開口，該等開口界定定位於該基板上方之一第一高度處之各別邊緣，且其中藉由該導線抵靠該模板開口之該邊緣之橫向移動來切割該導線段。
  2. 如請求項1之方法，其中至少一個微電子元件上覆於該基板之該第一表面上，其中該基板具有一第一區及一第二區，該微電子元件位於該第一區內，該等導電元件位於該第二區內且電連接 至該至少一個微電子元件，且其中該介電密封層經形成為在至少該基板之該第二區中上覆於該基板之該第一表面上。
  3. 如請求項2之方法，其中該封裝經組態以使得該等導線接合中之一第一導線接合經調適用於攜載一第一信號電位，且該等導線接合中之一第二導線接合經調適用於同時攜載不同於該第一信號電位之一第二信號電位。
  4. 一種製作一微電子封裝之方法，其包括：a)將一模板定位於一製程中單元上方，該製程中單元包含具有一第一表面及遠離該第一表面之一第二表面之一基板，一微電子元件安裝至該基板之該第一表面，複數個導電元件暴露於該第一表面處，該等導電元件中之至少某些導電元件電連接至該微電子元件，該模板在其中具有上覆於且暴露該等導電元件之至少部分之複數個開口，該等開口界定定位於該基板上方之一第一高度處之各別邊緣；b)藉由包含以下步驟之一製程形成一導線接合：自一接合工具之一毛細管饋出具有一預定長度之一金屬導線段；將該導線段之一部分結合至該等導電元件中之一者以形成該導線接合之一基底；及藉由該導線抵靠該模板開口之該邊緣之橫向移動來剪切該導線段，以分離該導線接合與該導線段之一剩餘部分且在該導線接合上界定一端表面，該導線接合界定在該基底與該端表面之間延伸之一邊緣表面；及c)重複步驟(b)以在複數個該等導電元件上形成複數個導線接合。
  5. 如請求項4之方法，其進一步包含在該製程中單元上形成一介電密封層，其中該密封層經形成以便至少部分地覆蓋該第一表面及該等導線接合之部分，以使得該等導線接合之未經密封部分 由不被該密封層覆蓋的該等導線接合之該端表面或該邊緣表面中之至少一者之一部分界定。
  6. 如請求項4之方法，其中延伸超過該毛細管之一面之該導線段之該剩餘部分係為足以形成一後續導線接合之至少一基底之一長度。
  7. 如請求項4之方法，其中該模板界定沿諸孔中之一者之一軸之一方向之一厚度，且其中該等孔中之至少某些孔貫穿該模板之該厚度係為一致直徑。
  8. 如請求項4之方法，其中該模板界定沿該等孔中之一者之一軸之一方向之一厚度，且其中該等孔中之至少某些孔自該邊緣附近之一較小直徑漸變至該邊緣與該基板之間的一位置處之一較大直徑。
  9. 如請求項4之方法，其中該模板包含沿著該基板之一或多個邊緣延伸之具有沿該基板之一厚度方向之一第一厚度之一邊緣部件，該第一厚度界定該第一高度且一中心部分包含該等孔且由該邊緣部件定界，該中心部分具有背對該基板之一外部表面，該外部表面安置於該第一高度處，該中心部分進一步具有小於該第一厚度之一厚度。
  10. 一種製作一微電子封裝之方法，其包括：a)饋送一金屬導線穿過一接合工具之一毛細管；b)使用該接合工具將該金屬導線之一部分接合至暴露於一基板之一第一表面處之一導電元件，藉此在該導電元件上形成一導線接合之一基底；c)將該導線之一部分夾緊於該接合工具內；及d)在該毛細管內在該經夾緊部分與該基底之間的一位置處切割該金屬導線以在距該導線接合之該基底之一預定距離處至少部 分地界定該導線接合之一端表面，e)重複步驟(a)至(d)以形成至該基板之複數個該等導電元件之複數個導線接合；及f)然後形成上覆於該基板之該第一表面上之一介電密封層，其中該密封層經形成以便至少部分地覆蓋該基板之該第一表面及該等導線接合之部分，以使得該等導線接合之未經密封部分由不被該密封層覆蓋的該等導線接合之該端表面或在該基底與該端表面之間延伸的一邊緣表面中之至少一者之一部分界定，其中一腔形成於該介電密封層之一主要表面的下方，使得該等導線接合之至少一個的該端表面突出超過該介電密封層之一次要表面，並且該等導線接合之該至少一個的該端表面被置於該密封層的該主要表面的下方於該腔之中。
  11. 如請求項10之方法，其中僅部分地切斷該金屬導線，且其中自該基板之該第一表面移開該接合工具同時該導線之該部分保持經夾緊以致使該導線在該切割之位置處斷裂，藉由該切割及該斷裂形成該端表面。
  12. 如請求項10之方法，其中沿實質上垂直於該導線接合之一邊緣表面之一方向完全穿過該金屬導線進行該切割，該邊緣表面在該基底與該端表面之間延伸，藉由該切割形成該導線接合之該端表面。
  13. 如請求項10之方法，其中至少一個微電子元件上覆於該基板之該第一表面上，其中該基板具有一第一區及一第二區，該微電子元件位於該第一區內，該等導電元件位於該第二區內且電連接至該至少一個微電子元件，且其中該介電密封層經形成為在至少該基板之該第二區中上覆於該基板之該第一表面上。
  14. 如請求項13之方法，其中該封裝經組態以使得該等導線接合中 之一第一導線接合經調適用於攜載一第一信號電位，且該等導線接合中之一第二導線接合經調適用於同時攜載不同於該第一信號電位之一第二信號電位。
  15. 如請求項10之方法，其中使用安裝於該接合工具上之一雷射來切割該金屬導線。
  16. 如請求項10之方法，其中使用在該毛細管內延伸之一切割刃來切割該金屬導線。
  17. 如請求項16之方法，其中該切割刃沿朝向該毛細管之一壁之一方向延伸。
  18. 如請求項10之方法，其中該毛細管界定其藉以饋送該導線之一面，其中使用具有相對的第一切割刃及第二切割刃之一切割器具來切割該金屬導線，且其中該切割器具安裝於該接合工具上以在該毛細管內切割該導線。
  19. 如請求項10之方法，其中該等導線接合之至少一個的該端表面包含一部份，該部份平行延伸至該介電密封層之該主要表面，該等導線接合之該至少一個的該端表面被放置在該介電密封層之該主要表面的下方於該腔之中。
  20. 一種製作一微電子封裝之方法，其包括：a)提供與一製程中單元之一基板相關聯之一結構之一表面，該基板具有一第一表面及遠離該第一表面之一第二表面，複數個導電元件暴露於該第一表面處，該結構在其中具有上覆於且暴露該等導電元件之至少部分之複數個開口；及b)藉由包含以下步驟之一製程形成一導線接合：饋送一金屬導線穿過一接合工具之一毛細管；將該導線之一部分結合至該等導電元件中之一者以形成該導線接合之一基底；使該接合工具相對於該導線接合之該基底移動以針對該導線接合提供一預定 長度之該導線；及透過該接合工具相對於該結構之該表面之移動來分離該導線接合與該導線之一剩餘部分以界定遠離該導線接合之該基底之該導線接合之一自由端。
  21. 如請求項20之方法，其中該結構係一可移除模板。
  22. 如請求項20之方法，其中該結構定位於該基板之該第一表面上方。
  23. 如請求項20之方法，其中該結構之該表面包含在該等開口中之至少一者處之一邊緣，且其中藉由該導線抵靠該邊緣之移動直至該導線接合與該導線分離來剪切該導線。
  24. 如請求項20之方法，其中將一微電子元件安裝至該基板之該第一表面，且將該等導電元件中之至少某些導電元件電連接至該微電子元件。
  25. 如請求項20之方法，其進一步包括：c)重複步驟(b)以在複數個該等導電元件上形成複數個導線接合。
  26. 如請求項25之方法，其進一步包含在該製程中單元上形成一介電密封層，其中該密封層經形成以便至少部分地覆蓋該第一表面及該等導線接合之部分，以使得該等導線接合之未經密封部分由不被該密封層覆蓋的該等導線接合之該自由端之一端表面或在該基底與該端表面之間延伸的一邊緣表面中之至少一者之一部分界定。
  27. 如請求項20之方法，其中延伸超過該毛細管之一面之該導線之該剩餘部分係為足以形成一後續導線接合之至少一基底之一長度。
  28. 如請求項20之方法，其中該結構界定沿該等開口中之一者之一軸之一方向之一厚度，且其中該等開口中之至少某些開口貫穿 該結構之該厚度係為一致直徑。
  29. 如請求項20之方法，其中該結構界定沿該等開口中之一者之一軸之一方向之一厚度，且其中該等開口中之至少某些開口自定位於該基板上方之一第一高度處之該結構之該表面之一邊緣附近之一較小直徑漸變至該邊緣與該基板之間的一位置處之一較大直徑。
  30. 如請求項20之方法，其中該結構包含沿著該基板之一或多個邊緣延伸之具有沿該基板之一厚度方向之一第一厚度之一邊緣部件，該第一厚度界定該結構之該表面之一邊緣定位於該基板上方之一第一高度，且一中心部分包含該等開口且由該邊緣部件定界，該中心部分具有背對該基板之一外部表面，該外部表面安置於該第一高度處，該中心部分進一步具有小於該第一厚度之一厚度。
TW102106326A 2012-02-24 2013-02-22 用於藉由至密封表面之導線接合之疊合封裝組合之方法 TWI553754B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/405,125 US8372741B1 (en) 2012-02-24 2012-02-24 Method for package-on-package assembly with wire bonds to encapsulation surface
US13/752,485 US8772152B2 (en) 2012-02-24 2013-01-29 Method for package-on-package assembly with wire bonds to encapsulation surface

Publications (2)

Publication Number Publication Date
TW201347059A TW201347059A (zh) 2013-11-16
TWI553754B true TWI553754B (zh) 2016-10-11

Family

ID=47631935

Family Applications (2)

Application Number Title Priority Date Filing Date
TW102106326A TWI553754B (zh) 2012-02-24 2013-02-22 用於藉由至密封表面之導線接合之疊合封裝組合之方法
TW105127427A TWI596682B (zh) 2012-02-24 2013-02-22 用於藉由至密封表面之導線接合之疊合封裝組合之方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW105127427A TWI596682B (zh) 2012-02-24 2013-02-22 用於藉由至密封表面之導線接合之疊合封裝組合之方法

Country Status (7)

Country Link
US (3) US8372741B1 (zh)
EP (1) EP2817823B1 (zh)
JP (2) JP6025875B2 (zh)
KR (2) KR101571457B1 (zh)
CN (1) CN104170083B (zh)
TW (2) TWI553754B (zh)
WO (1) WO2013126269A1 (zh)

Families Citing this family (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101313391B1 (ko) 2004-11-03 2013-10-01 테세라, 인코포레이티드 적층형 패키징
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
JP5081578B2 (ja) * 2007-10-25 2012-11-28 ローム株式会社 樹脂封止型半導体装置
JP5688289B2 (ja) 2008-05-09 2015-03-25 インヴェンサス・コーポレイション チップサイズ両面接続パッケージの製造方法
US9941195B2 (en) 2009-11-10 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical metal insulator metal capacitor
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9721872B1 (en) * 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8642393B1 (en) * 2012-08-08 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of forming same
JP5972735B2 (ja) 2012-09-21 2016-08-17 株式会社東芝 半導体装置
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US8970023B2 (en) * 2013-02-04 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming same
US8884427B2 (en) * 2013-03-14 2014-11-11 Invensas Corporation Low CTE interposer without TSV structure
US9016552B2 (en) * 2013-03-15 2015-04-28 Sanmina Corporation Method for forming interposers and stacked memory devices
US9446943B2 (en) 2013-05-31 2016-09-20 Stmicroelectronics S.R.L. Wafer-level packaging of integrated devices, and manufacturing method thereof
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) * 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
TWI587412B (zh) * 2014-05-08 2017-06-11 矽品精密工業股份有限公司 封裝結構及其製法
US10381326B2 (en) * 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9899794B2 (en) * 2014-06-30 2018-02-20 Texas Instruments Incorporated Optoelectronic package
US9449908B2 (en) 2014-07-30 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package system and method
US10319607B2 (en) * 2014-08-22 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with organic interposer
US9368470B2 (en) * 2014-10-31 2016-06-14 Freescale Semiconductor, Inc. Coated bonding wire and methods for bonding using same
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9802813B2 (en) 2014-12-24 2017-10-31 Stmicroelectronics (Malta) Ltd Wafer level package for a MEMS sensor device and corresponding manufacturing process
KR20160093248A (ko) * 2015-01-29 2016-08-08 에스케이하이닉스 주식회사 반도체 패키지 및 제조 방법
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9530749B2 (en) 2015-04-28 2016-12-27 Invensas Corporation Coupling of side surface contacts to a circuit platform
US9502372B1 (en) * 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
JP6392171B2 (ja) * 2015-05-28 2018-09-19 新光電気工業株式会社 半導体装置及びその製造方法
US9779940B2 (en) * 2015-07-01 2017-10-03 Zhuahai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Chip package
TWI620296B (zh) * 2015-08-14 2018-04-01 矽品精密工業股份有限公司 電子封裝件及其製法
US9806052B2 (en) * 2015-09-15 2017-10-31 Qualcomm Incorporated Semiconductor package interconnect
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
ITUB20155408A1 (it) * 2015-11-10 2017-05-10 St Microelectronics Srl Substrato di packaging per dispositivi a semiconduttore, dispositivo e procedimento corrispondenti
PL3168874T3 (pl) 2015-11-11 2021-07-12 Lipac Co., Ltd. Obudowa chipów półprzewodnikowych z interfejsem optycznym
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9831155B2 (en) * 2016-03-11 2017-11-28 Nanya Technology Corporation Chip package having tilted through silicon via
TWI567897B (zh) * 2016-06-02 2017-01-21 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造與製造方法
TWI602269B (zh) * 2016-06-08 2017-10-11 力成科技股份有限公司 柱頂互連之封裝堆疊方法與構造
JP6712050B2 (ja) * 2016-06-21 2020-06-17 富士通株式会社 樹脂基板及びその製造方法、並びに回路基板及びその製造方法
US9930773B2 (en) * 2016-06-21 2018-03-27 Microsoft Technology Licensing, Llc Flexible interconnect
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US20180114786A1 (en) * 2016-10-21 2018-04-26 Powertech Technology Inc. Method of forming package-on-package structure
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
TWI637536B (zh) * 2017-02-24 2018-10-01 矽品精密工業股份有限公司 電子封裝結構及其製法
US10522505B2 (en) * 2017-04-06 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
US10181447B2 (en) * 2017-04-21 2019-01-15 Invensas Corporation 3D-interconnect
US10426030B2 (en) * 2017-04-21 2019-09-24 International Business Machines Corporation Trace/via hybrid structure multichip carrier
CN108807430A (zh) * 2017-04-28 2018-11-13 南昌欧菲光电技术有限公司 摄像模组及其复合式感光组件
US10707635B2 (en) * 2017-05-15 2020-07-07 Current Lighting Solutions, Llc Method for providing a wire connection to a printed circuit board
DE102017114771B4 (de) * 2017-06-29 2022-01-27 Pac Tech - Packaging Technologies Gmbh Verfahren und Vorrichtung zur Herstellung einer Drahtverbindung sowie Bauelementanordnung mit Drahtverbindung
US20190035715A1 (en) * 2017-07-31 2019-01-31 Innolux Corporation Package device and manufacturing method thereof
US10312198B2 (en) * 2017-10-20 2019-06-04 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US10529693B2 (en) * 2017-11-29 2020-01-07 Advanced Micro Devices, Inc. 3D stacked dies with disparate interconnect footprints
US10566279B2 (en) 2018-01-25 2020-02-18 Advanced Semiconductor Engineering, Inc. Package device, semiconductor device, and method for manufacturing the package device
US10727204B2 (en) 2018-05-29 2020-07-28 Advances Micro Devices, Inc. Die stacking for multi-tier 3D integration
US10937755B2 (en) 2018-06-29 2021-03-02 Advanced Micro Devices, Inc. Bond pads for low temperature hybrid bonding
US11139283B2 (en) * 2018-12-22 2021-10-05 Xcelsis Corporation Abstracted NAND logic in stacks
KR20230024413A (ko) 2020-07-29 2023-02-20 교세라 가부시키가이샤 회로 기판 및 프로브 카드
JP2022033633A (ja) 2020-08-17 2022-03-02 キオクシア株式会社 半導体装置
US12040284B2 (en) 2021-11-12 2024-07-16 Invensas Llc 3D-interconnect with electromagnetic interference (“EMI”) shield and/or antenna
WO2023100517A1 (ja) * 2021-12-01 2023-06-08 株式会社村田製作所 回路モジュール
TWI777872B (zh) 2021-12-14 2022-09-11 頎邦科技股份有限公司 半導體封裝構造及其製造方法
CN115132687B (zh) * 2022-09-02 2022-11-22 甬矽电子(宁波)股份有限公司 封装堆叠结构和封装堆叠方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095187A (en) * 1989-12-20 1992-03-10 Raychem Corporation Weakening wire supplied through a wire bonder
JPH10135220A (ja) * 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
JPH11251350A (ja) * 1998-02-27 1999-09-17 Fuji Xerox Co Ltd バンプ形成方法および装置
US20010002607A1 (en) * 1999-12-02 2001-06-07 Kazuo Sugiura Method for forming pin-form wires and the like
US20010045012A1 (en) * 1992-10-19 2001-11-29 Beaman Brian Samuel Angled flying lead wire bonding process
US6476503B1 (en) * 1999-08-12 2002-11-05 Fujitsu Limited Semiconductor device having columnar electrode and method of manufacturing same
US7750483B1 (en) * 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal

Family Cites Families (543)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1439262B2 (de) * 1963-07-23 1972-03-30 Siemens AG, 1000 Berlin u. 8000 München Verfahren zum kontaktieren von halbleiterbauelementen durch thermokompression
US3358897A (en) * 1964-03-31 1967-12-19 Tempress Res Co Electric lead wire bonding tools
US3430835A (en) 1966-06-07 1969-03-04 Westinghouse Electric Corp Wire bonding apparatus for microelectronic components
US3623649A (en) 1969-06-09 1971-11-30 Gen Motors Corp Wedge bonding tool for the attachment of semiconductor leads
DE2119567C2 (de) 1970-05-05 1983-07-14 International Computers Ltd., London Elektrische Verbindungsvorrichtung und Verfahren zu ihrer Herstellung
DE2228703A1 (de) 1972-06-13 1974-01-10 Licentia Gmbh Verfahren zum herstellen einer vorgegebenen lotschichtstaerke bei der fertigung von halbleiterbauelementen
JPS5150661A (zh) 1974-10-30 1976-05-04 Hitachi Ltd
US4067104A (en) 1977-02-24 1978-01-10 Rockwell International Corporation Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components
US4213556A (en) 1978-10-02 1980-07-22 General Motors Corporation Method and apparatus to detect automatic wire bonder failure
US4327860A (en) 1980-01-03 1982-05-04 Kulicke And Soffa Ind. Inc. Method of making slack free wire interconnections
US4422568A (en) 1981-01-12 1983-12-27 Kulicke And Soffa Industries, Inc. Method of making constant bonding wire tail lengths
NL184184C (nl) * 1981-03-20 1989-05-01 Philips Nv Werkwijze voor het aanbrengen van kontaktverhogingen op kontaktplaatsen van een electronische microketen.
US4437604A (en) 1982-03-15 1984-03-20 Kulicke & Soffa Industries, Inc. Method of making fine wire interconnections
JPS59189069A (ja) 1983-04-12 1984-10-26 Alps Electric Co Ltd 電気部品の端子のハンダ塗布装置
JPS61125062A (ja) * 1984-11-22 1986-06-12 Hitachi Ltd ピン取付け方法およびピン取付け装置
US4604644A (en) 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US4642889A (en) 1985-04-29 1987-02-17 Amp Incorporated Compliant interconnection and method therefor
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US4924353A (en) 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
US4716049A (en) 1985-12-20 1987-12-29 Hughes Aircraft Company Compressive pedestal for microminiature connections
JPS62158338A (ja) 1985-12-28 1987-07-14 Tanaka Denshi Kogyo Kk 半導体装置
US4793814A (en) 1986-07-21 1988-12-27 Rogers Corporation Electrical circuit board interconnect
US4695870A (en) 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
JPS62226307A (ja) 1986-03-28 1987-10-05 Toshiba Corp ロボツト装置
US4771930A (en) * 1986-06-30 1988-09-20 Kulicke And Soffa Industries Inc. Apparatus for supplying uniform tail lengths
JPS6397941A (ja) 1986-10-14 1988-04-28 Fuji Photo Film Co Ltd 感光材料
US4955523A (en) * 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
DE3703694A1 (de) 1987-02-06 1988-08-18 Dynapert Delvotec Gmbh Ball-bondverfahren und vorrichtung zur durchfuehrung derselben
US5195237A (en) * 1987-05-21 1993-03-23 Cray Computer Corporation Flying leads for integrated circuits
KR970003915B1 (ko) 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
JP2642359B2 (ja) 1987-09-11 1997-08-20 株式会社日立製作所 半導体装置
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
US4804132A (en) 1987-08-28 1989-02-14 Difrancesco Louis Method for cold bonding
US4845354A (en) 1988-03-08 1989-07-04 International Business Machines Corporation Process control for laser wire bonding
JPH01313969A (ja) 1988-06-13 1989-12-19 Hitachi Ltd 半導体装置
US4998885A (en) * 1989-10-27 1991-03-12 International Business Machines Corporation Elastomeric area array interposer
US5077598A (en) 1989-11-08 1991-12-31 Hewlett-Packard Company Strain relief flip-chip integrated circuit assembly with test fixturing
AU637874B2 (en) 1990-01-23 1993-06-10 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
AU645283B2 (en) 1990-01-23 1994-01-13 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
US5948533A (en) 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
US5376403A (en) 1990-02-09 1994-12-27 Capote; Miguel A. Electrically conductive compositions and methods for the preparation and use thereof
US5083697A (en) 1990-02-14 1992-01-28 Difrancesco Louis Particle-enhanced joining of metal surfaces
US4975079A (en) 1990-02-23 1990-12-04 International Business Machines Corp. Connector assembly for chip testing
US4999472A (en) * 1990-03-12 1991-03-12 Neinast James E Electric arc system for ablating a surface coating
US5241456A (en) 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5067382A (en) 1990-11-02 1991-11-26 Cray Computer Corporation Method and apparatus for notching a lead wire attached to an IC chip to facilitate severing the wire
KR940001149B1 (ko) 1991-04-16 1994-02-14 삼성전자 주식회사 반도체 장치의 칩 본딩 방법
JPH04346436A (ja) * 1991-05-24 1992-12-02 Fujitsu Ltd バンプ製造方法とバンプ製造装置
US5316788A (en) 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates
US5203075A (en) 1991-08-12 1993-04-20 Inernational Business Machines Method of bonding flexible circuit to cicuitized substrate to provide electrical connection therebetween using different solders
US5133495A (en) 1991-08-12 1992-07-28 International Business Machines Corporation Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween
WO1993004375A1 (en) 1991-08-23 1993-03-04 Nchip, Inc. Burn-in technologies for unpackaged integrated circuits
US5220489A (en) 1991-10-11 1993-06-15 Motorola, Inc. Multicomponent integrated circuit package
US5238173A (en) 1991-12-04 1993-08-24 Kaijo Corporation Wire bonding misattachment detection apparatus and that detection method in a wire bonder
JP2931936B2 (ja) * 1992-01-17 1999-08-09 株式会社日立製作所 半導体装置用リードフレームの製造方法及び半導体装置用リードフレーム並びに樹脂封止型半導体装置
US5831836A (en) 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5438224A (en) 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5494667A (en) 1992-06-04 1996-02-27 Kabushiki Kaisha Hayahibara Topically applied hair restorer containing pine extract
KR100209457B1 (ko) 1992-07-24 1999-07-15 토마스 디스테파노 반도체 접속 부품과 그 제조 방법 및 반도체 칩 접속 방법
US5977618A (en) 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
US6054756A (en) 1992-07-24 2000-04-25 Tessera, Inc. Connection components with frangible leads and bus
US5371654A (en) * 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
US20050062492A1 (en) * 2001-08-03 2005-03-24 Beaman Brian Samuel High density integrated circuit apparatus, test probe and methods of use thereof
JP2716336B2 (ja) 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
JPH06268101A (ja) 1993-03-17 1994-09-22 Hitachi Ltd 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板
US5340771A (en) 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US7368924B2 (en) * 1993-04-30 2008-05-06 International Business Machines Corporation Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof
US5811982A (en) 1995-11-27 1998-09-22 International Business Machines Corporation High density cantilevered probe for electronic devices
US20030048108A1 (en) * 1993-04-30 2003-03-13 Beaman Brian Samuel Structural design and processes to control probe position accuracy in a wafer test probe assembly
JP2981385B2 (ja) 1993-09-06 1999-11-22 シャープ株式会社 チップ部品型ｌｅｄの構造及びその製造方法
US5346118A (en) 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US6835898B2 (en) 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
KR100437437B1 (ko) 1994-03-18 2004-06-25 히다치 가세고교 가부시끼가이샤 반도체 패키지의 제조법 및 반도체 패키지
US5802699A (en) 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
US5615824A (en) 1994-06-07 1997-04-01 Tessera, Inc. Soldering with resilient contacts
JPH07335783A (ja) 1994-06-13 1995-12-22 Fujitsu Ltd 半導体装置及び半導体装置ユニット
US5468995A (en) 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections
US5518964A (en) 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US5989936A (en) 1994-07-07 1999-11-23 Tessera, Inc. Microelectronic assembly fabrication with terminal formation from a conductive layer
US6117694A (en) 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US6828668B2 (en) 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5659952A (en) 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5541567A (en) * 1994-10-17 1996-07-30 International Business Machines Corporation Coaxial vias in an electronic substrate
US5495667A (en) 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
US5736074A (en) 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
US5971253A (en) 1995-07-31 1999-10-26 Tessera, Inc. Microelectronic component mounting with deformable shell terminals
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5810609A (en) 1995-08-28 1998-09-22 Tessera, Inc. Socket for engaging bump leads on a microelectronic device and methods therefor
US5766987A (en) 1995-09-22 1998-06-16 Tessera, Inc. Microelectronic encapsulation methods and equipment
US6211572B1 (en) 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
JP3332308B2 (ja) 1995-11-07 2002-10-07 新光電気工業株式会社 半導体装置及びその製造方法
JPH09134934A (ja) 1995-11-07 1997-05-20 Sumitomo Metal Ind Ltd 半導体パッケージ及び半導体装置
US5718361A (en) 1995-11-21 1998-02-17 International Business Machines Corporation Apparatus and method for forming mold for metallic material
US5731709A (en) 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US5994152A (en) * 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
JP3146345B2 (ja) * 1996-03-11 2001-03-12 アムコー テクノロジー コリア インコーポレーティド バンプチップスケール半導体パッケージのバンプ形成方法
US6000126A (en) 1996-03-29 1999-12-14 General Dynamics Information Systems, Inc. Method and apparatus for connecting area grid arrays to printed wire board
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
DE19618227A1 (de) 1996-05-07 1997-11-13 Herbert Streckfus Gmbh Verfahren und Vorrichtung zum Verlöten von elektronischen Bauelementen auf einer Leiterplatte
KR100186333B1 (ko) * 1996-06-20 1999-03-20 문정환 칩 사이즈 반도체 패키지 및 그 제조방법
JPH1012769A (ja) 1996-06-24 1998-01-16 Ricoh Co Ltd 半導体装置およびその製造方法
JPH10135221A (ja) * 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
US6492719B2 (en) 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device
US5976913A (en) 1996-12-12 1999-11-02 Tessera, Inc. Microelectronic mounting with multiple lead deformation using restraining straps
US6225688B1 (en) 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6133072A (en) 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
US6054337A (en) 1996-12-13 2000-04-25 Tessera, Inc. Method of making a compliant multichip package
US6121676A (en) 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
JP3400279B2 (ja) * 1997-01-13 2003-04-28 株式会社新川 バンプ形成方法
US5898991A (en) * 1997-01-16 1999-05-04 International Business Machines Corporation Methods of fabrication of coaxial vias and magnetic devices
US5839191A (en) 1997-01-24 1998-11-24 Unisys Corporation Vibrating template method of placing solder balls on the I/O pads of an integrated circuit package
JPH1118364A (ja) 1997-06-27 1999-01-22 Matsushita Electric Ind Co Ltd キャプスタンモータ
DE69838849T2 (de) 1997-08-19 2008-12-11 Hitachi, Ltd. Mehrchip-Modulstruktur und deren Herstellung
CA2213590C (en) 1997-08-21 2006-11-07 Keith C. Carroll Flexible circuit connector and method of making same
JP3859318B2 (ja) 1997-08-29 2006-12-20 シチズン電子株式会社 電子回路のパッケージ方法
US6525414B2 (en) 1997-09-16 2003-02-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a wiring board and semiconductor elements mounted thereon
JP3937265B2 (ja) 1997-09-29 2007-06-27 エルピーダメモリ株式会社 半導体装置
JP3262531B2 (ja) 1997-10-02 2002-03-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 曲げられたフライング・リード・ワイヤ・ボンデイング・プロセス
JP2978861B2 (ja) 1997-10-28 1999-11-15 九州日本電気株式会社 モールドｂｇａ型半導体装置及びその製造方法
US6038136A (en) 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
JP3393800B2 (ja) 1997-11-05 2003-04-07 新光電気工業株式会社 半導体装置の製造方法
JPH11219984A (ja) 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US6222136B1 (en) 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US6002168A (en) 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
JPH11163022A (ja) 1997-11-28 1999-06-18 Sony Corp 半導体装置、その製造方法及び電子機器
US6124546A (en) 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
US6260264B1 (en) 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US6052287A (en) 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
US5973391A (en) 1997-12-11 1999-10-26 Read-Rite Corporation Interposer with embedded circuitry and method for using the same to package microelectronic units
JPH11220082A (ja) 1998-02-03 1999-08-10 Oki Electric Ind Co Ltd 半導体装置
JPH11260856A (ja) * 1998-03-11 1999-09-24 Matsushita Electron Corp 半導体装置及びその製造方法並びに半導体装置の実装構造
KR100260997B1 (ko) 1998-04-08 2000-07-01 마이클 디. 오브라이언 반도체패키지
US6329224B1 (en) 1998-04-28 2001-12-11 Tessera, Inc. Encapsulation of microelectronic assemblies
US6180881B1 (en) 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
JPH11330134A (ja) 1998-05-12 1999-11-30 Hitachi Ltd ワイヤボンディング方法およびその装置並びに半導体装置
KR100266693B1 (ko) 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
KR100265563B1 (ko) 1998-06-29 2000-09-15 김영환 볼 그리드 어레이 패키지 및 그의 제조 방법
US6414391B1 (en) 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6164523A (en) 1998-07-01 2000-12-26 Semiconductor Components Industries, Llc Electronic component and method of manufacture
US6399426B1 (en) 1998-07-21 2002-06-04 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6515355B1 (en) 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
JP2000091383A (ja) 1998-09-07 2000-03-31 Ngk Spark Plug Co Ltd 配線基板
US6194250B1 (en) 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
US6158647A (en) 1998-09-29 2000-12-12 Micron Technology, Inc. Concave face wire bond capillary
US6684007B2 (en) 1998-10-09 2004-01-27 Fujitsu Limited Optical coupling structures and the fabrication processes
US6268662B1 (en) 1998-10-14 2001-07-31 Texas Instruments Incorporated Wire bonded flip-chip assembly of semiconductor devices
JP3407275B2 (ja) * 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション バンプ及びその形成方法
US6332270B2 (en) 1998-11-23 2001-12-25 International Business Machines Corporation Method of making high density integral test probe
US6926796B1 (en) 1999-01-29 2005-08-09 Matsushita Electric Industrial Co., Ltd. Electronic parts mounting method and device therefor
US6206273B1 (en) * 1999-02-17 2001-03-27 International Business Machines Corporation Structures and processes to create a desired probetip contact geometry on a wafer test probe
KR100319609B1 (ko) 1999-03-09 2002-01-05 김영환 와이어 어래이드 칩 사이즈 패키지 및 그 제조방법
US6177729B1 (en) 1999-04-03 2001-01-23 International Business Machines Corporation Rolling ball connector
US6211574B1 (en) 1999-04-16 2001-04-03 Advanced Semiconductor Engineering Inc. Semiconductor package with wire protection and method therefor
US6376769B1 (en) 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
JP3398721B2 (ja) 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
US6228687B1 (en) 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
TW417839U (en) 1999-07-30 2001-01-01 Shen Ming Tung Stacked memory module structure and multi-layered stacked memory module structure using the same
JP5333337B2 (ja) * 1999-08-12 2013-11-06 富士通セミコンダクター株式会社 半導体装置の製造方法
US6168965B1 (en) 1999-08-12 2001-01-02 Tower Semiconductor Ltd. Method for making backside illuminated image sensor
KR101084525B1 (ko) 1999-09-02 2011-11-18 이비덴 가부시키가이샤 프린트배선판 및 그 제조방법
US6867499B1 (en) 1999-09-30 2005-03-15 Skyworks Solutions, Inc. Semiconductor packaging
JP3513444B2 (ja) * 1999-10-20 2004-03-31 株式会社新川 ピン状ワイヤ等の形成方法
JP2001127246A (ja) 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
US6362525B1 (en) 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
JP3619410B2 (ja) 1999-11-18 2005-02-09 株式会社ルネサステクノロジ バンプ形成方法およびそのシステム
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
KR100426494B1 (ko) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
US6790757B1 (en) * 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
KR20010061849A (ko) 1999-12-29 2001-07-07 박종섭 웨이퍼 레벨 패키지
JP2001196407A (ja) 2000-01-14 2001-07-19 Seiko Instruments Inc 半導体装置および半導体装置の形成方法
US6710454B1 (en) 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
JP2001339011A (ja) 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP3980807B2 (ja) 2000-03-27 2007-09-26 株式会社東芝 半導体装置及び半導体モジュール
JP2001274196A (ja) 2000-03-28 2001-10-05 Rohm Co Ltd 半導体装置
KR100583491B1 (ko) 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6531335B1 (en) 2000-04-28 2003-03-11 Micron Technology, Inc. Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods
JP2001326236A (ja) 2000-05-12 2001-11-22 Nec Kyushu Ltd 半導体装置の製造方法
JP2001326304A (ja) 2000-05-15 2001-11-22 Toshiba Corp 半導体装置及びその製造方法
US6522018B1 (en) 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6647310B1 (en) 2000-05-30 2003-11-11 Advanced Micro Devices, Inc. Temperature control of an integrated circuit
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6560117B2 (en) 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6476583B2 (en) 2000-07-21 2002-11-05 Jomahip, Llc Automatic battery charging system for a battery back-up DC power supply
SE517086C2 (sv) 2000-08-08 2002-04-09 Ericsson Telefon Ab L M Förfarande för säkring av lodkulor och eventuella komponenter, vilka är fästa på en och samma sida av ett substrat
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6462575B1 (en) 2000-08-28 2002-10-08 Micron Technology, Inc. Method and system for wafer level testing and burning-in semiconductor components
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6507104B2 (en) 2000-09-07 2003-01-14 Siliconware Precision Industries Co., Ltd. Semiconductor package with embedded heat-dissipating device
US7009297B1 (en) 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
JP4505983B2 (ja) 2000-12-01 2010-07-21 日本電気株式会社 半導体装置
JP3798620B2 (ja) 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
KR100393102B1 (ko) 2000-12-29 2003-07-31 앰코 테크놀로지 코리아 주식회사 스택형 반도체패키지
AUPR244801A0 (en) 2001-01-10 2001-02-01 Silverbrook Research Pty Ltd A method and apparatus (WSM01)
US6388322B1 (en) 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
US6653170B1 (en) 2001-02-06 2003-11-25 Charles W. C. Lin Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit
JP2002280414A (ja) 2001-03-22 2002-09-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2002289769A (ja) 2001-03-26 2002-10-04 Matsushita Electric Ind Co Ltd 積層型半導体装置およびその製造方法
SG108245A1 (en) 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
US7115986B2 (en) 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6825552B2 (en) 2001-05-09 2004-11-30 Tessera, Inc. Connection components with anisotropic conductive material interconnection
TW544826B (en) 2001-05-18 2003-08-01 Nec Electronics Corp Flip-chip-type semiconductor device and manufacturing method thereof
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6754407B2 (en) 2001-06-26 2004-06-22 Intel Corporation Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board
US20030006494A1 (en) 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
US6451626B1 (en) 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
US6765287B1 (en) 2001-07-27 2004-07-20 Charles W. C. Lin Three-dimensional stacked semiconductor package
JP4023159B2 (ja) 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
WO2003019654A1 (en) 2001-08-22 2003-03-06 Tessera, Inc. Stacked chip assembly with stiffening layer
US7176506B2 (en) 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US20030057544A1 (en) 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US6977440B2 (en) 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
JP2005506690A (ja) 2001-10-09 2005-03-03 テッセラ，インコーポレイテッド 積層パッケージ
JP2003122611A (ja) 2001-10-11 2003-04-25 Oki Electric Ind Co Ltd データ提供方法及びサーバ装置
JP4257771B2 (ja) 2001-10-16 2009-04-22 シンジーテック株式会社 導電性ブレード
US20030094666A1 (en) 2001-11-16 2003-05-22 R-Tec Corporation Interposer
JP3875077B2 (ja) 2001-11-16 2007-01-31 富士通株式会社 電子デバイス及びデバイス接続方法
JP2003174124A (ja) 2001-12-04 2003-06-20 Sainekkusu:Kk 半導体装置の外部電極形成方法
JP3507059B2 (ja) 2002-06-27 2004-03-15 沖電気工業株式会社 積層マルチチップパッケージ
JP2003197669A (ja) * 2001-12-28 2003-07-11 Seiko Epson Corp ボンディング方法及びボンディング装置
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
JP3935370B2 (ja) * 2002-02-19 2007-06-20 セイコーエプソン株式会社 バンプ付き半導体素子の製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
SG115456A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
US6653723B2 (en) 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
KR100452819B1 (ko) 2002-03-18 2004-10-15 삼성전기주식회사 칩 패키지 및 그 제조방법
US6979230B2 (en) 2002-03-20 2005-12-27 Gabe Cherian Light socket
US7323767B2 (en) 2002-04-25 2008-01-29 Micron Technology, Inc. Standoffs for centralizing internals in packaging process
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7078822B2 (en) 2002-06-25 2006-07-18 Intel Corporation Microelectronic device interconnects
JP2004047702A (ja) 2002-07-11 2004-02-12 Toshiba Corp 半導体装置積層モジュール
US6756252B2 (en) 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
US6987032B1 (en) 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
US7053485B2 (en) 2002-08-16 2006-05-30 Tessera, Inc. Microelectronic packages with self-aligning features
TW549592U (en) 2002-08-16 2003-08-21 Via Tech Inc Integrated circuit package with a balanced-part structure
US6740546B2 (en) 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP3765778B2 (ja) 2002-08-29 2006-04-12 ローム株式会社 ワイヤボンディング用キャピラリ及びこれを用いたワイヤボンディング方法
JP2004095799A (ja) 2002-08-30 2004-03-25 Toshiba Corp 半導体装置およびその製造方法
US7246431B2 (en) 2002-09-06 2007-07-24 Tessera, Inc. Methods of making microelectronic packages including folded substrates
US7294928B2 (en) 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
US7071547B2 (en) 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US7229906B2 (en) * 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
JP2006501677A (ja) 2002-09-30 2006-01-12 アドバンスド インターコネクト テクノロジーズ リミテッド ブロック成形集成体用の耐熱強化パッケージ
US7045884B2 (en) 2002-10-04 2006-05-16 International Rectifier Corporation Semiconductor device package
TWI322448B (en) 2002-10-08 2010-03-21 Chippac Inc Semiconductor stacked multi-package module having inverted second package
US6989122B1 (en) 2002-10-17 2006-01-24 National Semiconductor Corporation Techniques for manufacturing flash-free contacts on a semiconductor package
TW567601B (en) 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
JP2004172157A (ja) 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd 半導体パッケージおよびパッケージスタック半導体装置
JP2004172477A (ja) * 2002-11-21 2004-06-17 Kaijo Corp ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置
JP4464041B2 (ja) 2002-12-13 2010-05-19 キヤノン株式会社 柱状構造体、柱状構造体を有する電極、及びこれらの作製方法
KR100621991B1 (ko) 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지
JP2004221257A (ja) * 2003-01-14 2004-08-05 Seiko Epson Corp ワイヤボンディング方法及びワイヤボンディング装置
WO2004077525A2 (en) 2003-02-25 2004-09-10 Tessera, Inc. Ball grid array with bumps
TW583757B (en) 2003-02-26 2004-04-11 Advanced Semiconductor Eng A structure of a flip-chip package and a process thereof
US20040217471A1 (en) 2003-02-27 2004-11-04 Tessera, Inc. Component and assemblies with ends offset downwardly
JP3885747B2 (ja) 2003-03-13 2007-02-28 株式会社デンソー ワイヤボンディング方法
JP2004343030A (ja) 2003-03-31 2004-12-02 North:Kk 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
JP2004319892A (ja) 2003-04-18 2004-11-11 Renesas Technology Corp 半導体装置の製造方法
JP4199588B2 (ja) 2003-04-25 2008-12-17 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法
DE10320646A1 (de) 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
JP2005002765A (ja) 2003-06-11 2005-01-06 Tamotsu Shimauchi 震災非常時の脱出避難自動開き装置
JP4145730B2 (ja) 2003-06-17 2008-09-03 松下電器産業株式会社 半導体内蔵モジュール
KR100604821B1 (ko) 2003-06-30 2006-07-26 삼성전자주식회사 적층형 볼 그리드 어레이 패키지 및 그 제조방법
US20040262728A1 (en) 2003-06-30 2004-12-30 Sterrett Terry L. Modular device assemblies
JP2005033141A (ja) 2003-07-11 2005-02-03 Sony Corp 半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びに半導体装置の実装構造
US7227095B2 (en) * 2003-08-06 2007-06-05 Micron Technology, Inc. Wire bonders and methods of wire-bonding
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
KR100546374B1 (ko) 2003-08-28 2006-01-26 삼성전자주식회사 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7061096B2 (en) 2003-09-24 2006-06-13 Silicon Pipe, Inc. Multi-surface IC packaging structures and methods for their manufacture
JP2007516602A (ja) 2003-09-26 2007-06-21 テッセラ，インコーポレイテッド 流動可能な伝導媒体を含むキャップ付きチップの製造構造および方法
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
JP4272968B2 (ja) 2003-10-16 2009-06-03 エルピーダメモリ株式会社 半導体装置および半導体チップ制御方法
JP4167965B2 (ja) 2003-11-07 2008-10-22 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路用部材の製造方法
KR100564585B1 (ko) 2003-11-13 2006-03-28 삼성전자주식회사 이중 스택된 ｂｇａ 패키지 및 다중 스택된 ｂｇａ 패키지
TWI227555B (en) 2003-11-17 2005-02-01 Advanced Semiconductor Eng Structure of chip package and the process thereof
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP2005183923A (ja) 2003-11-28 2005-07-07 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7345361B2 (en) 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
JP2005175019A (ja) 2003-12-08 2005-06-30 Sharp Corp 半導体装置及び積層型半導体装置
JP5197961B2 (ja) 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド マルチチップパッケージモジュールおよびその製造方法
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
JP4334996B2 (ja) 2003-12-24 2009-09-30 株式会社フジクラ 多層配線板用基材、両面配線板およびそれらの製造方法
US7495644B2 (en) 2003-12-26 2009-02-24 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing display device
US6900530B1 (en) 2003-12-29 2005-05-31 Ramtek Technology, Inc. Stacked IC
US6917098B1 (en) 2003-12-29 2005-07-12 Texas Instruments Incorporated Three-level leadframe for no-lead packages
US8207604B2 (en) 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
US7709968B2 (en) 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
US7176043B2 (en) 2003-12-30 2007-02-13 Tessera, Inc. Microelectronic packages and methods therefor
JP2005203497A (ja) 2004-01-14 2005-07-28 Toshiba Corp 半導体装置およびその製造方法
US20050173807A1 (en) 2004-02-05 2005-08-11 Jianbai Zhu High density vertically stacked semiconductor device
US8399972B2 (en) 2004-03-04 2013-03-19 Skyworks Solutions, Inc. Overmolded semiconductor package with a wirebond cage for EMI shielding
US7095105B2 (en) 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
US8092734B2 (en) 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US7629695B2 (en) 2004-05-20 2009-12-08 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
US6962864B1 (en) * 2004-05-26 2005-11-08 National Chung Cheng University Wire-bonding method for chips with copper interconnects by introducing a thin layer
US7233057B2 (en) 2004-05-28 2007-06-19 Nokia Corporation Integrated circuit package with optimized mold shape
TWI255022B (en) 2004-05-31 2006-05-11 Via Tech Inc Circuit carrier and manufacturing process thereof
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
TWI250596B (en) 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
JP4385329B2 (ja) 2004-10-08 2009-12-16 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
WO2006050691A2 (de) 2004-11-02 2006-05-18 Imasys Ag Verlegevorrichtung, kontaktiervorrichtung, zustellsystem, verlege- und kontaktiereinheit herstellungsanlage, verfahren zur herstellung und eine transpondereinheit
KR101313391B1 (ko) 2004-11-03 2013-10-01 테세라, 인코포레이티드 적층형 패키징
US7268421B1 (en) 2004-11-10 2007-09-11 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
KR100674926B1 (ko) 2004-12-08 2007-01-26 삼성전자주식회사 메모리 카드 및 그 제조 방법
JP4504798B2 (ja) 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
JP2006186086A (ja) 2004-12-27 2006-07-13 Itoo:Kk プリント基板のはんだ付け方法およびブリッジ防止用ガイド板
DE102005006333B4 (de) 2005-02-10 2007-10-18 Infineon Technologies Ag Halbleiterbauteil mit mehreren Bondanschlüssen und gebondeten Kontaktelementen unterschiedlicher Metallzusammensetzung und Verfahren zur Herstellung desselben
DE102005006995B4 (de) 2005-02-15 2008-01-24 Infineon Technologies Ag Halbleiterbauteil mit Kunstoffgehäuse und Außenanschlüssen sowie Verfahren zur Herstellung desselben
KR100630741B1 (ko) 2005-03-04 2006-10-02 삼성전자주식회사 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법
US7939934B2 (en) 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US7371676B2 (en) * 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
TWI284394B (en) 2005-05-12 2007-07-21 Advanced Semiconductor Eng Lid used in package structure and the package structure of having the same
JP2006324553A (ja) * 2005-05-20 2006-11-30 Renesas Technology Corp 半導体装置及びその製造方法
US7216794B2 (en) * 2005-06-09 2007-05-15 Texas Instruments Incorporated Bond capillary design for ribbon wire bonding
JP4322844B2 (ja) 2005-06-10 2009-09-02 シャープ株式会社 半導体装置および積層型半導体装置
EP1905083A2 (en) 2005-07-01 2008-04-02 Koninklijke Philips Electronics N.V. Electronic device
US7476608B2 (en) * 2005-07-14 2009-01-13 Hewlett-Packard Development Company, L.P. Electrically connecting substrate with electrical device
TWI263313B (en) 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
JP5522561B2 (ja) 2005-08-31 2014-06-18 マイクロン テクノロジー， インク． マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法
US7675152B2 (en) 2005-09-01 2010-03-09 Texas Instruments Incorporated Package-on-package semiconductor assembly
US7504716B2 (en) 2005-10-26 2009-03-17 Texas Instruments Incorporated Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
JP2007123595A (ja) 2005-10-28 2007-05-17 Nec Corp 半導体装置及びその実装構造
EP1946364A1 (en) 2005-11-01 2008-07-23 Koninklijke Philips Electronics N.V. Methods of packaging a semiconductor die and package formed by the methods
JP4530975B2 (ja) * 2005-11-14 2010-08-25 株式会社新川 ワイヤボンディング方法
JP2007142042A (ja) 2005-11-16 2007-06-07 Sharp Corp 半導体パッケージとその製造方法，半導体モジュール，および電子機器
US7344917B2 (en) 2005-11-30 2008-03-18 Freescale Semiconductor, Inc. Method for packaging a semiconductor device
US7307348B2 (en) 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
JP4530984B2 (ja) 2005-12-28 2010-08-25 株式会社新川 ワイヤボンディング装置、ボンディング制御プログラム及びボンディング方法
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
JP2007208159A (ja) 2006-02-06 2007-08-16 Hitachi Ltd 半導体装置
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
JP2007234845A (ja) * 2006-03-01 2007-09-13 Nec Corp 半導体装置
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7759782B2 (en) 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
JP5598787B2 (ja) 2006-04-17 2014-10-01 マイクロンメモリジャパン株式会社 積層型半導体装置の製造方法
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US7780064B2 (en) 2006-06-02 2010-08-24 Asm Technology Singapore Pte Ltd Wire bonding method for forming low-loop profiles
JP4961848B2 (ja) 2006-06-12 2012-06-27 日本電気株式会社 金属ポストを有する配線基板、半導体装置及び半導体装置モジュールの製造方法
US20070290325A1 (en) 2006-06-16 2007-12-20 Lite-On Semiconductor Corporation Surface mounting structure and packaging method thereof
US7967062B2 (en) 2006-06-16 2011-06-28 International Business Machines Corporation Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof
KR101043484B1 (ko) 2006-06-29 2011-06-23 인텔 코포레이션 집적 회로 패키지를 포함하는 장치, 시스템 및 집적 회로 패키지의 제조 방법
KR100792352B1 (ko) 2006-07-06 2008-01-08 삼성전기주식회사 패키지 온 패키지의 바텀기판 및 그 제조방법
KR100800478B1 (ko) 2006-07-18 2008-02-04 삼성전자주식회사 적층형 반도체 패키지 및 그의 제조방법
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
US8048479B2 (en) 2006-08-01 2011-11-01 Qimonda Ag Method for placing material onto a target board by means of a transfer board
JP2008039502A (ja) 2006-08-03 2008-02-21 Alps Electric Co Ltd 接触子およびその製造方法
US7486525B2 (en) 2006-08-04 2009-02-03 International Business Machines Corporation Temporary chip attach carrier
US7425758B2 (en) 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
KR20080020069A (ko) 2006-08-30 2008-03-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR100891516B1 (ko) 2006-08-31 2009-04-06 주식회사 하이닉스반도체 적층 가능한 에프비지에이 타입 반도체 패키지와 이를이용한 적층 패키지
KR100770934B1 (ko) 2006-09-26 2007-10-26 삼성전자주식회사 반도체 패키지와 그를 이용한 반도체 시스템 패키지
TWI336502B (en) 2006-09-27 2011-01-21 Advanced Semiconductor Eng Semiconductor package and semiconductor device and the method of making the same
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
TWI312561B (en) 2006-10-27 2009-07-21 Advanced Semiconductor Eng Structure of package on package and method for fabricating the same
KR100817073B1 (ko) 2006-11-03 2008-03-26 삼성전자주식회사 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
WO2008065896A1 (fr) 2006-11-28 2008-06-05 Kyushu Institute Of Technology Procédé de fabrication d'un dispositif semi-conducteur ayant une structure d'électrode à double face et dispositif semi-conducteur fabriqué par le procédé
US8598717B2 (en) 2006-12-27 2013-12-03 Spansion Llc Semiconductor device and method for manufacturing the same
JP2008166439A (ja) * 2006-12-27 2008-07-17 Spansion Llc 半導体装置およびその製造方法
KR100757345B1 (ko) 2006-12-29 2007-09-10 삼성전자주식회사 플립 칩 패키지 및 그의 제조 방법
US20080156518A1 (en) 2007-01-03 2008-07-03 Tessera, Inc. Alignment and cutting of microelectronic substrates
TWI332702B (en) 2007-01-09 2010-11-01 Advanced Semiconductor Eng Stackable semiconductor package and the method for making the same
JP5347222B2 (ja) * 2007-01-10 2013-11-20 富士通株式会社 半導体装置の製造方法
US7719122B2 (en) 2007-01-11 2010-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. System-in-package packaging for minimizing bond wire contamination and yield loss
KR100827667B1 (ko) 2007-01-16 2008-05-07 삼성전자주식회사 기판 내에 반도체 칩을 갖는 반도체 패키지 및 이를제조하는 방법
JP4823089B2 (ja) 2007-01-31 2011-11-24 株式会社東芝 積層型半導体装置の製造方法
KR101057368B1 (ko) 2007-01-31 2011-08-18 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법
US8685792B2 (en) 2007-03-03 2014-04-01 Stats Chippac Ltd. Integrated circuit package system with interposer
JP5584474B2 (ja) 2007-03-05 2014-09-03 インヴェンサス・コーポレイション 貫通ビアによって前面接点に接続された後面接点を有するチップ
US7517733B2 (en) 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
TWI335070B (en) 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
US8183684B2 (en) * 2007-03-23 2012-05-22 Semiconductor Components Industries, Llc Semiconductor device and method of manufacturing the same
JP4926787B2 (ja) 2007-03-30 2012-05-09 アオイ電子株式会社 半導体装置の製造方法
WO2008120755A1 (ja) 2007-03-30 2008-10-09 Nec Corporation 機能素子内蔵回路基板及びその製造方法、並びに電子機器
US7589394B2 (en) 2007-04-10 2009-09-15 Ibiden Co., Ltd. Interposer
JP5003260B2 (ja) 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
US7994622B2 (en) 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
KR20080094251A (ko) 2007-04-19 2008-10-23 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조방법
JP5601751B2 (ja) 2007-04-26 2014-10-08 スパンション エルエルシー 半導体装置
US20080284045A1 (en) 2007-05-18 2008-11-20 Texas Instruments Incorporated Method for Fabricating Array-Molded Package-On-Package
JP2008306128A (ja) 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
KR100865125B1 (ko) 2007-06-12 2008-10-24 삼성전기주식회사 반도체 패키지 및 그 제조방법
US20080308305A1 (en) 2007-06-15 2008-12-18 Ngk Spark Plug Co., Ltd. Wiring substrate with reinforcing member
US7944034B2 (en) 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
JP5179787B2 (ja) 2007-06-22 2013-04-10 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7911805B2 (en) 2007-06-29 2011-03-22 Tessera, Inc. Multilayer wiring element having pin interface
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR20090007120A (ko) 2007-07-13 2009-01-16 삼성전자주식회사 봉지부를 통하여 재배선을 달성하는 웨이퍼 레벨 적층형패키지 및 그 제조방법
US7781877B2 (en) 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
JP2009044110A (ja) 2007-08-13 2009-02-26 Elpida Memory Inc 半導体装置及びその製造方法
SG150396A1 (en) 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
US8039960B2 (en) 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
JP2009088254A (ja) 2007-09-28 2009-04-23 Toshiba Corp 電子部品パッケージ及び電子部品パッケージの製造方法
KR101388538B1 (ko) 2007-09-28 2014-04-23 테세라, 인코포레이티드 이중 포스트를 사용하여 플립칩 상호연결한 마이크로전자 어셈블리
KR20090033605A (ko) 2007-10-01 2009-04-06 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US20090091009A1 (en) 2007-10-03 2009-04-09 Corisis David J Stackable integrated circuit package
US8008183B2 (en) 2007-10-04 2011-08-30 Texas Instruments Incorporated Dual capillary IC wirebonding
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
TWI389220B (zh) 2007-10-22 2013-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
JP2009123863A (ja) 2007-11-14 2009-06-04 Tessera Interconnect Materials Inc バンプ構造形成方法及びバンプ構造
US20090127686A1 (en) 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
KR100886100B1 (ko) 2007-11-29 2009-02-27 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
JP2009135398A (ja) 2007-11-29 2009-06-18 Ibiden Co Ltd 組合せ基板
US7902644B2 (en) 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation
US7964956B1 (en) 2007-12-10 2011-06-21 Oracle America, Inc. Circuit packaging and connectivity
US8390117B2 (en) 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
JP2009158593A (ja) 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
US20090170241A1 (en) 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
JP5292827B2 (ja) * 2008-01-24 2013-09-18 富士通株式会社 半導体装置の製造方法及び半導体装置の製造装置
US8048720B2 (en) 2008-01-30 2011-11-01 Kulicke And Soffa Industries, Inc. Wire loop and method of forming the wire loop
US8120186B2 (en) 2008-02-15 2012-02-21 Qimonda Ag Integrated circuit and method
US8258015B2 (en) 2008-02-22 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with penetrable film adhesive
US7956456B2 (en) 2008-02-27 2011-06-07 Texas Instruments Incorporated Thermal interface material design for enhanced thermal performance and improved package structural integrity
US7919871B2 (en) 2008-03-21 2011-04-05 Stats Chippac Ltd. Integrated circuit package system for stackable devices
KR101501739B1 (ko) 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
US8072079B2 (en) 2008-03-27 2011-12-06 Stats Chippac, Ltd. Through hole vias at saw streets including protrusions or recesses for interconnection
JP5043743B2 (ja) 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法
KR20090123680A (ko) 2008-05-28 2009-12-02 주식회사 하이닉스반도체 적층 반도체 패키지
US8021907B2 (en) 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
EP2308087B1 (en) 2008-06-16 2020-08-12 Tessera, Inc. Stacking of wafer-level chip scale packages having edge contacts
US7932170B1 (en) 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
TWI473553B (zh) 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US7859033B2 (en) 2008-07-09 2010-12-28 Eastman Kodak Company Wafer level processing for backside illuminated sensors
JP5339800B2 (ja) 2008-07-10 2013-11-13 三菱電機株式会社 半導体装置の製造方法
TWI372453B (en) * 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
TWI573201B (zh) 2008-07-18 2017-03-01 聯測總部私人有限公司 封裝結構性元件
US8004093B2 (en) 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
US20100044860A1 (en) 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
KR100997793B1 (ko) 2008-09-01 2010-12-02 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
KR20100033012A (ko) 2008-09-19 2010-03-29 주식회사 하이닉스반도체 반도체 패키지 및 이를 갖는 적층 반도체 패키지
US7842541B1 (en) 2008-09-24 2010-11-30 Amkor Technology, Inc. Ultra thin package and fabrication method
US8063475B2 (en) 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
JPWO2010041630A1 (ja) 2008-10-10 2012-03-08 日本電気株式会社 半導体装置及びその製造方法
JP5185062B2 (ja) 2008-10-21 2013-04-17 パナソニック株式会社 積層型半導体装置及び電子機器
MY149251A (en) 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
KR101461630B1 (ko) 2008-11-06 2014-11-20 삼성전자주식회사 실장 높이는 축소되나, 솔더 접합 신뢰도는 개선되는 웨이퍼 레벨 칩 온 칩 패키지와, 패키지 온 패키지 및 그 제조방법
TW201023308A (en) 2008-12-01 2010-06-16 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
KR101011863B1 (ko) 2008-12-02 2011-01-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US7898083B2 (en) 2008-12-17 2011-03-01 Texas Instruments Incorporated Method for low stress flip-chip assembly of fine-pitch semiconductor devices
US8012797B2 (en) 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
JP2010199528A (ja) 2009-01-27 2010-09-09 Tatsuta System Electronics Kk ボンディングワイヤ
JP2010177597A (ja) 2009-01-30 2010-08-12 Sanyo Electric Co Ltd 半導体モジュールおよび携帯機器
US20100200981A1 (en) 2009-02-09 2010-08-12 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
JP2010206007A (ja) 2009-03-04 2010-09-16 Nec Corp 半導体装置及びその製造方法
WO2010101163A1 (ja) 2009-03-04 2010-09-10 日本電気株式会社 機能素子内蔵基板及びそれを用いた電子デバイス
US8106498B2 (en) 2009-03-05 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof
US8258010B2 (en) 2009-03-17 2012-09-04 Stats Chippac, Ltd. Making a semiconductor device having conductive through organic vias
US20100244276A1 (en) 2009-03-25 2010-09-30 Lsi Corporation Three-dimensional electronics package
US8194411B2 (en) 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules
US20100289142A1 (en) 2009-05-15 2010-11-18 Il Kwon Shim Integrated circuit packaging system with coin bonded interconnects and method of manufacture thereof
US8020290B2 (en) * 2009-06-14 2011-09-20 Jayna Sheats Processes for IC fabrication
TWI379367B (en) 2009-06-15 2012-12-11 Kun Yuan Technology Co Ltd Chip packaging method and structure thereof
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
JP5214554B2 (ja) 2009-07-30 2013-06-19 ラピスセミコンダクタ株式会社 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法
US7923304B2 (en) 2009-09-10 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8264091B2 (en) 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US8390108B2 (en) 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
US8169065B2 (en) 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
TWI392066B (zh) 2009-12-28 2013-04-01 矽品精密工業股份有限公司 封裝結構及其製法
US9496152B2 (en) 2010-03-12 2016-11-15 STATS ChipPAC Pte. Ltd. Carrier system with multi-tier conductive posts and method of manufacture thereof
US7928552B1 (en) 2010-03-12 2011-04-19 Stats Chippac Ltd. Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof
KR101667656B1 (ko) 2010-03-24 2016-10-20 삼성전자주식회사 패키지-온-패키지 형성방법
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8564141B2 (en) 2010-05-06 2013-10-22 SK Hynix Inc. Chip unit and stack package having the same
US8217502B2 (en) 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
KR20120007839A (ko) 2010-07-15 2012-01-25 삼성전자주식회사 적층형 반도체 패키지의 제조방법
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
KR101683814B1 (ko) 2010-07-26 2016-12-08 삼성전자주식회사 관통 전극을 구비하는 반도체 장치
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8304900B2 (en) 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
US8518746B2 (en) 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US20120063090A1 (en) 2010-09-09 2012-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling mechanism for stacked die package and method of manufacturing the same
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US20120080787A1 (en) 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
JP2012104790A (ja) 2010-10-12 2012-05-31 Elpida Memory Inc 半導体装置
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8263435B2 (en) 2010-10-28 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias
US8697492B2 (en) 2010-11-02 2014-04-15 Tessera, Inc. No flow underfill
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US8502387B2 (en) 2010-12-09 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
KR101215271B1 (ko) 2010-12-29 2012-12-26 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 반도체 패키지 구조물의 제조 방법
US20120184116A1 (en) 2011-01-18 2012-07-19 Tyco Electronics Corporation Interposer
US8476115B2 (en) 2011-05-03 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US9006031B2 (en) 2011-06-23 2015-04-14 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumps
US8487421B2 (en) 2011-08-01 2013-07-16 Tessera, Inc. Microelectronic package with stacked microelectronic elements and method for manufacture thereof
US8937309B2 (en) 2011-08-08 2015-01-20 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US20130037929A1 (en) 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
US20130049218A1 (en) 2011-08-31 2013-02-28 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation
KR101800440B1 (ko) 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
US9177832B2 (en) 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9105552B2 (en) 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
KR101297015B1 (ko) 2011-11-03 2013-08-14 주식회사 네패스 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지
US8912651B2 (en) 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
US8680684B2 (en) 2012-01-09 2014-03-25 Invensas Corporation Stackable microelectronic package structures
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US20130234317A1 (en) 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9082763B2 (en) 2012-03-15 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure for substrates and methods of forming
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9171790B2 (en) 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8828860B2 (en) 2012-08-30 2014-09-09 International Business Machines Corporation Double solder bumps on substrates for low temperature flip chip bonding
KR101419597B1 (ko) 2012-11-06 2014-07-14 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US8940630B2 (en) 2013-02-01 2015-01-27 Invensas Corporation Method of making wire bond vias and microelectronic package having wire bond vias
US9299670B2 (en) 2013-03-14 2016-03-29 Freescale Semiconductor, Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095187A (en) * 1989-12-20 1992-03-10 Raychem Corporation Weakening wire supplied through a wire bonder
US20010045012A1 (en) * 1992-10-19 2001-11-29 Beaman Brian Samuel Angled flying lead wire bonding process
JPH10135220A (ja) * 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
JPH11251350A (ja) * 1998-02-27 1999-09-17 Fuji Xerox Co Ltd バンプ形成方法および装置
US6476503B1 (en) * 1999-08-12 2002-11-05 Fujitsu Limited Semiconductor device having columnar electrode and method of manufacturing same
US20010002607A1 (en) * 1999-12-02 2001-06-07 Kazuo Sugiura Method for forming pin-form wires and the like
US7750483B1 (en) * 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal

Also Published As

Publication number Publication date
US20130224914A1 (en) 2013-08-29
CN104170083B (zh) 2018-01-09
KR20140124011A (ko) 2014-10-23
JP2017038074A (ja) 2017-02-16
KR101571457B1 (ko) 2015-11-24
US20160260647A1 (en) 2016-09-08
KR20150135543A (ko) 2015-12-02
WO2013126269A1 (en) 2013-08-29
TWI596682B (zh) 2017-08-21
US9691679B2 (en) 2017-06-27
JP6239718B2 (ja) 2017-11-29
TW201347059A (zh) 2013-11-16
JP2015508240A (ja) 2015-03-16
US8372741B1 (en) 2013-02-12
EP2817823A1 (en) 2014-12-31
US8772152B2 (en) 2014-07-08
CN104170083A (zh) 2014-11-26
EP2817823B1 (en) 2018-09-12
JP6025875B2 (ja) 2016-11-16
TW201643975A (zh) 2016-12-16

Similar Documents

Publication Publication Date Title
TWI553754B (zh) 用於藉由至密封表面之導線接合之疊合封裝組合之方法
US11424211B2 (en) Package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) Method for package-on-package assembly with wire bonds to encapsulation surface
US9093435B2 (en) Package-on-package assembly with wire bonds to encapsulation surface
TWI570864B (zh) 具有焊線通孔的微電子封裝、其之製造方法以及用於其之硬化層
US20220375891A1 (en) Package-on-package assembly with wire bonds to encapsulation surface
KR20120125148A (ko) 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리