TWI490978B - 三維積體電路方法及裝置 - Google Patents
三維積體電路方法及裝置 Download PDFInfo
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- TWI490978B TWI490978B TW095129638A TW95129638A TWI490978B TW I490978 B TWI490978 B TW I490978B TW 095129638 A TW095129638 A TW 095129638A TW 95129638 A TW95129638 A TW 95129638A TW I490978 B TWI490978 B TW I490978B
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Classifications
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Description
本發明係關於三維積體電路之領域且更特定言之係關於使用直接晶圓接合之三維積體電路之裝置及其製造。
半導體積體電路(IC)通常經製造入一矽晶圓之表面且在矽晶圓之表面上製造,其產生一必須隨著該IC之尺寸增加而增加之IC面積。減小IC中電晶體之尺寸之持續改良通常稱為莫耳定律,已允許在一給定IC面積中電晶體之數目的一實質增加。然而,不顧此增加之電晶體密度,歸因於用以達成一特殊功能的所需電晶體數之更大增加或電晶體之間所需之橫向互連之數目的增加,許多應用需要總體IC面積之增加。在一單一大面積IC晶粒中之此等應用的實現通常導致晶片良率之降低,且相應地,增加的IC成本。
IC製造中之另一趨勢已增加一單一IC內不同類型之電路的數目,該IC更通常地稱為一晶片上系統(SoC)。此製造通常需要遮罩層之數目的增加以製造不同類型的電路。此遮罩層增加通常亦導致良率之降低,且相應地,增加之IC成本。避免此等非所要之良率降低及成本增加之解決方法為垂直堆疊及垂直互連IC。此等IC可具有不同尺寸,來自不同尺寸晶圓,包含不同功能(意即類比、數位、光學),由不同材料製成(意即矽、GaAs、InP等等)。該等IC可在堆疊之前加以測試以允許良裸晶粒(KGD)經組合以改良良率。此垂直堆疊及垂直互連方法之經濟成功視與增加之IC或SoC面積相關聯的良率及成本相比堆疊及互連之良率及成本是否有利而定。一種用於實現此方法之可製造方法為使用直接接合來垂直堆疊IC及使用包括晶圓薄化、光微影遮罩、通道蝕刻及互連金屬化之習知晶圓製造技術來形成垂直互連結構。堆疊IC之間的垂直電互連可作為直接接合之堆疊之直接結果或作為直接接合之堆疊之後的一序列之晶圓製造技術的結果而加以形成。
此方法之垂直互連部分之成本直接與蝕刻通道及形成電互連所需的光微影遮罩層之數目相關。因此需要使形成垂直互連所需之光微影遮罩層之數目最小化。
垂直堆疊及垂直互連之一型式為(一基板上之)IC面對面或IC側對IC側接合處。此型式可以一晶圓對晶圓格式而得以完成,但通常較佳以一晶粒對晶圓格式得以完成,其中晶粒IC側向下接合至一IC側向上之晶圓以允許良裸晶粒之堆疊以改良良率。垂直互連可作為堆疊之直接結果而加以形成,例如在申請案10/359,608中所描述,或作為直接接合之堆疊之後的一序列之晶圓製造技術之結果而加以形成。直接接合之堆疊之後的該序列之晶圓製造技術通常包括以下技術。晶粒通常大體上藉由移除大部分晶粒基板而加以薄化。一般而言,歸因於基板中電晶體之位置(例如在塊狀CMOS IC中之狀況),晶粒基板不可總體地經移除。因此通常將基板移除至可實行之最大程度,保留足夠之剩餘基板以避免對電晶體之損害。接著,晶粒IC之互連藉由蝕刻一通過剩餘基板至晶粒IC中之一互連位置的通道而加以形成,使得此通道附近不存在必要的電晶體。此外,為達成最高之互連密度,較佳將此通道通過整個晶粒IC且進入晶圓IC而延續至晶圓IC中的一互連位置。此通道通常延伸通過提供與晶粒IC及晶圓IC中互連位置之所要電隔離的絕緣介電材料且暴露晶粒IC及晶圓IC中的所要電連接位置。在形成此通道之後,可以導電材料製造一垂直互連至晶粒IC及晶圓IC中暴露之所要電連接位置。導電材料與通道側壁上所暴露之基板之間的一絕緣層可用於避免導電材料與基板之間的非所要電傳導。
此結構之製造通常以四個光微影遮罩層來建置。此等層為1)通過基板之通道蝕刻,2)暴露晶粒IC及晶圓IC中所要導電材料的通過晶粒IC及晶圓IC中之絕緣介電材料的通道蝕刻,3)通過一隨後沈積之絕緣層之通道蝕刻,該絕緣層電隔離將晶粒IC中之互連位置及晶圓IC中之互連位置互連至暴露晶粒IC及晶圓IC中之所要導電材料的暴露之基板通道側壁的導電材料,4)與晶粒IC中暴露之互連點與晶圓IC中暴露之互連點之間的導電材料的互連。
界定通過絕緣(介電)材料之通道蝕刻的圖案通常小於界定通過基板之通道蝕刻的圖案以充分暴露晶粒IC及晶圓IC中的互連點且避免移除基板通道側壁上之絕緣材料。因為此等圖案在基板中通道之後加以形成,所以此圖案化通常在一低於基板通道之圖案化的地形層處加以完成。此在一非平坦結構上產生一圖案化,其將結構之縮放比例限制為達成最高互連密度所要之極小特徵尺寸且消耗最少可能的矽基板,其中功能性電晶體以其他方式駐留。
因此需要具有一包含一結構之裝置及一製造該結構之方法,該方法需要減少數目的遮罩步驟及可在一平坦表面上,在該結構中地形之最高層或最高層中之一者處實現的遮罩步驟。進一步需要具有一包含一結構之裝置及一製造該結構之方法,藉以達成一最小矽消耗量,其中功能性電晶體將以其他方式駐留。
本發明係針對一種三維裝置整合之方法及一種三維整合裝置。
在該方法之一實例中,一具有一第一接觸結構之第一元件與一具有一第二接觸結構的第二元件整合。本方法可包括以下步驟:在該第一元件中形成一暴露至至少該第一接觸結構之通道;在該通道中形成一連接至至少該第一接觸結構之導電材料;及將該第一元件接合至該第二元件,使得該第一接觸結構及該導電材料中之一者直接連接至該第二接觸結構。
在一第二實例中,該方法可包括以下步驟:在一第一元件中形成一通道;在該通道中形成一第一導電材料;將該第一導電材料連接至該第一接觸結構;及將該第一元件接合至該第二元件,使得該第一接觸結構及該第一導電材料中之一者直接連接至該第二接觸結構。
在一第三實例中,該方法包括以下步驟:在一具有一第一基板之第一元件中形成一通道;在該通道中形成一導電材料;在形成該通道及該導電材料之後在該第一元件中形成一電連接至該導電材料的接觸結構;形成一具有至少一第二接觸結構之第二元件;移除該第一基板之一部分以暴露該通道及該導電材料;將該第一基板接合至第二基板;及在該第二接觸結構與該第一接觸結構及該導電材料中的一者之間形成一連接作為該接合步驟之一部分。
在根據本發明之整合結構之一實例中,一第一元件具有一第一接觸結構,一第二元件具有一第二接觸結構,一第一通道形成於該第一元件中,一第一導電材料形成於連接至該第一接觸結構的該第一通道中,且該第一元件接合至該第二元件使得該第一導電材料及該第一接觸結構中之一者直接連接至該第二接觸結構。
現參看該等圖式,尤其圖1,將描述根據本發明之方法的一第一實施例。注意到圖式未按比例加以繪製但經繪製以說明本發明之概念。
基板10包括一裝置區域11,該裝置區域11具有接觸結構12。基板10可視所要應用而由若干材料製成,諸如半導體材料或絕緣材料。通常,基板10由矽或III-V材料製成。接觸結構12通常為對基板10中形成之裝置或電路結構(未圖示)形成接觸之金屬墊或互連結構。基板10亦可含有一與接觸結構12連接之積體電路,且基板10可為一僅含有接觸結構之模組。舉例而言,基板10可為一用於互連接合至基板10之結構、或產生(例如)一印刷電路板上與其他模組或電路結構之封裝連接或整合的模組。該模組可由諸如石英、陶瓷、BeO或AlN之絕緣材料製成。
位於表面13上用於接合至基板10的是三個分離之晶粒14-16。每一晶粒具有一基板部分19、一裝置區域18及接觸結構17。晶粒可先前藉由切塊等等與另一晶圓分離。晶粒14-16可視所要應用而由若干材料製成,諸如半導體材料。通常,基板由矽或III-V材料製成。接觸結構17通常為對裝置區域18中形成之裝置或電路結構(未圖示)形成接觸之金屬墊或互連結構。接觸結構12及17之尺寸各可變化。接觸結構尺寸之典型範圍在1與20微米之間,但尺寸及相對尺寸視對準容限、電路設計參數或其他因子而定可在此範圍外部。接觸結構之尺寸經繪製以說明發明性概念意在及並非意在限制。裝置區域18亦可含有一與接觸結構17連接之積體電路。可移除大體上所有基板部分19,保留一裝置層、一電路或一電路層。再者,晶粒14-16之基板可在接合至一所要厚度之後加以薄化。
晶粒14-16可與晶圓10使用相同技術或不同技術加以製造。晶粒14-16可各為相同或不同裝置或材料。晶粒14-16中之每一者具有形成於一裝置區域18中之導電結構17。結構17間隔開以在其間保留一間隙,或可為一具有一可延伸越過整個接觸結構之孔徑的單一結構。換言之,該孔徑可為一在接觸結構中之孔或可將接觸結構分為兩個。該間隙或孔徑之尺寸可藉由所接合之特定技術的光微影設計規則來確定。舉例而言,需要一最小橫向寬度之接觸結構12及17以隨後形成一具有互連金屬之可靠、低電阻電連接。
確定間隙或孔徑之最佳尺寸之一額外因子為接觸結構17與12之間的垂直間隔加上接觸結構17之厚度給出的距離與間隙或孔徑之尺寸的比率。此界定一將隨後形成於接觸結構17與12之間以使接觸結構17與12之間的一電互連成為可能之通道的縱橫比。如在申請案序號第09/505,283號(其內容以引用的方式併入本文中)中所描述,對於氧化物對氧化物直接接合,此垂直間隔通常為1-5微米或更少,或者如在申請案序號第10/359,608號中(其內容以引用的方式併入本文中)中所描述,對於金屬直接接合,此垂直間隔潛在地為零。此外,接觸結構17厚度通常為0.5至5微米。以視所使用之製程技術而為0.5至5之典型所要通道縱橫比,間隙的尺寸之一典型範圍對於氧化物對氧化物接合為0.3-20微米,或對於金屬直接接合為約0.1-10微米。金屬直接接合狀況描述於以下第四實施例中。
晶粒14-16一般與接觸結構12對準,使得結構17及間隙或孔徑定位於相應接觸結構12之上。接觸結構12之尺寸經選擇以允許晶粒14-16簡單地與位於接觸結構17之間的間隙對準。此尺寸視用於將晶粒14-16置放於基板10上之方法的對準精度而定。雖然市售之生產工具之進一步改良可能導致較小對準精度,但是使用此等工具之典型方法允許1-10微米之範圍的對準精度。間隙或孔徑之外部的接觸結構17之橫向長度較佳至少為由此對準精度給出之距離。
雖然對於每一晶粒14-16僅展示一組接觸結構17,但是應瞭解到接觸結構17之橫向長度通常遠小於每一晶粒14-16之橫向長度,使得每一晶粒具有幾個或極大數目的接觸結構17。舉例而言,接觸結構17可具有1-100微米之範圍之橫向長度且晶粒14-16可具有1-100 mm之範圍的橫向長度。晶粒14-16中接觸接觸17之數量具有104
及更高之數量級因此為實際上可實現的。
如在圖2A中展示,將晶粒14之表面20接合至基板10之表面13。此可藉由若干方法來完成,但較佳使用如在申請案序號第09/505,283號(其中形成500-2000 mJ/m2
之範圍之強度的接合,意即化學鍵)中所描述之接合方法在室溫下加以接合。圖2中說明晶粒14-16與基板10之接合。在接合之後薄化晶粒14-16之基板。薄化通常藉由拋光、研磨、蝕刻或此等三種技術之組合來達成以保留薄化基板21或完全移除基板部分19。圖2B說明基板部分19經完全或大體上完全移除之實例。再者,可在接合之前薄化晶粒14-16之基板。
在一實施例中,形成接觸12及17之材料為使用化學氣相沈積(CVD)或電漿增強CVD(PECVD)、濺鍍或藉由蒸鍍形成之沈積氧化物如SiO2
。亦可使用諸如氮化矽、非晶矽、聚合物、半導體或燒結材料之其他材料。再者,可在晶粒上形成一沈積氧化物層。
接著以直接接合技術來接合表面。較佳地,可使用任何類型之氧化物接合,尤其低或室溫氧化物接合。接合技術可包括平坦化及平滑表面13及20(表面20可在晶粒單一化之前加以製備)。此步驟可使用化學機械研磨法來完成。表面較佳經研磨至一約不多於0.5-1.5 nm且較佳不多於約0.5 nm之粗糙度且大體上平坦。表面粗糙度值通常經給出為均方根(RMS)值。再者,表面粗糙度可經給出為幾乎與RMS值相同之平均值。在研磨之後,清潔及乾燥表面以移除自研磨步驟之任何殘餘物。接著較佳以一溶液沖洗已研磨之表面。
在研磨之前亦可蝕刻接合表面以改良平坦度及/或表面粗糙度。該蝕刻可為有效的以藉由使用(例如)標準光微影技術之高光點之選擇性蝕刻來移除接合表面上的高光點。
接合技術可包括一活化製程。此活化製程可包括一蝕刻製程且較佳一極輕微蝕刻(VSE)製程。術語“VSE”意謂極輕微蝕刻之表面之均方根微粗糙度(RMS)保持在大約未蝕刻值,通常<0.5 nm且較佳在0.5 nm至1.5 nm的範圍。所移除之材料之最佳量視移除所使用的材料及方法而定。典型移除量自埃至幾奈米變化。亦可能移除更多材料。
術語"VSE"亦可指非所要有機污染物自表面之移除而無表面上故意沈積的材料如氧化矽之移除。非所要有機污染物之移除可因此減小RMS。
活化製程可為一以不同模式進行之電漿製程。實例為Ar或O電漿。反應性離子蝕刻(RIE)及電漿模式可加以使用,以及一感應耦合電漿模式(ICP)。濺鍍亦可加以使用。實例以RIE及電漿模式在下文中給出。
或者,可使用在VSE後製程期間以一所要終止物質活化且終止表面的VSE後處理。
表面可在活化之後以一較佳形成與表面原子層之臨時接合之所要物質加以終止,有效地終止原子層,直至此表面可與藉由相同或另一接合物質終止之表面在一起的隨後時間為止。當表面上之所要物質足夠接近以允許在低溫或室溫下表面之間的化學鍵結時,其將進一步較佳地彼此反應,該化學鍵結可藉由所反應之所要物質的擴散或解離及擴散遠離接合介面而增強。
終止製程可包括浸沒於一含有所選化學物之溶液中以產生導致以所要物質終止接合表面的表面反應。可使用基於N之溶液,諸如NH4
OH。浸沒較佳在活化製程之後立即加以執行。終止製程亦可由一電漿、RIE或其他乾式製程組成,藉以引入適當之氣體化學物以導致以所要物質終止表面。
可視需要沖洗表面接著將其乾燥。藉由對準兩個表面(若必要)且使其在一起來接合該兩個表面以形成一接合介面。藉由(例如)市售之接合裝備(未圖示)使該兩個表面在一起以起始接合介面。
接著,一自發性接合通常發生在接合介面之某位置處且傳播越過表面。隨著初始接合開始傳播,當表面足夠接近時,諸如導致化學鍵之聚合的化學反應在用於終止表面之物質之間發生。因此以一接合能量形成一強接合,該接合能量經定義為藉由插入一楔狀物而部分脫裂之接合介面處的分離表面中之一者的特殊表面能量。化學反應之副產物可遠離接合介面而擴散且通常在周圍材料中經吸收。副產物亦可轉化為擴散開且經吸收之其他副產物。共價及/或離子鍵之量可藉由導致接合強度之進一步增加的所轉化物質之移除而增加。
雖然在圖2A中三個晶粒經展示為接合至一單一基板10,但是亦可能將更大或更小數目之晶粒接合至基板10。再者,可能接合尺寸可與基板10之尺寸相比較之另一基板,其在圖2C中加以說明,其中一具有一裝置區域23之基板22接合至晶圓10,使得間隔開之導電結構24一般與導電結構12對準。基板22可在接合之前加以薄化或移除以便於對準。基板22可在接合之後加以薄化,且若需要則可移除大體上所有基板22。以下圖式中描述之程序亦可應用於圖2B及2C中展示之結構,但出於簡短之目的而省略單獨圖式。
如在圖3A中展示,一等形介電膜30形成於基板10之表面13及晶粒14-16之上。此膜可藉由(例如)CVD、PVD或PECVD而形成且較佳由諸如典型厚度範圍0.1至1.0微米之氧化矽之氧化物膜組成。再者,如在圖3B中展示,諸如一沈積或旋塗氧化物之填充材料或諸如聚醯亞胺或苯幷環丁烯之聚合物32可形成於晶粒14-16之上及/或其間。材料32可在製程中各點處加以形成。圖3B展示材料32在形成膜30及40之前加以形成的實例。視諸如所選材料或溫度考慮之許多因子而定,填充物、材料可在形成圖3A中展示之結構之後、在形成硬遮罩40(圖4)之後或在製程中各個其他點處加以形成。其他技術可用於形成填充材料。舉例而言,藉由(例如)使用以上描述之方法之連續或重複介電質形成步驟及化學機械研磨法可使用一介電填充物如氧化矽。或者,藉由連續或重複之金屬形成步驟及化學機械研磨法可使用例如藉由(例如)電鍍形成之金屬的導電填充物。具有一平坦表面可改良在表面上形成光阻及其他膜且在此等膜中形成孔徑,例如圖4中展示之孔徑41。
隨後,一硬遮罩40在介電膜30上加以形成且經圖案化以保留一般與結構17對準之孔徑41(圖4)。該硬遮罩較佳地包含一具有一對隨後蝕刻製程或用於蝕刻一通過薄化基板21及裝置區域18及11至接觸結構12之通道的製程之高蝕刻選擇性的材料。一硬遮罩之實例為鋁、鎢、鉑、鎳及鉬,且一蝕刻製程之一實例為一用以蝕刻一通過一薄化矽基板之通道之基於SF6
的反應性離子蝕刻及一用以蝕刻一通過裝置區域18及11至接觸結構12之後繼通道之基於CF4
的反應性離子蝕刻。硬遮罩40之厚度通常為0.1至1.0微米。孔徑40之寬度視包括薄化基板21之厚度及接觸結構17之間的間隙之若干因子而定,但通常為1至10微米。
孔徑41係使用硬遮罩40及介電膜30之標準光微影圖案化及蝕刻技術而加以形成。舉例而言,一孔徑可使用光微影在光阻中加以形成。此孔徑可經對準至晶粒14-16(或基板22)或基板10上之對準標記。光學或IR成像可用於該對準。接著,視硬遮罩材料而定以一適當濕式化學溶液或一乾式反應性離子蝕刻製程而蝕刻硬遮罩40,顯露孔徑中之介電膜30。接著以一類似於硬遮罩40之方式視介電膜材料而定以一適當濕式化學溶液或一乾式反應性離子蝕刻而蝕刻介電膜30。若硬遮罩為鋁,則用於一硬遮罩之濕式化學溶液之一實例為A型鋁蝕刻劑。若介電膜材料為氧化矽,則用於一介電膜之反應性離子蝕刻製程之一實例為基於CF4
的反應性離子蝕刻。許多其他濕式及乾式蝕刻可能用於此等及其他硬遮罩及介電膜材料。若孔徑經對準至晶粒14-16(或基板22),則孔徑41之寬度較佳寬於基板17之間的間隔,或者若孔徑經對準至下部基板20,則孔徑之寬度較佳寬於結構17之間的間隔加上用於將晶粒14-16(或基板22)置放於基板20上之方法的對準精度。
如在圖5中展示,使用硬遮罩40,蝕刻晶粒14-16之基板部分以形成通道50。該蝕刻延續通過鄰近接觸結構12及17之通常為介電材料之材料,以暴露導電結構17的背部及側面部分及接觸結構12之頂面。例如基於SF6
之一第一組氣體及狀態可用於蝕刻通過晶粒14-16之基板材料,且例如基於CF4
的一第二組氣體及狀態可用於蝕刻通過接觸結構17周圍之介電層。藉由適當地切換氣體及狀態可在一腔室中執行兩種蝕刻,而無需打破真空。用以暴露導電結構12之蝕刻展示於圖6A中。該蝕刻產生一延伸通過接觸結構17之間隙或孔徑至接觸結構12的通道部分60。
用以暴露接觸結構12及17之介電通道蝕刻較佳地具有一對接觸結構17之高蝕刻選擇性以避免對接觸結構17的不利蝕刻量。然而,可存在導致對接觸結構17之不利蝕刻量之介電通道蝕刻與導電結構的某些組合。舉例而言,當導電結構17足夠薄或當接觸結構12與17之間的垂直距離足夠大時,可發生不利效應。
一不利蝕刻量之一實例為藉由氧化矽介電質包圍之鋁接觸結構17與某些基於CF4
的反應性離子蝕刻(其中鋁導電結構蝕刻速率與氧化矽介電質蝕刻速率之比率可與接觸結構17之厚度與接觸結構12與17之間的氧化矽介電質之厚度的比率相比較或高於其)之某些組合。
在存在對接觸結構17之不利蝕刻量的彼等情形下,接觸結構17之厚度可經增加或一中間步驟經添加以保護接觸結構17不受介電通道蝕刻影響。一中間處理步驟可用於避免如下之不利蝕刻。當介電質蝕刻首先暴露上部接觸結構17之背部及側面部分時,在導致對接觸結構17之不利蝕刻的介電質蝕刻之繼續之前可在接觸結構17的顯露部分上選擇性地沈積諸如一金屬材料之硬遮罩。在一硬遮罩之選擇性沈積之後,可繼續介電質蝕刻而無對接觸結構17之不利蝕刻。一硬遮罩之一選擇性沈積之一實例為無電極鎳電鍍。舉例而言,此展示於圖6B中,其中在暴露接觸結構17之後且在任何顯著不利蝕刻發生之前停止蝕刻。接著使用(例如)無電極電鍍以例如鎳之保護性硬遮罩材料61塗覆接觸結構17。諸如鎳之材料可在接觸結構12及17之隨後連接中保留在裝置中。或者,若需要,則可在形成連接結構12及17之前移除材料61。
注意到保護性硬遮罩61亦可選擇性地沈積於硬遮罩40上。一實例為當硬遮罩40導電且保護性硬遮罩61之沈積以無電極電鍍加以完成時。此可有利於減小硬遮罩40之所需厚度。硬遮罩40上保護性硬遮罩材料61之沈積的一進一步優勢可為導致遮蔽接觸結構17之一部分免於通道60之各向異性蝕刻的通道50之孔徑之限制。圖7A詳細說明晶粒14-16中之一者以更清楚地說明隨後步驟。在遮罩40及接觸結構12與17及通道50及60之側壁上形成一等形絕緣膜70,部分地填充通道50及60。一適當絕緣膜之實例為氧化矽、氮化矽或聚對二甲苯基。可使用包括(但不限於)物理氣相沈積、化學氣相沈積及氣相沈積之若干典型沈積方法而形成絕緣膜。物理氣相沈積之一實例為濺鍍,化學氣相沈積之一實例為電漿增強化學氣相沈積,且氣相沈積之一實例為固體之汽化,接著是高溫分解且接著沈積。
可在藉由(例如)蝕刻之等形絕緣膜70的形成之前移除硬遮罩40或硬遮罩40及等形介電膜30。圖7B說明移除硬遮罩40之狀況。若用以移除硬遮罩40或硬遮罩40及膜30之蝕刻對藉由通道50及60暴露之材料為選擇性的,則此蝕刻可在無遮罩的狀況下加以完成。若此蝕刻對藉由通道50及60暴露之材料為非選擇性的,則在通道50及60中經受蝕刻之彼等材料可以一適當材料加以遮蔽。舉例而言,若硬遮罩40及接觸結構12及17皆為鋁,則通道可以一可容易地移除之旋塗黏性液體材料部分地加以填充至一深度,使得接觸結構12及17經覆蓋。通道可藉由首先選擇一將適當平坦化藉由硬遮罩40形成之表面之充分旋塗膜厚度而以一旋塗黏性液體材料部分地加以填充,通道50及60通過硬遮罩40加以形成。此膜厚度之應用接著將產生通道內部比通道外部厚得多的膜厚度。整個表面之一適當蝕刻接著將此材料自硬遮罩40的表面移除而保留通道50及60中之覆蓋接觸結構12及17的材料。一可容易地移除之旋塗材料及適當蝕刻之一實例分別為光阻及一O2電漿蝕刻。
各向異性蝕刻等形膜70以暴露接觸結構12及17而保留通道50及60之側壁上的膜70。較佳暴露結構17之背部表面以建立一用於增加接觸表面積之凸耳27,產生減小之接觸電阻。超過1微米之典型凸耳27較佳用於使接觸電阻最小化,但此距離將基於裝置及製程參數而變化。圖8A及8B分別描述在等形絕緣膜70之形成之前未移除及移除遮罩40之蝕刻的等形膜70。膜30及40皆可在形成層70之前經移除。在此狀況下,接著等形層70之蝕刻,可藉由(例如)氧化或沈積而在基板部分21(或部分21經完全移除之裝置區域18)上形成另一絕緣層。
作為等形膜70之替代,亦可在接觸結構12之頂面之暴露之前形成等形膜。舉例而言,如在圖8C、8D、8E及8F中分別展示,等形膜71可在蝕刻通過晶粒14-16之基板部分之後但在蝕刻入鄰近接觸結構17的材料之前加以形成,等形膜72可在蝕刻入鄰近接觸結構17之材料之後但在達到接觸結構17之前加以形成,等形膜73可在達到接觸結構17之後但在形成通道60之前加以形成,或等形膜74可在達到導電結構17且形成通道60的部分之後但在完成通道60且達到接觸結構12之前加以形成。可隨後各向異性地蝕刻等形膜71、72、73及74以在晶粒14-16之基板部分之通道部分50上形成隔離側壁。舉例而言,如在圖8G、8H、8I及8J中分別展示,等形膜71可隨後經各向異性地蝕刻以在晶粒14-16之基板部分之通道部分50上形成一隔離側壁,等形膜72可隨後經各向異性地蝕刻以在晶粒14-16的基板部分之通道部分50及包含鄰近接觸結構17之材料的通道50之上部上形成一隔離側壁,等形膜73可隨後經各向異性地蝕刻以在通道50之整個深度上形成一隔離側壁,且等形膜74可隨後經各向異性地蝕刻以在通道50的整個深度及通道60之上部上形成一隔離側壁。
如在圖8K中展示,作為藉由膜70、71、72、73或74之等形沈積及該等膜之隨後各向異性蝕刻而形成的側壁之替代,在晶粒14-16的基板部分藉由通道50而形成之後,可選擇性地在該通道中於該部分上形成一側壁75。側壁75可藉由一相對於鄰近接觸結構17之材料優先與基板部分反應之製程來加以形成。舉例而言,若晶粒14-16之基板部分為矽且鄰近接觸結構17之材料為氧化矽,則可在圖8K中所示的等形膜71之各向異性蝕刻之後使用一相對於氧化矽優先在矽上成核的介電質沈積製程,其中介電質沈積包含側壁75,其中側壁75結構上類似於通道50中之等形膜71。此處,側壁75在蝕刻通過晶粒14-16之基板部分之後但在蝕刻入鄰近接觸結構17的材料之前加以形成。
接觸結構17之一側表面亦可在各向異性蝕刻中經暴露以進一步增加表面積且降低接觸電阻。此亦展示於圖8A及8B中。接著通道50及60可以金屬進一步加以填充或完全填充。以金屬填充通道50及60之方法包括(但不限於)物理氣相沈積(PVD)、化學氣相沈積(CVD)或電鍍。電鍍通常用於比PVD或CVD更厚之膜的沈積且通常在一薄PVD或CVD晶種層的沈積之後。藉由PVD形成之膜之實例為濺鍍的鋁、鈀、鈦、鎢、鈦-鎢或銅,藉由CVD形成之膜之實例為鎢或銅,且藉由電鍍(其包括無電極電鍍)形成的膜之實例為鎳、金、鈀或銅。
圖9A展示一遮蔽電鍍之方法的一實例,藉以一金屬晶種層90首先沈積於該結構上,與接觸結構12及17電接觸,接著使用(例如)光阻而形成遮罩91。晶種層90可藉由如以上所描述之PVD、CVD或電鍍而加以沈積。使用遮罩91及與晶種層90之電接觸,金屬接觸92填充通道50及60。在圖9B中,展示一結構,其中遮罩40在等形絕緣膜70之形成之前經移除,且圖9C展示未使用晶種層的結構。接著,例如化學機械研磨法之研磨步驟可用於移除通道50及60外部之金屬接觸92的多餘部分。此研磨步驟亦可移除晶粒14-16之暴露側上的金屬晶種層90。其可進一步移除晶粒14-16之暴露側上的硬遮罩40。若硬遮罩如以上給出之鋁之狀況而電傳導,則硬遮罩40之移除可為較佳的,以將如此形成之金屬填充通道彼此電隔離。如圖10A及10B中展示,此研磨步驟可進一步移除等形介電膜30,從而在晶粒14-16之暴露側上產生一大體上平坦表面及平坦金屬結構100,其中因為在以金屬填充通道之前未使用晶種層,所以圖10B中之結構與圖10A中的結構有區別。
如圖10C中展示,作為以金屬填充通道50及60接著CMP之替代,通道50及60可以金屬93加襯,以介電質94加以填充接著CMP。藉由使用如以上所描述之PVD、電鍍或CVD中之至少一者的沈積以金屬93給通道50及60加襯。金屬93之厚度通常為0.01至0.2微米且可包括一鄰近等形絕緣膜70之障壁層以防止接觸結構12或17或裝置區域18或11的污染。障壁層之實例包括氮化鉭、氮化鎢及氮化鈦且可位於典型厚度為0.005至0.02微米之鈦黏著層之後。障壁層之一典型厚度為0.005至0.05微米。在93之一初始厚度已沈積之後,電鍍亦可用於等形地將93的厚度增加至一所要厚度。對於通道50而言,一典型增加之厚度為0.5至2.0微米,以具有足夠寬度之通道50為依據。介電質94之一實例為氧化矽且填充之一實例為使用電漿增強化學氣相沈積(PECVD)。此替代具有以下優勢:減少之金屬沈積及金屬CMP及所加襯之複合金屬、介電質填充的通道與晶粒14-16之周圍基板部分之間的一較佳熱膨脹係數(CTE)匹配之可能。
如以上描述及圖10D中展示,以金屬填充通道50及60或以金屬93給通道50及60加襯接著以介電質94填充的另一替代為以金屬97填充通道60或給通道60加襯以在接觸結構12與17之間形成一電互連而不接觸薄化基板21,且接著以介電質98填充通道50及60,接著CMP。金屬97可經形成以藉由無電極電鍍而互連接觸結構12及17而不接觸薄化基板21,該無電極電鍍藉由電鍍至優先電鍍互連接觸結構12及17之足夠厚度而優先在接觸結構12及17上電鍍。可經電鍍至足夠厚度之無電極電鍍的一實例為鎳無電極電鍍。如圖10D中展示,此替代具有以下優勢:剩餘基板晶粒14-16之通道50部分上無需一側壁60、71、72、73、74或75以將該電互連與該剩餘基板晶粒電隔離。
互連之接觸結構12及17之電互連可藉由如圖10E中所示且類似於圖10B中的描述蝕刻一通過介電質98至金屬97之通道51及以金屬46填充通道51或藉由如圖10F中所示且類似於圖10C之描述以導電材料52給通道51加襯及以介電質53填充而加以形成。圖10E及圖10F中之通道51經展示為連接至接觸結構12上之金屬97的部分。或者,通道51可連接接觸17或接觸結構12及17上金屬97之部分。
圖10A-10F之結構適用於包括(但不限於)用以支援引線接合或覆晶封裝之基於光微影的互連布線或凸塊下金屬化的隨後處理。此處理通常包括在暴露之薄化基板側21上形成一電絕緣材料以提供互連布線或凸塊下金屬化之電隔離。
圖11中展示之一實例具有在CMP之後在晶粒14-16上形成的諸如沈積或旋塗氧化物或聚合物的絕緣材料96,及形成於材料96上與金屬結構100接觸的互連布線或凸塊下金屬化95。如在圖3B中所示,在形成材料96之前可在晶粒14-16之間使用另一填充材料。金屬化可包括藉由絕緣層分離之幾個層(此處未圖示)以容納一高通道密度及/或一高布線複雜度。或者,若研磨步驟未移除等形介電膜70,則等形介電膜保留且可提供金屬化結構之足夠電隔離。
圖12中說明根據本發明之方法的一第二實施例。於晶粒14-16上形成一硬遮罩101而無任何插入介電層。硬遮罩101厚度之一典型範圍為0.1至1.0微米。硬遮罩101較佳地係由一具有一對隨後蝕刻製程或用於蝕刻一通過薄化基板21及裝置區域18及11至接觸結構12之通道的製程之高蝕刻選擇性的材料所組成。一硬遮罩之一實例為鋁、鎢、鉑、鎳或鉬,且一蝕刻製程之一實例為:一用以蝕刻一通過一薄化矽基板之通道之基於SF6
的反應性離子蝕刻;及一用以蝕刻一通過裝置區域18及11至接觸結構12之後繼通道之基於CF4
的反應性離子蝕刻。孔徑102形成於遮罩101中且該結構經如在第一實施例中之處理,以蝕刻通過晶粒基板及裝置區域以暴露結構12及17,而較佳暴露結構17之頂面以形成一凸耳(諸如圖8A及8B中展示之27)。使用遮罩103如圖7-9中所示而進行金屬化以形成金屬接觸104,以產生圖13中展示之結構。在CMP(圖14)之後,平坦化金屬105,且該結構適用於包括(但不限於)用以支持引線接合或覆晶封裝之基於光微影的互連布線或凸塊下金屬化的隨後處理,類似於圖11中所示之金屬化結構。此處理可包括晶粒14-16之暴露側上一電絕緣材料之形成,以提供在晶粒14-16之暴露側上布線的該互連布線或凸塊下金屬化的電隔離。為進一步輔助互連布線或凸塊下金屬化,可形成如在第一實施例中所描述之平坦化材料,例如介電質或金屬,或者聚醯亞胺或苯幷環丁烯材料,以在CMP處理之前或之後(例如)藉由填充晶粒、孔徑或槽之間的任何空間而平坦化該結構之表面。
本發明亦可與其他結構一起使用。舉例而言,無需一對接觸17,但一晶粒或晶圓中之一單一接觸可連接至與該晶粒或晶圓接合之基板中的一接觸。此說明於圖15中,其中與晶種90之金屬接觸107互連接觸結構12與108,結構108自結構12偏離。金屬接觸107之一部分(左側)自基板部分109之上部表面直接延伸至結構108上的晶種90,而金屬接觸107之另一部分(右側)自基板部分109之上部表面直接延伸至結構12上的晶種90。
本發明提供眾多優勢。一單一遮罩用於蝕刻通過一接合至一基板之晶粒或晶圓之背側以互連該晶粒或晶圓與該基板。該通道中無需光微影,其通常可為複雜的、有問題的且限制縮放比例。該蝕刻進行通過一接合介面。此外,可能暴露待互連之接觸之頂面,增加接觸的表面積且減小接觸之電阻。可互連不同技術裝置,最佳化裝置效能且避免與嘗試以一單一製程序列製造不同技術相關聯的問題。
一第三實施例展示於圖16A、16B及17中。基板110具有裝置區域111,裝置區域111具有接觸結構112。各具有一裝置區域118、基板部分121及接觸結構117之晶粒114-116接合至如圖16A所示之表面113上的基板110。在此實施例中,不存在覆蓋接觸結構112之材料。跟隨針對第一實施例或第二實施例描述之單一遮罩製程,產生圖16B及17中所示之結構。一通道50經蝕刻通過基板部分121及裝置區域118,暴露接觸結構117之背部表面上之一凸耳26。該蝕刻持續形成一通道60且暴露接觸結構112之一頂面。在具有或無一晶種層90之通道中形成接觸120,連接接觸結構112與117。如以上相對於圖3B所論述,填充材料可用於平坦化該裝置。接觸120亦可以以上圖10C-10F中展示之方式加以形成。再者,可如圖8C-8K所示形成膜70。
一第四實施例展示於圖18-19中。在此實施例中,不存在覆蓋接觸結構122或123之材料。晶粒114-116中包含例如金屬之導電材料的接觸結構123可在晶粒114-116的表面上延伸且包含例如金屬之導電材料的接觸結構122可在表面113上延伸。接觸結構123及接觸結構122可包含不同金屬。舉例而言,接觸結構123可包含銅、鎢、鎳或金中之一者,且接觸結構122可包含銅、鎢、鎳或金中之一不同者。接觸結構123或接觸結構122可進一步包含不同金屬,例如鎳、鈀及金之組合。接觸結構123及接觸結構122可進一步包含銅、鎢、鎳或金之合金或其他合金,例如氧化銦錫。此等金屬可藉由包括PVD、熱、電子束及電鍍之多種技術加以形成。
排除接觸結構123之晶粒114-116之表面的部分及排除接觸結構122之表面113之部分較佳為一非導電材料,例如氧化矽、氮化矽、氮氧化矽或可與半導體積體電路製造相容的備用隔離材料。如在申請案序號第10/359,608號中所描述,具有暴露之接觸結構123之晶粒114-116以一足以將晶粒114-116之表面中暴露的接觸結構123之一部分與表面113中暴露之接觸結構122的一部分對準且將晶粒114-116之表面之非導電材料部分與表面113的非導電材料部分對準之對準精度接合至具有暴露之接觸結構122的表面113。晶粒114-116之表面之非導電材料部分與表面113的非導電材料部分之間的接合較佳為在申請案序號第10/359,608號中描述之直接接合。亦可使用一備用類型之直接接合,例如描述於申請案序號第10/440,099號中。該直接接合之接合能量(較佳多於1 J/m2
)產生相抵接觸結構123之接觸結構122的一外部壓力,其產生接觸結構122與123之間的一電連接。因此較佳使用在低溫下產生一較高接合能量的直接接合,例如描述於以上之彼等接合,以產生最高內部壓力;然而,在低溫下產生一較低接合能量或需要較高溫度以獲得一較高接合能量之直接接合對於某些應用亦為可接受的。舉例而言,亦可使用需要中等溫度(例如小於400℃)或中等壓力(例如小於10 kg/cm2
)以達成高接合能量(例如大於1 J/m2
)之習知直接接合。
更詳言之,隨著包括金屬接合襯墊之晶圓表面在室溫接觸,相對晶圓表面之接觸非金屬部分在接觸點處開始形成一接合,且晶圓之間的吸引接合力隨著接觸化學鍵面積增加而增加。不存在金屬襯墊的情況下,晶圓將接合越過整個晶圓表面。根據本發明,金屬襯墊之存在雖然中斷相對晶圓之間的接合接縫,但是未阻止化學晶圓對晶圓接合。歸因於金屬接合襯墊之展性及延性,藉由非金屬區域中化晶學圓對晶圓接合所產生之壓力可產生一可使金屬襯墊上非平坦及/或粗糙區域變形的力,其導致金屬襯墊之改良之平坦度及/或粗糙度及金屬襯墊之間的密切接觸。藉由化學鍵產生之壓力足以消除針對此等金屬襯墊待施加以使其彼此密切接觸之外部壓力的需求。歸因於在配合介面處之金屬原子之互相擴散或自擴散,甚至在室溫下,密切接觸的金屬襯墊之間可形成一強金屬接合。此擴散經熱動地驅動以減少表面自由能量且對於通常具有高互相擴散及/或自擴散係數之金屬而經增強。此等高擴散係數為通常大多數藉由行動自由電子氣體確定之內聚能量的結果,該行動電子氣體未藉由擴散期間金屬離子之運動而受到干擾。
或者,晶粒114-116中接觸結構123可標稱地與晶粒114-116之表面共平面且接觸結構122可標稱地與表面113共平面。此可藉由形成一具有一具有金屬填充通道(諸如W、Ni、Au或Cu)之平坦表面的基板來完成。金屬填充通道可以在一諸如Cu、Al、Al-Cu(2%)或Al-Si(2%)合金層,或形成於Al或Al合金上之Cu層,厚度約為0.5微米的金屬晶種層上電鍍而加以形成。Pd可用作晶種層且亦可形成於Al或Al合金層之頂部。Ni、W、Au或Cu柱可形成於晶種層上。在電鍍之後,使用該等柱或光微影界定之圖案作為一遮罩及一金屬蝕刻而自柱之間的表面移除晶種層。接著於表面上形成一氧化物層。該氧化物層經受CMP以產生一具有氧化物及金屬區域之平坦表面。
接觸結構122及123可具有一大於晶粒114-116之非金屬表面部分及表面113之非金屬部分的表面粗糙度。舉例而言,晶粒114-116之表面及表面113較佳具有一小於1 nm且進一步較佳小於0.5 nm之均方根(RMS)表面粗糙度,而接觸結構122及123之表面較佳具有一小於2 nm且進一步較佳小於1 nm的RMS表面粗糙度。
歸因於例如晶粒114-116之暴露金屬表面或表面113上之自然氧化物或其他污染物(例如烴),由晶粒114-116之表面的非接觸結構123部分與表面113之非接觸結構122部分之間的接合產生之接觸結構122的相抵接觸結構123之內部壓力可不足以達成一接合或產生一具有一較佳低電阻的電連接。接觸結構123與122之間的一改良之接合或較佳較低電阻電連接可藉由移除接觸結構123或122上之自然氧化物而達成。舉例而言,稀氫氟酸可在使表面113與晶粒表面114-116接觸之前加以使用。此外,在移除自然氧化物之後直至使表面113與晶粒表面114-116接觸為止,表面113及晶粒114-116之表面可暴露至一惰性環境,例如氮或氬。或者,接觸結構123與122之間一改良之接合或較佳較低電阻電連接可在將晶粒114-116之表面之非接觸結構123部分與表面113的非接觸結構122部分接合之後藉由增加(例如加熱)接觸結構122及123之溫度而達成。溫度增加(例如若接觸結構123或122相對於接觸結構123及122周圍之非金屬材料具有一較高熱膨脹係數)可藉由自然氧化物或其他污染物之減少或藉由增加接觸結構123與122之間的內部壓力來產生較佳低電阻電連接,或藉由自然氧化物或其他污染物之減少及內部壓力之增加來產生較佳低電阻電連接。溫度增加亦可增加接觸結構如122與123之間的相互擴散以產生一較佳低電阻電連接。溫度增加因此可增強接觸結構123與122之間的金屬接合、金屬接觸、金屬互連或傳導。已達成小於1 ohm/μm2
之接觸電阻。舉例而言,對於直徑約5及10 μm且各約1 μm厚之兩個接觸結構,已獲得小於50莫姆之電阻。
若在晶粒114-116中或在表面113之下之層111中存在IC如矽IC,則溫度增加對於2小時較佳小於400℃且對於2小時進一步較佳小於350℃,以避免對IC、接觸結構或其他金屬結構的損壞。若接觸結構包含易受熱膨脹或內部壓力或可忽略之自然氧化物影響之導電材料如金,則導致接觸結構122與123之間之增強的金屬接合、金屬接觸、金屬互連或傳導之溫度增加可為極低的,例如對於10分鐘低為50℃。
若需要,則在較低接合後溫度下導致較高內部壓力的增加且此外在一較低壓力下可變形之接觸結構123及122的用途較佳為使達成接觸結構123與122之間金屬接合、金屬接觸、金屬互連或傳導之所要增強所需的接合後溫度增加最小化。舉例而言,作為接合後溫度增加之結果而產生之內部壓力視包含接觸結構123及122的金屬而定。舉例而言,具有高熱膨脹係數(CTE)值之金屬如銅、鎳及金導致一給定溫度下之更多膨脹。此外,具有一較高剪切模數之金屬如鎢及鎳針對一給定膨脹將產生更多應力。具有CTE與剪切模數之高乘積之金屬如銅、鎢及鎳將因此對於以增加的溫度產生內部壓力之增加為最有效的。此外,具有一低屈服應力之金屬如銅、鎳及金較佳為高純度的,例如高於99.9%,在較低應力下更易變形且因此在較低應力下導致接觸結構之間的改良之金屬接合、金屬接觸、金屬互連及傳導。包含具有CTE與剪切模數之高乘積或藉由屈服應力正規化之CTE與剪切模數的高乘積之金屬(例如銅、鎳及金)之接觸結構123及122因此較佳用於作為接合後溫度增加的內部壓力產生之結果展現接觸結構之間改良的金屬接合、金屬接觸、金屬互連及傳導的接觸結構123及122。
或者,接觸結構123可略低於晶粒114-116之表面或接觸結構122可略低於表面113。晶粒114-116之表面下與表面113之距離較佳少於20 nm且進一步較佳少於10 nm。隨後接合,接著溫度增加可增加如以上所描述之接觸結構122與123之間的內部壓力且導致接觸結構122與123之間的改良之金屬接合、金屬接觸、金屬互連或傳導。接觸結構122於表面113以下之微小距離及接觸結構123於晶粒114-116之表面以下的微小距離為在接觸結構之長度上的一平均距離。接觸結構之構形將包括等於、高於及低於該平均距離之位置。藉由最大高度與最低高度之差給出之接觸結構的總高度變化可大體上大於RMS變化。舉例而言,一具有為1 nm之RMS的接觸結構可具有10 nm之總高度變化。因此,雖然如以上所描述,接觸結構123可略低於晶粒114-116之表面且接觸結構122可略低於表面113,但是接觸結構122之一部分可在晶粒114-116的表面上延伸且接觸結構123之一部分可在表面113上延伸,從而在表面113之非金屬部分與晶粒114-116的非金屬部分之接合之後在接觸結構122與接觸結構123之間產生一機械連接。歸因於接觸結構122或接觸結構123上一不完全機械連接或自然氧化物或其他污染物,此機械連接可不產生接觸結構122與接觸結構123之間的一充分電連接。如以上所描述,隨後溫度增加可改良接觸結構122與123之間的金屬接合、金屬接觸、金屬互連、傳導。
或者,若接觸結構123之最高部分位於晶粒114-116之表面以下或接觸結構122的最高部分位於表面113以下且在接合之後接觸結構123與122之間不存在一機械接觸,則溫度增加可產生接觸結構123與122之間的機械接觸及/或所要電互連。
或者,接觸結構123可位於晶粒114-116之表面以下且接觸結構122可位於表面113以上,或接觸結構123可位於晶粒114-116之表面以上且接觸結構122可位於表面113以下。如在申請案序號第10/359,608號中所描述,接觸結構122於表面113以下之距離與接觸結構123於晶粒114、115或116之表面以下之距離的差(或反之亦然)可略為正。或者,接觸結構122於表面113以下之距離與接觸結構123於晶粒114、115或116之表面以下之距離的差(或反之亦然)可標稱地為零或略為負,且如以上所描述,一接合後溫度增加可改良接觸結構122與123之間的金屬接合、金屬接觸、金屬互連、傳導。
接觸結構123相對於晶粒114-116之表面之高度及接觸結構122相對於表面113之高度的高度可以一形成晶粒114-116之表面或表面113之研磨製程(例如化學機械研磨法(CMP))加以控制。該CMP製程通常具有包括(但不限於)研磨漿類型、研磨漿添加速率、研磨襯墊、研磨襯墊旋轉速率及研磨壓力之若干製程變數。該CMP製程進一步視包含表面113及晶粒114-116之表面之特殊非金屬及金屬材料、非金屬材料與金屬材料的相對研磨速率(類似研磨速率較佳,例如鎳及氧化矽)、接觸結構122及123之尺寸、間距及顆粒結構,及表面113或晶粒114-116之表面的非平坦度而定。此等製程參數之最佳化可用於控制接觸結構123相對於晶粒114-116之表面的高度及接觸結構122相對於表面113之高度的高度。亦可使用其他研磨技術,例如無研磨漿研磨法。
接觸結構123相對於晶粒114-116之表面之高度及接觸結構122相對於表面113之高度的高度亦可以晶粒114-116之表面上接觸結構123周圍的材料或表面113上接觸結構122周圍之材料之一輕微乾式蝕刻(例如用於包含例如氧化矽、氮化矽或氮氧化矽之某些介電材料的表面,使用CF4
及O2之混合物的電漿或反應性離子蝕刻)加以控制,較佳使得產生將顯著減少該等表面之間的接合能量之表面粗糙度的增加。或者,接觸結構123及接觸結構122之高度可藉由接觸結構123及122上一極薄金屬層之形成而加以控制。舉例而言,例如金之某些金屬之無電極電鍍可自限至一極薄層,例如大約5-50 nm。此方法可具有以極薄非氧化金屬(例如金或鎳)終止一氧化金屬以便於電連接之形成的額外優勢。
此外,接觸結構122可具有一大於或小於接觸結構123之橫向尺寸的橫向尺寸,使得在接合之後,一接觸結構123的周邊含於接觸結構122內,或一接觸結構122之周邊含於接觸結構123之周邊內。最小橫向尺寸較大或較小通常由晶粒114-116接合至表面113之對準精度的至少兩倍來確定。舉例而言,若晶粒114-116接合至表面之對準精度為一微米,則接觸結構122較佳大於接觸結構123至少兩微米以便使接觸結構123之周邊含於接觸結構122的周邊內。
可由接觸結構123周圍晶粒114-116之表面之部分與接觸結構122周圍表面113的部分之間的接合產生或藉由接合後溫度增加供應之接觸結構122相抵接觸結構123的最大內部壓力視晶粒114-116之表面之此部分與表面113之此部分的接合面積及接觸結構123相抵接觸結構122之面積的面積而定。歸因於由接觸結構123與122之間的橫向尺寸之差及晶粒114-116之表面與表面113之間的一接合對準不良產生之與表面113之非接觸結構122部分對準的接觸結構123之剩餘面積及與晶粒114-116之表面的非接觸結構123部分對準之接觸結構122的剩餘面積,此等兩個面積的和通常小於晶粒114-116相抵表面113之整個面積。可藉由接合產生或藉由接合後溫度增加供應之最大內部壓力可藉由晶粒114-116之表面的部分與表面113之部分之間的接合之斷裂強度乘以此接合之面積與接觸結構123相抵接觸結構122之面積的面積之比率來加以近似。舉例而言,若晶粒114-116之表面之部分及表面113的部分包含具有16,000 psi之斷裂強度的氧化矽且此等部分的對準部分之間的直接接合具有氧化矽之斷裂強度之一半(或8,000 psi)的斷裂強度,且接觸結構123及122在10微米之間距上為直徑為4微米之圓形,且對準較佳,則接觸結構123與122之間超過60,000 psi的最大內部壓力係可能的。此壓力通常顯著大於藉由接合後溫度增加所產生之壓力。舉例而言,若接觸結構123及122包含具有17 ppm之CTE及6,400,000 psi之剪切模數的銅且晶粒114-116之表面之部分及表面113之部分包含具有0.5的CTE之氧化矽,且接觸結構123與晶粒114-116之部分共平面且接觸結構122與表面113的部分共平面,在350℃之接合後溫度增加時期望接觸結構123與122之間一大約37,000 psi的應力。
接觸結構123與122通常對準不佳且具有相同橫向尺寸。此可導致接觸結構123之一部分與接觸結構122周圍表面113之一部分接觸或接觸結構122的一部分與結構123周圍晶粒114-116之表面之一部分接觸。若接觸結構123之一部分與表面113之此部分接觸且此外,若接觸結構122位於表面113以下,或者,若接觸結構122的一部分與晶粒114-116之表面的此部分接觸且此外,若接觸結構123位於晶粒114-116之表面以下,則接合後溫度增加可導致優先在接觸結構122與晶粒114-116的表面之此部分之間或接觸結構123與表面113的此部分之間的內部壓力增加,且導致將以其他方式獲得在接觸結構123與122之間於一給定接合後溫度增加處之內部壓力的減小。為避免接觸結構123與122之間之此內部壓力之增加,較佳若接觸結構123位於晶粒114-116的表面以下,則在接合之後接觸結構122之周邊在接觸結構123的周邊內一量(諸如兩倍對準容限)以容納接觸結構123與接觸結構122之尺寸及形狀之對準不良及不匹配,使得內部壓力增加將主要在接觸結構123與接觸結構122之間。或者,較佳若接觸結構122位於表面113以下,則在接合之後接觸結構123之周邊在接觸結構122的周邊內一量以容納接觸結構123及接觸結構122之尺寸及形狀之對準不良及不匹配,使得內部壓力增加將主要在接觸結構123與接觸結構122之間。此外或者,若接觸結構123位於晶粒114-116之表面以下且接觸結構122位於表面113以下,則藉由接觸結構CTE規格化之緊貼表面下的接觸結構在接合之後具有一在相對接觸結構之周邊內一量的周邊以容納接觸結構123及接觸結構122之尺寸及形狀的對準不良及不匹配,使得內部壓力增加將主要在接觸結構123與接觸結構122之間。
可在薄化晶粒114-116之基板之前或之後增加接觸結構123及接觸結構122的溫度以形成薄化之晶粒基板121。可在接合之後以包括(但不限於)熱、紅外及電感之多種類型的加熱增加接觸結構123及接觸結構122之溫度。熱學加熱之實例包括烘箱、帶式鍋爐及熱板。紅外加熱之一實例為快速熱退火。紅外加熱源可經篩選以具有較佳能量之光子優先加熱接觸結構123及122。舉例而言,若基板110、晶粒114-116基板、薄化晶粒基板121、裝置區域111或裝置區域118包含一半導體,例如矽,則紅外熱源可經篩選以防止具有超過半導體帶隙之能量的光子由該半導體吸收,從而導致相比接觸結構123或接觸結構122之溫度增加的半導體之減少的溫度增加。當接觸結構123或接觸結構122為磁性,例如包含鎳時,電感加熱之一實例為電感磁性共振。
如圖18中所示,複數個接觸結構123可接觸一單一接觸結構122而不覆蓋一單一接觸結構122之整體。或者,一單一接觸結構123可部分地或者以其整體接觸一單一接觸結構122,一單一接觸結構122可部分地或以其整體接觸一單一接觸結構123,或一單一接觸結構123可接觸複數個接觸結構122。
跟隨針對先前實施例描述之單一遮罩製程,當複數個接觸結構123接觸一單一接觸結構122而不覆蓋一單一接觸結構122之整體時,可生產圖19A中所示的結構,其中金屬晶種層90形成與接觸結構122及123之電互連。或者,金屬晶種層90可僅與接觸結構123接觸,尤其若接觸結構123覆蓋接觸結構122之整體。圖19A中所示之結構可進一步經處理以形成一類似於如先前在此實施例中描述且展示於19B中之圖18中表面113的表面,圖19B中接觸結構59類似於接觸結構122且平坦化材料58類似於表面113之非接觸122部分。具有暴露之接觸結構123之額外晶粒接著可與具有類似於具有暴露之接觸結構123的晶粒114-116與暴露之接觸結構122之接合的暴露之接觸59的表面接合且互連。圖19C說明具有接觸124而無孔徑或間隙之填充通道。
在此第四實施例中,無需一由金屬互連跟隨之通道蝕刻以在接觸結構123與122之間進行一電互連。然而,如圖19A中所示之由金屬互連跟隨之通道蝕刻可經期望為自晶粒114-116之暴露側的電接取作準備。一可需要此之應用之實例在於晶粒114-116之暴露側與一封裝、板或積體電路的用以在接觸結構123或122與此封裝、板或積體電路之間進行電連接的覆晶塊狀接合。亦存在出於此目的無需一通道之應用,例如在某些類型之凝視焦平面陣列之製造中。對於此等應用,進而如圖18中所示之包括(但不限於)以上所描述之衍生的方法及所製造之裝置可為足夠的。
一第五實施例展示於圖20A-20H中。在通道50之形成之前,此實施例類似於先前實施例,以下除外:具有一孔徑或重疊通道50之邊緣的晶粒17、108、117或123中接觸結構替換為無孔徑或重疊邊緣之接觸結構87。在此實施例中,具有基板部分89、裝置區域88之晶粒84-86中的接觸結構87接合至具有裝置區域81、基板80及接觸結構82之表面83。如圖20A中所示,接觸結構87定位於接觸結構82之上。晶粒84-86亦可接合至一具有類似於圖16及17中所示暴露之接觸結構之暴露的接觸結構112或類似於圖18及19中所示之接觸結構之接觸結構122的表面113。注意到接觸結構87可經接合而與說明於裝置86中之接觸結構82直接接觸。晶粒84-86亦可具有相同接觸結構組態。圖20A及20B經繪製以展示兩個接觸結構組態,出於簡要之目的兩個組態之間具有一切口。通常接合至一基板之晶粒中的每一者將具有相同接觸結構組態。若具有不同接觸結構之晶粒接合至相同基板,則可需要某些製程變化,諸如獨立地調節蝕刻參數或蝕刻通道。該等圖式經繪製以說明本發明,其中相同或不同基板存在於一基板上,且未必展示此等變化。
如在第一實施例中描述及在圖20B中所示,形成圖案化硬遮罩40及孔徑41。接著藉由順序地各向異性地蝕刻晶粒84-86中之剩餘基板部分89、晶粒84-86中之裝置區域88之部分至接觸結構87,接觸結構87建立側表面79,裝置區域88之剩餘部分至表面83(若需要),及裝置區域81(若需要)至接觸結構12來形成通道55。蝕刻接觸結構87除外,此等各向異性蝕刻可如在第一實施例中所描述而加以完成。考慮接觸結構87之各向異性蝕刻,可使用對硬遮罩40選擇性蝕刻導電結構87之RIE蝕刻。若硬遮罩40及導電結構87具有類似蝕刻速率,則硬遮罩40可形成為大體上厚於接觸結構87以使暴露之接觸結構87連同基板部分89、裝置區域88、接觸結構87及裝置區域81至接觸結構82(如需要)得以蝕刻而未完全蝕刻硬遮罩40。接觸結構87之蝕刻可大體上與晶粒84-86中之剩餘基板部分89及裝置區域88及裝置區域81之蝕刻不同。舉例而言,若剩餘基板部分89包含矽,且裝置區域88及81之蝕刻部分包含氧化矽,且接觸結構87包含Al,則非基於氯之RIE蝕刻可用於蝕刻剩餘基板部分89及裝置區域88及81,且基於氯之RIE蝕刻可用於蝕刻接觸結構87。
側壁76較佳在接觸結構87之蝕刻之前加以形成。特定言之,結構經各向異性地蝕刻通過基板部分89且可在達到裝置區域88之後停止,或繼續進入裝置區域88而在未達到接觸結構87時停止。接著如圖20C中所示,針對此等兩種狀況為分離之接觸結構及直接接合之接觸結構形成層76。層76可藉由在通道55中沈積一諸如氧化矽之絕緣層接著藉由(例如)各向異性蝕刻自通道55之底部移除層而加以形成。裝置區域88及接觸結構87之剩餘部分經蝕刻通過以暴露接觸結構82,如圖20D(左側)中所示,且裝置區域88之剩餘部分經蝕刻通過以暴露圖20D(右側)中的接觸87。
側壁形成、接觸結構82與87之間的電互連及通道加襯及/或填充之隨後步驟遵循先前描述之實施例中所描述,主要例外為:與接觸結構87之電互連限於一藉由各向異性地蝕刻通過接觸結構87所暴露之側表面79。一第二例外為側壁形成類似於圖8A或8B中側壁70,或圖8J中所示之側壁74所示之形成,其中該側壁在接觸結構17以下延伸且將抑制與接觸結構87之側表面79的電互連。圖20D(左側)詳細說明晶粒84-86中之一者以更清楚地說明未抑制與側表面79之電互連的側壁76之一實例。
圖20D中側壁形成之實例類似於先前在圖8H中給出之實例,其中側壁72在薄化晶粒基板21以下但在接觸結構17以上延伸。如圖20E中所示,通過接觸結構87或通過接觸結構87與接觸結構82之間的區域之通道55之蝕刻在接觸結構87以上亦可略微為各向同性的,以在接觸結構87之頂側上形成一極小自對準凸耳28以減小在接觸結構82與87之間隨後形成的電互連之互連電阻而未大體上增加通道55之橫截面。一類似於如圖8K中所示形成之側壁75之選擇性側壁77亦可在接觸結構87的蝕刻之前(圖20F,左側或右側)或在接觸結構87之蝕刻之後加以形成(圖20F,左側)。在接觸結構87之蝕刻之後一選擇性側壁77的形成懸於暴露之側表面79上且可使暴露之側表面79與接觸結構82之間的電互連之形成變複雜。此複雜化可藉由以一類似於電互連接觸結構12與17但未接觸圖10D中所示之薄化基板21之電互連97的形成之方式在暴露之側表面79與接觸結構87之間形成電互連99而加以避免。互連99可在接觸結構87上但在88或89中任何導電材料以下延伸。
在電互連99形成之後,類似於圖8A或8B中側壁70的覆蓋暴露至通道55之基板部分89的側壁76可如圖20G中所示而加以形成,其中假設一可與互連99厚度相比較的側壁厚度。或者,如圖20H中所示,可形成類似於圖8K中側壁75之選擇性側壁。接著可如在先前實施例中所描述以金屬填充或以金屬加襯且以介電質填充通道55之剩餘部分。
此等所得結構亦適用於包括(但不限於)如在先前實施例中所描述之用以支持引線接合或覆晶封裝之基於光微影的互連布線或凸塊下金屬化的隨後處理。注意到圖20C-20F中所示之結構亦可包括如晶粒86中所示經組態之接觸結構。
一第六實施例展示於圖21A-21E中,其中可移除類似於先前實施例中之19、21、89、109、121之整個晶粒基板部分127或大體上所有部分127,而保留一裝置層、一電路或一電路層。在此實施例中,基板130具有裝置區域131,裝置區域131具有接觸結構132。適當操作無需各具有一裝置區域138、接觸結構137及基板部分127之晶粒134-136。如在第五實施例中,接觸137展示為在晶粒134中具有一孔徑,且接觸137在晶粒135中為整體的且一孔徑可蝕刻通過該處。如在圖21A中所示,晶粒134-136接合至表面133上之基板130。藉由(例如)研磨及/或拋光而整體移除晶粒基板127,暴露如圖21B中所示之裝置區域138。歸因於缺少基板部分127,針對此實施例相比先前實施例大體減少且簡化蝕刻一通道以暴露接觸結構且在接觸結構之間形成一電互連隨後所需之步驟的數目。
舉例而言,在圖21C中,其中僅展示晶粒134-136中之一者,因為不存在需要蝕刻一通道所通過之基板部分127,所以簡化蝕刻一通道129以暴露接觸結構132及137的步驟。通道129可因此大體上淺於先前實施例中描述之通道,從而導致通道橫截面之一大體減少及通道密度的相應增加。在另一實施例中,在圖21D中,其中僅展示晶粒134-136中之一者,因為不存在需要一側壁以電隔離電互連128之基板部分127,所以簡化形成暴露之接觸結構132與137之間的一電互連128之步驟。圖21E說明包括以直接接觸接合之接觸結構的此實施例。注意到圖21E中展示之結構亦可包括如晶粒135中展示而經組態且類似於圖19C中之接觸結構124及122的接觸結構。
可移除整個晶粒基板部分之應用的實例包括某些絕緣體覆矽及III-VIC,其中該等IC之晶粒基板部分並非用於主動電晶體或其他IC裝置製造。
自第六實施例所得之結構亦適用於包括(但不限於)如在先前實施例中所描述之用以支持引線接合或覆晶封裝的基於光微影之互連布線或凸塊下金屬化的隨後處理。
圖21A-21E中所示之彼等結構之其他變化形式包括(但不限於)先前實施例中描述的彼等結構,例如:如圖10及圖14中所示之通道填充或通道加襯及填充;如圖15中所示之與一晶粒接觸結構邊緣之互連;將如圖17及圖18中所示暴露的晶粒與晶圓接觸結構,或如圖19中所示暴露之晶粒與晶圓接觸結構接合;如圖20中所示之晶粒接觸結構的一暴露之側表面之接觸亦為可能的。
本發明之一第七實施例展示於圖22A-L及圖23A-K中。注意到表面接觸結構組態係藉由晶粒146而加以說明。如以上所論述,所有晶粒在一基板中可具有相同或不同接觸結構組態且當不同接觸結構接合至相同基板時可需要某些製程變化。基板140可含有諸如藉由劃線道(scribe alley)38分離之144-146(藉由虛線指示)的晶粒。晶粒144-146中之每一者具有位於裝置區域148中之接觸結構147。出於解釋之簡易之目的,注意到該等接觸結構未按比例加以繪製。接觸結構147可為獨立部件或可由一具有一通過其之孔徑的部件組成。
接觸結構147可藉由金屬沈積及空浮或金屬沈積及蝕刻之習知方法加以形成。或者,接觸結構147可藉由圖案化及蝕刻通過一預先存在之導電層或一導電層之一孔徑內的圖案化及金屬沈積的一組合而加以形成。接觸結構147之形成較佳由類似於裝置區域148中接觸結構147以下之電隔離介電材料151之一平坦化層的沈積。一典型平坦化材料為藉由圖22A中層151指示之電漿增強化學氣相沈積而形成之氧化矽。當需要表面接觸時,如在裝置146中,層151可未經形成,未在基板140之某些區域中加以形成,或可稍後經移除。
一通道可在晶粒144-146中加以形成。該通道之蝕刻較佳在晶粒144-146沿劃線道38經單一化為個別晶粒之前以晶圓尺度加以完成,使得一晶圓上之所有晶粒上的所有通道可同時加以蝕刻。晶粒144-146可因此使所有其通道同時加以蝕刻,或者若晶粒144-146源自不同晶圓,則可在單獨時間加以蝕刻。該等通道較佳各向異性地加以蝕刻,以消耗最小量之裝置區域材料148及基板140。
晶粒144-146中之接觸結構亦可以一類似於先前在第五實施例中描述之方式的方式加以形成。舉例而言,如在圖22B中所示平坦化材料151經圖案化及蝕刻以形成一通過平坦化材料151至導電材料154的通道152,接著蝕刻一通過導電材料154之通道以形成具有一暴露之側表面153的接觸結構147(154),如圖22C所示接著進一步蝕刻通過裝置區域148且進入基板140以形成通道155。此蝕刻較佳為各向異性的以使通道155之橫向長度最小化。平坦化材料151亦可經圖案化及經蝕刻以形成暴露如圖22D所示之兩個凸耳160的通道156,暴露如圖22E所示之一凸耳160的通道157,或如圖22F所示未暴露凸耳的通道158。平坦化材料151之圖案化及蝕刻可具有一略大於藉由接觸結構147(或接觸結構154)形成之孔徑的區域,導致接觸結構147以下通道156之位置及橫向長度由接觸結構147(154)給出且接觸結構147(154)以上通道156的上部略寬於通道156之下部。如圖22D所示,顯露接觸結構147(154)之凸耳160及側表面153。或者,平坦化材料151之平坦化及蝕刻可重疊接觸結構147(154)之邊緣,導致通道157的位置及橫向長度之一部分由接觸結構147(154)給出且通道157之上部略寬於下部。如圖22E中所示,顯露接觸結構147及154之一凸耳160及接觸結構147(154)之一側表面153。作為圖22D及22E之替代,平坦化材料151之圖案化及蝕刻可不與接觸結構147(154)的任何部分重疊,導致如圖22F中所示,通道158之位置及橫向長度未由接觸結構147(154)給出且未顯露接觸結構147(154)之側表面153。注意到圖22E及22F中之接觸中之任一者無需具有一孔徑。通道156、157或158較佳經蝕刻至一足夠之深度,使得在將晶粒144-146接合至基板140之表面143之後用以形成薄化基板161之單一化晶粒144-146之基板140的隨後薄化針對如圖22C中所示形成之通道155及接觸結構147(154)顯露如圖22G中所示之通道156、157及/或158。
藉由接觸結構147界定或接觸結構154中之通道之蝕刻對一所要長度可為各向同性的,以如圖22C之通道155的圖22H中所示在接觸結構147(154)的背側上形成一自對準凸耳162以產生通道159,或如圖22D之通道156的圖22I中所示在接觸結構147(154)的背側上形成一自對準凸耳162以產生通道163。該各向同性蝕刻可包括接觸結構147(154)以下之裝置區域148及基板140,以顯露如圖22H或圖22I中所示之接觸結構147(154)的背側。各向同性蝕刻可藉由修正用於蝕刻通道155或通道156之蝕刻條件而達成。舉例而言,若用於蝕刻通道155或通道156之蝕刻條件包括低壓下的反應性離子蝕刻,則可在一較高壓力下使用一類似之反應性離子蝕刻。顯露接觸結構147之所要量之背側及形成自對準凸耳162所需要的壓力增加視包括平坦化材料151之厚度及通道156、157或158之深度的若干因子而定且可實驗地加以確定。或者,各向同性蝕刻可包括基板140但無裝置區域148,產生如圖22J中所展示之一自對準凸耳166及在接觸結構147(154)的背側上及通道164之上的裝置區域148之剩餘部分165。類似於如以上所描述之圖22H及22I,形成一自對準凸耳166之接觸結構147(154)的背側上及通道164之上之裝置區域148的剩餘部分165以在接觸結構147(154)以下各向同性蝕刻至一所要長度而產生。舉例而言,若剩餘部分165包含一絕緣體(例如氧化矽),且各向同性蝕刻之裝置區域148且基板140包含一半導體(例如矽),則可形成此結構。
在通道之形成之後,如在第一實施例中所描述可形成一非選擇性介電側壁170以將基板140與可在如圖22K中所示的通道中隨後形成之互連金屬電隔離。圖22K展示如圖22I中所示形成以產生具有凸耳172之通道171的通道163之實例。亦可形成一類似於第一實施例中所描述及圖22L中所示之側壁77之選擇性介電側壁173。在蝕刻通道之後,將晶粒144-146單一化(若需要)且將其接合至具有接觸結構142及裝置區域141之基板140的表面143。或者,可接合晶粒144-146而無單一化。舉例而言,可以一單一置放替代分離之晶粒置放將一整個晶圓或晶粒接合至基板,且替代由晶粒之間的間隔產生之非平坦表面而產生一標稱平坦表面。基板140亦可含有接觸結構但無裝置或一裝置區域。若通道如在圖22C中所描述且如圖23A-23B中所示而加以形成,則接著(例如)以背研磨、化學機械研磨法或蝕刻中之至少一者薄化基板140以保留薄化之基板晶粒161且顯露通道,例如通道155。接觸結構142可如圖23A中所示與接合表面共平面,或如圖23B中所示凹入至接合表面。如圖23A中所示與接合表面共平面之接觸結構142可藉由在基板140之表面上沈積例如銅電鍍或鎳電鍍的導電材料,接著在該導電材料上沈積一隔離材料而加以形成,接著一化學機械研磨法以形成接觸結構142及表面143。導電材料之研磨速率較佳可與該隔離材料之研磨速率相比較。導電材料之可比較之研磨速率可以導電材料、隔離材料、導電材料尺寸、導電材料之形狀及面積覆蓋及研磨參數(包括如在第四實施例中描述的研磨漿及襯墊)的適當選擇而加以獲得。
或者,如圖23B中所示凹入至接合表面之接觸結構142可藉由例如氧化矽之隔離材料的沈積,接著藉由選擇性研磨升高之特徵而平坦化該表面之隔離材料的化學機械研磨法,產生接觸結構142之頂部的一薄平坦化介電材料而加以形成。或者,如圖23B所示凹入至表面143之接觸結構142可藉由首先形成圖23A中所指示的平坦化表面143,接著在圖23A中所示之表面143上之一極薄隔離材料層之沈積或沈積及研磨而加以形成以形成圖23B中所示之表面143。凹入至接合表面之接觸結構142可具有(例如)藉由圖案化及蝕刻平坦化介電材料形成之如圖23C中所示之暴露的表面,以暴露具有通道63之接觸結構142。晶粒144-146之接合及薄化接著產生如圖23D中所示之接觸結構142的暴露之表面。例如圖23A及23D中所示之接觸結構142及147(154)之暴露較佳用以便於以下描述之接觸結構142與147(154)之間的隨後電互連。暴露之接觸結構142之橫向長度視通道63之相對尺寸及如圖22C中所示而蝕刻之通道155的橫向長度而定可小於、大於或等於通道155之橫向長度。舉例而言,當圖22C中之通道155之橫向長度小於圖23C中通道63的橫向長度時,暴露之接觸結構142之橫向長度大於如圖23D中所示的通道155之橫向長度。或者,可在接合、薄化及顯露通道(例如通道155)之後以如圖23E中所示之暴露的裝置區域141及148至接觸結構142之一各向同性蝕刻來使暴露之接觸結構142的長度變寬。或者,圖23C中所示之暴露之接觸結構142在對接觸結構142有其他方式之不利的接合製程期間可藉由一薄層加以保護。舉例而言,若接觸結構142包含鋁,則其可藉由暴露至用於達成室溫共價鍵之基於氨之溶液而受到折衷。此薄層之一實例為可藉由PEVCD形成之氧化矽。該薄層之化學機械研磨法亦可經完成以維持一所要表面143而未自接觸結構142移除該薄層。接著該薄層可在將晶粒144-146接合至基板140及薄化基板140之後加以移除,以顯露通道且形成薄化之晶粒基板161且因此較佳較薄,在0.05至0.5微米之範圍以在顯露通道之後簡化移除。
若薄化之晶粒基板161為非導電的,則顯露之接觸結構142與接觸結構147(154)可用重疊接觸結構142及接觸結構147(154)之導電材料的形成加以互連。或者,若薄化之晶粒基板161為導電的,例如若薄化之晶粒基板係由矽組成,則將薄化之晶粒基板161電隔離於使接觸結構142與接觸結構147(154)互連的導電材料之隔離側壁係較佳的。如在先前實施例中所描述之隔離非選擇性側壁(例如圖8A及8B中之側壁70)當暴露的接觸結構142與表面143共平面時,可在晶粒144-146之接合及晶粒144-146之隨後薄化之後加以形成,以保留側壁62之圖23F中所示的薄化之晶粒基板161,類似於圖23A中所示及如圖22H中所示形成之通道159,替代於如先前在如圖22I中所示形成之通道163的圖22K或圖22L中所示在接合之前之側壁形成。亦可使用類似於描述於第一實施例中之側壁但在晶粒基板之接合、薄化之後加以形成且顯露通道的隔離選擇性側壁。如在先前實施例中所描述,側壁形成較佳防止該薄化之晶粒基板與接觸結構142與接觸結構147(154)之間的電互連之間的非所要電傳導。
在接觸結構147(154)及接觸結構142經暴露的狀況下,且薄化之晶粒基板161上存在一側壁(若較佳),接觸結構147(154)與接觸結構142之間的電互連可藉由在接觸結構142及147(154)之暴露之表面至上形成導電材料而加以形成。一典型導電材料為金屬且典型金屬為鋁、銅、鎳及金。此等金屬可以在先前實施例中所描述之多種方法加以形成。此形成可導致如圖23G中所示的暴露之薄化晶粒基板161表面以導電材料52加以覆蓋。如圖23H所示,此覆蓋可以一自對準方式且未使用藉由研磨以導電材料52覆蓋之薄化之晶粒基板161表面的光微影圖案化及蝕刻而加以移除,直至導電材料52自薄化之晶粒基板161加以移除為止。當存在如圖22J所示具有自對準凸耳166之裝置區域148的剩餘部分165,暴露的接觸結構142與類似於圖23A所示之表面之表面143共平面時,在將晶粒144-146接合至基板140及基板140的薄化之後,一類似於圖23I中所示之結構的結構產生以顯露通道164且形成薄化之基板161。接著較佳以一各向異性蝕刻移除剩餘部分165以相抵接觸結構147(154)之背側再定位自對準凸耳,產生如圖23J所示之自對準凸耳167。
接著可形成導電材料以將接觸結構147與接觸結構142電互連而未形成與薄化之基板161的電互連(若較佳),類似於以上所描述及圖23F、23G及23H中所示。如先前所描述,互連金屬之形成可以電子束、熱、物理氣相沈積、化學氣相沈積及電鍍中之一者或組合而加以進行。所形成之互連金屬可為鈦、鎢、金、銅或鋁中之一者或組合。
在以導電材料電連接接觸結構142與147(154)之後,通道可以如在先前實施例中所描述之金屬化、介電質沈積及化學機械研磨法的組合加以填充及平坦化。在通道加以填充且平坦化之後,可如在先前實施例中所描述完成凸塊下金屬化、衝撞、切塊及覆晶封裝。注意到圖23F-J說明一表面接觸142但如圖23B所示此接觸亦可為凹入的。再者,具有表面接觸結構之晶粒可如圖23F-23J中所說明經接合且組態及/或連接。圖23K說明圖23H之狀況。
再者,此實施例(例如圖22C-22F、22H-L)中之通道可在單一化之前以導電材料168加以填充,使得當基板140之單一化部分經薄化時暴露導電材料。如以上所論述,用於電隔離之絕緣材料可按需要而在通道之側壁上加以形成。填充通道之晶粒(或晶圓)接著可與以下在第九實施例中所描述之晶粒(或晶圓)裝置區域148(或晶粒向下)之暴露的表面或與以下在第十實施例中所描述之暴露之裝置區域148表面(或晶粒向上)相對的表面接合。可如在第四實施例中所描述使用接觸結構147及在晶粒向下之圖23L之左手側中所示及如以下在第九實施例中更詳細描述,或在晶粒向上之圖23L的中間結構(其中導電材料168經連接至接觸結構142)及如以下在第十實施例中更詳細描述,或在晶粒向上之圖23L之右手側(其中接觸結構179類似於如在第四實施例中描述及以下在第十實施例中更詳細描述的接觸結構147之形成而加以形成)來執行接合。若需要,則介電材料169可在基板部分161上加以形成,且按需要加以研磨用於接合至基板140。通道可以包括(但不限於)多晶矽或例如鎢、鎳或銅之多種金屬的多種導電材料或導電材料之組合加以填充,該等材料藉由包括(但不限於)化學氣相沈積、物理氣相沈積及電鍍之多種方法加以沈積。導電材料可經選擇以便於與與低電阻率或高熱導率之導電材料接合之接觸結構的良好電接觸,且可藉由一(例如)藉由金屬有機氣相沈積或物理氣相沈積而沈積的例如氮化鈦或氮化鎢之障壁層與該通道外部的基板部分或通道側壁上的絕緣材料分離,若需要則防止導電材料擴散入通道外部的基板部分。舉例而言,當建置基於矽之IC(其中通道經蝕刻入矽)時,銅歸因於其低電阻率可為較佳的,但在一適當通道絕緣層(通常氧化矽)之間通常需要一適當障壁層(通常氮化鈦或氮化鎢)以避免銅擴散入矽。或者,若需要,則亦可使用例如鎢之其他金屬與一絕緣或障壁層。再者,若需要,則可使用如以上所論述研磨性質有利之材料如鎳,與一絕緣或障壁層。
一第八實施例說明於圖24A-B中。此實施例與第七實施例之區別之處在於晶粒144-146之相對側(例如薄化之晶粒基板161)在薄化該晶粒基板以顯露通道之後接合至基板140的表面143。此針對如圖22C中所示形成之通道155及如圖23A中所示形成之接觸結構142導致如圖24A中所示薄化的晶粒基板161接合至表面143及通道139暴露至表面143。例如矽之薄化之基板161可直接接合至基板140的表面143或例如氧化矽之介電質可在直接接合至基板140之表面143之前形成於薄化的基板161上。薄化之基板161之形成較佳在晶粒144-146單一化為個別晶粒之前以晶圓尺度加以完成,使得一晶圓上所有晶粒上的所有通道(例如在圖22C中所示的通道155)同時加以顯露。晶粒144-146可因此使其所有通道同時加以顯露,或者,若晶粒144-146源自不同晶圓,則可在單獨時間加以顯露。
若通道並非足夠深,則(例如)由圖22C中之基板140形成薄化之基板161可折衷機械完整性。舉例而言,對於200 mm直徑且包含矽之薄化之基板,深度小於大約0.1至0.3 mm的通道通常為足夠的。此通道深度(機械完整性在其以下受到折衷)對於具有較大直徑之薄化基板將較大且對於具有較小直徑之薄化基板將較小。此機械完整性折衷可藉由在如圖22C中所示形成之通道155及接觸結構147(154)之圖24B中展示的基板140之薄化之前將基板140的暴露之表面之相對側附著至一處理晶圓44而加以避免。處理晶圓44附著可以包括直接接合或黏著接合之多種接合方法加以完成。在將基板140之暴露之表面的相對側附著至一處理晶圓44及薄化基板140以形成薄化之基板161且顯露通道155之後,薄化的基板161可用作接合表面或介電質(例如氧化矽),可如以上所描述沈積為一接合層。在形成較佳接合表面之後,單一化晶粒144-146且將其接合至基板140之表面143,且移除處理晶圓44的單一化部分。單一化可以切塊或雕合中之至少一者加以完成。處理晶圓44之單一化部分之移除可以研磨、化學機械研磨法或蝕刻中的至少一者或組合加以完成。
在接合至處理晶圓44及薄化以形成薄化之基板161之前,接觸結構147(154)可如在第七實施例中所描述在晶粒144-146中加以形成。然而,用以改良導電材料52與接觸結構147之間的電連接電阻之在接觸結構147上一凸耳之形成係在第七實施例中所描述及圖23F及圖23G中所示之接觸結構147的相對側上。此凸耳可因此藉由在比接觸結構147中之孔徑更大之長度上在接觸結構147之上蝕刻裝置區域148以形成一類似於為圖22D中之通道156及接觸結構147所示之通道的通道而加以形成。
此外,在接合至處理晶圓44及薄化以形成薄化基板125之前,一側壁可形成於通道中。該側壁可類似於非選擇性側壁170及通道163之圖22K中所示之側壁為非選擇性的,或類似於選擇性側壁173及通道163的圖22L中所示之側壁為選擇性的。或者,一選擇性或非選擇性側壁可如先前實施例中所描述在接合晶粒144-146之後加以形成。
晶粒144-146接合至基板140可以與接合表面共平面或凹入至接合表面且經暴露或藉由如在第七實施例中所描述之一薄層保護的接觸結構142加以完成。在接合晶粒144-146,且移除處理晶圓44(若使用)之單一化部分,及移除薄保護層(若使用)之後,類似於在第七實施例中之圖23A或圖23D而暴露接觸結構142。接著導電材料經形成以電互連暴露之接觸結構142與147(154),例如類似於第七實施例中的圖23G及圖23H。此導電材料形成部分地或全部填充通道。若電互連暴露之接觸結構142與147(154)之導電材料部分地填充通道,則通道的剩餘部分可以在先前實施例中所描述之金屬化、介電質沈積及化學機械研磨法之組合而加以填充且平坦化。在通道加以填充且平坦化之後,可如在先前實施例中所描述完成凸塊下金屬化、衝撞、切塊及覆晶封裝。
關於接合及電互連類似於第四實施例且關於一通過晶粒之通道在接合之前的形成及在接合之後藉由薄化之暴露類似於第七實施例的第九實施例亦為可能的。此實施例如第七實施例中所描述而起始且持續通過晶粒114-116(或晶圓)之單一化及接合,以下除外:含有接觸結構123及122之接合表面如第四實施例中所描述而加以製備、接合及電互連。在接合之後,晶粒114-116經薄化以如在第七實施例中所描述暴露晶粒114-116中的通道且如在先前實施例中所描述以金屬加以填充。最終結構看起來類似於圖19A通道經填充且接觸結構123包含一孔徑之狀況。
在第九實施例之一變化形式中,接合前通道形成以在第七實施例中所描述之金屬填充而加以強化。舉例而言,晶粒114-116中之通道在通道156、157及158之圖22D、22E及22F中所示之接合之前加以形成。若晶粒基板及晶粒裝置區域之部分為導電的,則一電絕緣側壁較佳形成於蝕刻之晶粒側壁之導電部分上,例如如圖22L中所示的基板140及裝置區域148上通道163中的側壁173。此側壁亦可形成於整個側壁、圖22K中所示之側壁之整個非接觸部分上,或晶粒的底部。在通道已適當地與晶粒基板及裝置區域電隔離之後,該通道以一導電材料(例如金屬)加以填充,如圖10B中所示具有平坦化金屬結構100或具有導電及絕緣材料之組合如圖10C中所示具有金屬加襯或障壁層93及介電質94。通道填充(例如以金屬或金屬及介電質)可以先前實施例中所描述之若干技術加以完成。
對蝕刻及填充通過晶粒裝置區域及晶粒基板之一部分的通道之替代,在裝置之形成或晶粒裝置區域的完成之前,該等通道可經蝕刻或經蝕刻及填充入晶粒基板之僅一部分,或晶粒裝置區域的一部分及晶粒基板之一部分。舉例而言,如在圖25A中所示,通道172經蝕刻入晶粒基板140且通過晶粒裝置區域171之一部分,例如包含一半導體電晶體層及包含例如金屬之傳導材料(未圖示)及例如氧化矽或其他適當材料之絕緣材料之一多層互連結構的裝置區域之半導體部分,或其中裝置區域可駐留於基板中。若晶粒裝置區域171之部分及晶粒基板140包含一傳導材料,例如具有足夠低之電阻率的半導體材料(例如在典型CMOS晶圓製造中使用之矽),則一側壁較佳如先前在此實施例及先前實施例中所描述及如在先前實施例中所描述亦在通道172之底部上形成的選擇性側壁173之圖25B中所示而加以形成。此外,若圖25A中之結構包含矽,則一極薄(例如5-50 nm)之高品質選擇性二氧化矽側壁可熱生長,便於橫向尺寸大體上小於使得超過每平方公分100,000,000之極高通道區域密度成為可能的一微米之通道172得以製造。或者,一非選擇側壁可在通道172之側壁上加以形成而未如在先前實施例中描述在通道172之底部上形成。接著可以一通當障壁層給通道172加襯(若需要),且以導電材料174填充通道172而形成(例如)以上所描述之金屬填充的通道。通道172亦可以導電多晶矽加以填充。接觸結構123可形成為與如在圖25D中所示之填充通道接觸。
或者,進一步處理可在接觸結構123之形成之前在圖25C之結構上進行以完成晶粒裝置區域148的製造,接著是晶粒裝置區域148之上部中之接觸結構123的形成,如在圖25E中所示。舉例而言,一多層互連結構可形成為包含例如金屬之導電材料及(例如)類似於或與典型CMOS晶圓製造一致之絕緣材料。典型金屬包括銅及鋁且典型絕緣材料包括氧化矽及低k介電質。晶粒114-116中之接觸結構123可如在第四實施例中所描述及在圖25E中所示而加以形成。裝置區域148可包括傳導材料176之形成以將接觸結構123與金屬填充之通道174電互連。導電材料176在圖25E展示為在導電材料174與接觸結構123之間為垂直的但亦可包括橫向組件或全部由橫向組件組成,例如藉由例如CMOS晶圓製造之典型積體電路之製造中的層間金屬之布線加以提供。參見具有導電材料178之圖25F。
因此可自金屬填充之通道174至接觸結構123使用(例如)根據典型CMOS晶圓製造之積體電路的互連結構提供電連接,有效地最小化或消除修正互連結構之設計規則以達成電連接之需求,從而導致改良的縮放比例及現有製造能力之槓桿率。注意到雖然導電材料176可包括橫向組件或主要由橫向組件組成,但是通道172無需橫向組件。舉例而言,若通道172位於例如晶粒裝置區域171之晶粒裝置區域148之半導體部分中,且導電材料176由通常在積體電路之製造中使用之層間金屬組成,則通道172可自導電材料176垂直地加以安置且可以本質上與導電材料176之製造無關的設計規則加以製造,以下除外:導電材料176與金屬填充之通道174電接觸。此外,此實例中通道172大體上比先前在此實施例中所描述之通道短,其中,舉例而言,通道155延伸通過晶粒裝置區域148之整個部分。較短之通道172進一步便於使通道172之橫向尺寸較小,例如大體上小於一微米,使得例如超過每平方公分100,000,000之極高區域密度的通道得以製造,從而導致改良之縮放比例。注意到當需要將導電材料176與其他表面接觸隔離時,在裝置146中包括一絕緣側壁膜177及絕緣表面膜180。
在此變化形式中,在接合之後,接合後薄化顯露一以金屬填充之通道而非一未以金屬填充的通道,例如如在圖23L之左手側中所示。在任一變化形式中,可如在第六實施例中所描述整體移除晶粒基板部分。另外,在任一變化形式中,接合至一無裝置區域但具有如在第四實施例中所描述製備之接觸結構的基板亦為可能的,例如作為對一晶片之替換以在球狀刪格陣列IC封裝中封裝插入式基板。
此外,在任一變化形式中,所暴露之表面可包含以金屬填充之通道。若需要,則此表面可經通當地製備用於使用用以平坦化第一實施例中所描述之表面的填充材料與第十實施例中所描述之通道顯露及接觸結構形成的組合而與在第四實施例中所描述之電互連接合。接著可將來自具有暴露之接觸結構之相同或不同晶圓的額外晶粒接合至如在第四實施例中所描述之具有顯露之金屬填充通道的接合後薄化表面。或者,為覆晶封裝作準備而形成之凸塊下金屬化可如在先前實施例中所描述而加以實施。此說明於圖23M及23N中,其中一第二晶粒接合至第一晶粒。在使用以上及以下所描述之組態將導電材料及/或一晶粒之接觸接合至另一晶粒中,許多組合係可能的。圖23M展示三個實例,其中晶粒181使用接觸結構179將其導電材料168連接至下部晶粒之導電材料168,晶粒182具有連接至下部晶粒之接觸147及導電材料168的接觸147(154),且晶粒183具有連接至下部晶粒之接觸147及導電材料168的接觸147及導電材料168。
在圖23N中,左手結構具有以晶粒向下組態接合之兩個晶粒。中間結構具有一具有接合至一諸如具有接觸結構142之插入式基板之基板149的接觸結構147(154)。接觸結構147(154)與導電材料168經由在接合之後形成之導電材料187加以連接。右手結構具有將基板149中之導電材料168與接觸結構154連接之導電材料187。
如以上所提及,根據本發明之方法可應用於晶圓對晶圓接合。圖23O說明具有多個接觸結構147及導電材料168之上部基板140,類似於圖23L之左手側上的晶粒,以接觸結構142進行個別連接而接合至下部基板140。晶粒或另一晶圓可使用以上及以下所描述之方法及組態接合至晶圓149。任何所要數目之晶圓及晶粒可經接合及互連在一起。
關於接合及電互連類似於第九實施例且關於晶粒144-146接合表面之定向及一處理晶圓之可選使用類似於第八實施例的第十實施例亦為可能的,且展示於圖26A中。此實施例如在第九實施例中所描述而起始,其中通道經蝕刻、隔離(若需要)且以導電材料加以填充,例如如圖25C中所示。如以上所提及,通道可以包括(但不限於)多晶矽或例如鎢或銅之多種金屬的多種導電材料而加以填充,該等材料藉由包括(但不限於)化學氣相沈積及電鍍之多種方法按需要使用絕緣及障壁層而加以沈積。例如圖25F中之140的晶粒(或晶圓)基板接著經薄化以顯露例如圖25F中之174的以導電材料填充之通道,一處理晶圓之可選使用如在第八實施例中所描述。通道之顯露可以背研磨、CMP與蝕刻之組合加以完成。該顯露較佳產生一平坦表面但或者可歸因於基板之CMP或蝕刻之選擇性而產生非平坦表面。舉例而言,矽可在CMP製程期間以一低於銅之速率加以移除,產生如在第四實施例中所描述之凹入或凹陷至矽基板表面以下的導電通道。或者,可顯露通道或所顯露通道可以一選擇性蝕刻加以蝕刻,該選擇性蝕刻對導電通道優先蝕刻基板,從而產生在矽基板表面之上延伸之導電通道。舉例而言,矽可以一基於SF6
之反應性離子蝕刻對銅或鎢填充之通道優先加以蝕刻。若導電填充之通道之顯露產生如在第四實施例中所描述的適當可接合表面,則晶粒可如在第八實施例中所描述而經單一化及接合。
若導電填充之通道之顯露未產生如在第四實施例中所描述的適當可接合表面,則接觸結構可經形成以形成如在第四實施例中所描述之適當可接合表面。舉例而言,若暴露之導電通道填充在接合表面以下,則接觸結構179可在導電材料174上以一類似於第四實施例中所描述之方式的方式加以形成。此形成可包括接觸結構及例如氧化矽之介電質的沈積,接著研磨,以產生一適當平坦且電絕緣的接合表面,接觸結構除外。此說明於具有與導電材料174接觸而形成之接觸結構179且具有諸如PECVD氧化矽之介電膜169的圖26B中。
或者,該製程可包括具有或無介電質之接觸結構之沈積及研磨,以產生一與接觸結構適當共平面且包含例如圖25F中的基板140之基板的接合表面。此外或者,若暴露之導電通道填充在接合表面之上,則接觸結構可在導電材料174上以一類似於第四實施例中所描述之方式的方式加以形成。此形成可包括接觸結構及例如氧化矽之介電質之沈積及研磨,以產生一適當平坦且電絕緣的接合表面,接觸結構179除外。接觸結構179可經形成為具有一可與導電材料174相比較、小於或大於導電材料174之橫向尺寸。
該晶粒接著如在第八實施例中所描述而加以單一化及接合。因此晶粒144-146接合至具有如在第九實施例中所描述而形成及填充之接合前通道的基板140,且若需要,則如在第四實施例中所描述而製備、接合且電互連含有接觸結構的接合表面。在將晶粒144-146接合至基板140之後,晶粒144-146無需與接觸結構142電互連且晶粒114-116之暴露表面針對在先前實施例中所描述的為覆晶封裝作準備之凸塊下金屬化為可達到的。
在實施例十中,可形成通過整個裝置區域148或通過如在實施例九中所描述之裝置區域148之一半導體部分的通道。如在第九實施例中,在裝置區域148之一半導體區域中形成通道藉由在裝置區域得以完成之前形成通道而避免較深且較寬的通道,其改良裝置密度且減小作為通道形成之結果消耗之半導體的部分,從而導致改良之縮放比例。此外,可如在第六實施例中所描述整體移除晶粒基板部分。此外,暴露之表面可包含接觸結構。此表面可經適當地製備用於使用如在第一實施例中所描述用以平坦化該表面之填充材料(若需要)與在第四實施例中所描述之電互連接合。接著可將來自具有暴露之金屬填充通道的相同或不同晶圓之額外晶粒接合至如在第四實施例中所描述之具有通當接觸結構之接合後表面。或者,為覆晶封裝作準備而形成之凸塊下金屬化可如在先前實施例中所描述而加以實施。再者,亦可進行實施例十以類似於圖23M堆疊多個晶粒或類似於圖23N以晶圓對晶圓格式進行。
本發明之所要特徵傳達至垂直堆疊及互連組態。舉例而言,可IC側向下或IC側向上接合晶粒。另外,作為晶粒對晶圓格式之替代,上部晶圓(IC側向上或者向下)接合至IC側向上之下部晶圓的晶圓對晶圓格式亦為可能的。此外,亦可使用此等晶粒對晶圓及晶圓對晶圓格式,使用無需基板具有IC功能性之基板製造IC。舉例而言,使用絕緣體覆矽(SOI)基板或例如III/V材料、SiC及藍寶石之非矽基板製造之IC可無需具有IC功能性之基板的存在。在此等狀況下,基板未用於電晶體製造之整個部分可經移除,以使形成垂直電互連所需之通道蝕刻最小化。
雖然基板經展示包含一裝置區域,但是無裝置區域但具有接觸結構之基板亦為可能的,例如作為對一晶片之替換以在球狀刪格陣列IC封裝中封裝插入式基板。再者,晶粒展示為具有裝置,但不具有裝置但具有接觸結構之其他晶粒或元件可使用根據本發明之方法接合至基板。
依據以上教示,本發明之眾多修正及變化係可能的。因此應瞭解到在附加申請專利範圍之範疇內,本發明可以除本文特定描述之外的其他方式加以實施。
10...基板/晶圓
11...裝置區域
12...接觸結構
13...表面
14-16...晶粒
17...接觸結構
18...裝置區域
19...基板部分
20...下部基板/表面
21...薄化基板
22...基板
23...裝置區域
24...導電結構
26-28...凸耳
30...等形介電膜
32...聚合物/材料
38...劃線道
40...膜/硬遮罩
41...孔徑
44...處理晶圓
50...通道
51...通道
52...導電材料
53...介電質
55...通道
58...平坦化材料
59...接觸結構
60...通道
61...保護性硬遮罩材料/保護性硬遮罩
70...等形膜/等形層
71...等形膜
72...等形膜
73...等形膜
74...等形膜
75...側壁
76...側壁
77...選擇性側壁
79...側表面
80...基板
81...裝置區域
82...接觸結構
83...表面
84-86...晶粒
87...接觸結構
88...裝置區域
89...基板部分
90...晶種層
91...遮罩
92...金屬接觸
93...金屬
94...介電質
95...凸塊下金屬化
96...絕緣材料
97...金屬/電互連
98...介電質
99...電互連
100...金屬結構
101...硬遮罩
102...孔徑
103...遮罩
104...金屬接觸
105...金屬
107...金屬接觸
108...結構
109...基板部分
110...基板
111...裝置區域
112...接觸結構
113...表面
114-116...晶粒表面
117...接觸結構
118...裝置區域
120...接觸
121...基板部分
122...接觸結構
123...接觸結構
124...接觸
125...薄化基板
127...基板部分
128...電互連
129...通道
130...基板
131...裝置區域
132...接觸結構
133...表面
134-136...晶粒
137...接觸結構
138...裝置區域
139...通道
140...基板
141...裝置區域
142...接觸結構
143...表面
144-146...晶粒
147...接觸結構
148...裝置區域
149...晶圓/基板
151...平坦化材料
152...通道
153...側表面
154...接觸結構/導電材料
155...通道
156...通道
157...通道
158...通道
159...通道
160...凸耳
161...晶粒基板
162...凸耳
163...通道
164...通道
165...剩餘部分
166...自對準凸耳
167...自對準凸耳
168...導電材料
169...介電材料
170...側壁
171...晶粒裝置區域/通道
172...凸耳/通道
173...側壁
174...導電材料/通道
176...導電材料
177...絕緣側壁膜
178...導電材料
179...接觸結構
180...絕緣表面膜
181...晶粒
182...晶粒
183...晶粒
187...導電材料
圖1為展示面向下接合至一面向上晶圓之晶粒的圖;圖2A為接合至一基板之晶粒之圖;圖2B為接合至一基板之晶粒的圖,該晶粒之基板的一部分經移除;圖2C為接合至另一基板之基板的圖;圖3A為展示圖2A之結構上一介電膜及遮罩層之形成的圖;圖3B為展示在形成一平坦化材料之後形成一介電膜及遮罩層的圖;圖4為展示圖3A及3B之介電膜及遮罩層中形成之孔徑的圖;圖5為展示使用如在圖4中所形成之孔徑的晶粒之蝕刻的圖;圖6A為展示用以暴露晶粒及晶圓中之接觸結構之進一步蝕刻的圖;圖6B為包括形成一硬遮罩之製程修正的圖;圖7A為在一等形絕緣側壁層形成之後圖6A之結構之一部分的圖;圖7B為移除硬遮罩之實施例的變化形式;圖8A為展示一等形絕緣側壁層之各向異性蝕刻的圖;圖8B為移除硬遮罩之實施例的變化形式;圖8C-8F說明在接合結構中形成一等形膜的變化形式;圖8G-8J分別說明在蝕刻等形膜之後圖8C-8J中所示的結構;圖8K說明在接合結構中形成一側壁膜之一替代性方式;圖9A為展示形成一包含一金屬晶種層及一金屬填充之金屬接觸的圖;圖9B為移除硬遮罩之實施例的變化形式;圖9C為未形成晶種層之實施例的變化形式;圖10A為在化學機械研磨之後圖9A或9B之結構的圖;圖10B為在化學機械研磨之後圖9C之結構的圖;圖10C-10F為說明填充接合結構中之一模穴之替代性方法的圖;圖11為說明圖10A之結構之金屬化的圖;圖12為使用一無插入介電層之遮罩層之第二實施例的圖;圖13為展示在第二實施例中形成一金屬接觸的圖;圖14為展示在化學機械研磨之後圖13之結構的圖;圖15為說明本發明之另一實施例的圖;圖16A為說明一接觸結構位於裝置中之一者之表面中的實施例的圖;圖16B為在進一步處理之後圖16A之結構的圖;圖17為展示一使用根據本發明之方法以圖16A及16B中展示之結構生產的裝置之圖;圖18為本發明之另一實施例的圖;圖19A為展示一使用根據本發明之方法以圖18中展示之結構生產的裝置之圖;圖19B說明具有在圖19A之結構上形成之平坦化材料及接觸的結構;圖19C說明類似於圖19A之結構但無孔徑之直接接合的接觸;圖20A-20H說明具有側壁膜之第五實施例;圖21A-21E說明基板大體上經完全移除之第六實施例;圖22A-22L說明通道在晶粒單一化之前形成之第七實施例;圖23A-23K說明晶粒頂部向下加以安裝之第八實施例;圖23L說明接合一具有一頂部向下及頂部向上組態之填充通道的結構;圖23M及23N說明接合一第二水平晶粒;圖23O說明晶圓對晶圓接合;圖24A及24B說明晶粒頂部向上加以安裝之第八實施例的變化形式;圖25A-25F說明在接合之前具有填充通道的第九實施例;及圖26A及26B說明具有填充通道及表面接觸之第十實施例。
70...等形膜
90...晶種層
110...基板
120...接觸
121...基板部分
122...接觸結構
123...接觸結構
Claims (84)
- 一種三維積體電路裝置之結構,其包含:一具有一第一基板之第一元件,一設置於該第一基板上之第一絕緣層,其包含矽以及氧和氮中之至少一者,以及一設置於該第一絕緣層中之第一接觸結構;一具有一第二基板之第二元件,一設置於該第二基板上之第二絕緣層,其包含矽以及氧和氮中之至少一者,以及一設置於該第二絕緣層中之第二接觸結構;該第一絕緣層直接接合至該第二絕緣層;該第一接觸結構直接連接至該第二接觸結構;及一設置於一通道(via)中之互連結構且連接至該第一接觸結構,該第一接觸結構及該第二接觸結構之每一者具有一拋光表面(polished surface);及該等拋光表面係直接地彼此接觸。
- 如請求項1之結構,其包含該第一接觸結構係實質上與該第一絕緣層之一表面共平面。
- 如請求項2之結構,其包含該第二接觸結構係實質上與該第二絕緣層之一表面共平面。
- 如請求項1之結構,其中該第一接觸結構包含銅、鎢、鎳、及金中之一者。
- 如請求項1之結構,其中該第一接觸結構及該第二接觸結構係表面上為相同寬度;及該第一接觸結構之一上表面之一部分係與該第二絕緣層接觸。
- 如請求項1之結構,其中該第一接觸結構與該第二接觸結構間之一接觸電阻係小於1ohm/μm2 。
- 如請求項1之結構,其中該第一接觸結構與該第二接觸結構之每一者包含一熱膨脹金屬接觸結構。
- 如請求項1之結構,其中該第一接觸結構與該第二接觸結構之每一者包含銅、鎢、鎳、及金中之一者。
- 如請求項1之結構,其中該第一接觸結構與該第二接觸結構之每一者包含包含一具有一表面之金屬接觸結構,其中一自然氧化物係自該表面移除。
- 如請求項1之結構,其包含一連接至該第一接觸結構之第三接觸結構且設置於該第一絕緣層中之一通道中。
- 如請求項10之結構,其中該第一接觸結構具有一平面表面,其連接至該第三接觸結構。
- 如請求項10之結構,其中該第三結構包含一形成於該第一絕緣層上之第一金屬層以及形成於該第一金屬層上之一第二金屬層。
- 如請求項10之結構,其中該第一元件係使用一直接接合製程而接合至該第二元件。
- 如請求項1之結構,其中該第一絕緣層及該第二絕緣層係直接接合。
- 如請求項1之結構,其中該第一元件包含一半導體基板。
- 如請求項1之結構,其中該第二元件包含一半導體基板。
- 一種三維積體電路裝置之結構,其包含:一第一元件,其具有一第一基板、一包含一第一絕緣區域及設置於該第一基板上之第一上層及一第一導電區域;一第二元件,其具有一第二基板、一包含一第二絕緣區域及設置於該第二基板上之第二上層及一第二導電區域;該第一絕緣區域直接接合至該第二絕緣區域;該第一導電區域直接連接至該第二導電區域;及該第一導電區域及該第二導電區域中之至少一者包含一熱膨脹金屬接觸結構,該第一導電區域及該第二導電區域之每一者具有一拋光表面;及該等拋光表面係直接地彼此接觸。
- 如請求項17之結構,其中該第一絕緣區域及該第二絕緣區域進一步包含矽以及氧和氮中之至少一者。
- 如請求項17之結構,其中該第一導電區域及該第二導電區域中之至少一者進一步包含一接觸結構。
- 如請求項19之結構,其中該接觸結構進一步包含多個接觸結構。
- 如請求項20之結構,其進一步包含在該多個接觸結構中之至少二者之間之電隔離。
- 如請求項17之結構,其中該第一基板及該第二基板中之至少一者進一步包含一半導體裝置。
- 如請求項17之結構,其中該第一基板及該第二基板中之至少一者進一步包含一半導體裝置之一部分。
- 如請求項17之結構,其中該第一導電區域係實質上與該第一絕緣區域之一表面共平面。
- 如請求項24之結構,其中該第二導電區域係實質上與該第二絕緣區域之一表面共平面。
- 如請求項17之結構,其中該第一導電區域包含銅、鎢、鎳、及金中之一者。
- 如請求項17之結構,其中該第一導電區域及該第二導電區域係表面上為相同寬度;及該第一導電區域之一上表面之一部分係與該第二絕緣區域接觸。
- 如請求項17之結構,其中該第一導電區域與該第二導電區域間之一接觸電阻係小於1ohm/μm2 。
- 如請求項17之結構,其中該第一導電區域與該第二導電區域之每一者包含一熱膨脹金屬接觸結構。
- 如請求項29之結構,其中該第一導電區域與該第二導電區域包含銅、鎢、鎳、及金中之一者。
- 如請求項17之結構,其中該第一導電區域與該第二導電區域之每一者包含一具有一表面之金屬接觸結構,其中一自然氧化物係自該表面移除。
- 如請求項17之結構,其包含一導電組件,其連接至該第一導電區域且設置於該第一絕緣區域之一通道中。
- 如請求項32之結構,其中該第一導電區域具有一平面表面,其連接至該導電組件。
- 如請求項32之結構,其中該導電組件包含一形成於該第一絕緣區域上之第一金屬層以及一形成於該第一金屬層上之第二金屬層。
- 如請求項32之結構,其中該第一元件具有第一及第二相對表面;該第一表面接合至該第二元件;及該通道自該第二表面延伸至該第一導電區域。
- 如請求項17之結構,其中該第一元件係使用一直接接合製程而接合至該第二元件。
- 一種整合一具有一第一接觸結構之第一元件與一具有一第二接觸結構之第二元件的方法,其包含:以一金屬形成該第一接觸結構及該第二接觸結構,該金屬係選自銅、鎢、鎳、金或其合金;在該第一元件中形成一通道,其中該通道係暴露於至少該第一接觸結構;在該通道中形成一導電材料且連接至至少該第一接觸結構;將該第一元件中之一材料接合至該第二元件中之一材料,使得該第一接觸結構係直接連接至該第二接觸結構;及以一小於400℃之溫度加熱該第一元件及該第二元件以增加該第一接觸結構及該第二接觸結構之間的壓力。
- 如請求項37之方法,其包含以350℃以下之一溫度加熱。
- 如請求項37之方法,其包含自該第一接觸結構及該第二 接觸結構中之至少一者移除一自然氧化物。
- 如請求項37之方法,其包含形成該第一接觸結構及該第二接觸結構以具有一上表面,其分別與該第一元件之表面與該第二元件之表面共平面。
- 如請求項37之方法,其包含形成該第一接觸結構及該第二接觸結構以具有一上表面,其在該第一元件與該第二元件之個別表面下方不超過20nm。
- 如請求項37之方法,其包含形成該第一接觸結構及該第二接觸結構以具有一上表面,其在該第一元件與該第二元件之個別表面下方不超過10nm。
- 如請求項37之方法,其包含:形成該第一接觸結構以具有一上表面,其在該第一元件之一上表面之下方;及形成該第二接觸結構以具有一側向面積,其小於該第一接觸結構之一側向面積。
- 如請求項43之方法,其包含形成該第二接觸結構以具有一上表面,其在該第二元件之一上表面之下方。
- 如請求項37之方法,其包含蝕刻鄰接於個別之該第一接觸結構及該第二接觸結構之該第一元件及該第二元件中之至少一者之一表面。
- 如請求項37之方法,其包含在該第一接觸結構及該第二接觸結構中之至少一者上形成一金屬材料之一層。
- 如請求項46之方法,其包含:以一鎳材料形成該第一接觸結構;及 在該鎳材料上形成一厚度為5-50nm之一金層。
- 如請求項37之方法,其包含:以一第一金屬形成該第一接觸結構;及以一不同於該第一金屬之第二金屬形成該第二接觸結構。
- 如請求項37之方法,其包含:形成該第一接觸結構以具有一上表面,其在該第一元件之一上表面之下方;及形成該第二接觸結構以具有一上表面,其在該第二元件之一上表面之上方。
- 如請求項37之方法,其包含形成該第二接觸結構以具有一面積,其小於該第一接觸結構之一面積。
- 如請求項37之方法,其包含:形成該第一接觸結構以具有一上表面,其在該第一元件之一上表面之下方;及形成該第二接觸結構以具有一面積,其小於該第一接觸結構之一面積。
- 如請求項37之方法,其包含:形成該第一接觸結構以具有一上表面,其在該第一元件之一上表面之下方之一第一距離處;及形成該第二接觸結構以具有一側向面積,其小於該第一接觸結構之一側向面積。
- 如請求項37之方法,其包含以一固態金屬形成該第一接觸結構及該第二接觸結構。
- 如請求項37之方法,其包含在該第一元件及該第二元間熱延展地接合至該第一接觸元件及該第二接觸元件中之至少一者之後,加熱該第一元件及該第二元件。
- 如請求項37之方法,其包含將該第一元件中之一氧化物材料及氮化物材料中之一者接合至該第二元件中之一氧化物材料及氮化物材料中之一者。
- 一種整合一具有一第一接觸結構之第一元件與一具有一第二接觸結構之第二元件的方法,其包含:在該第一元件中形成一通道;在該通道中形成一第一導電材料;將該第一導電材料連接至該第一接觸結構;移除該第一元件之一部分以暴露出該通道中之該第一導電材料;及將該第一元件接合至該第二元件,使得該第一接觸結構及該第一導電材料中之一者直接連接至該第二接觸結構,其中在形成該第一接觸結構之前,形成該通道及該第一導電材料。
- 如請求項56之方法,其包含:在該第一元件中形成一第二通道;在該第二通道中形成一第二導電材料;及使用該第二導電材料將該第一接觸結構與該第一導電材料連接。
- 如請求項57之方法,其包含:形成該第二導電材料以具有一實質上橫向部分。
- 如請求項57之方法,其包含:將該第二導電材料形成為實質上垂直。
- 如請求項56之方法,其中該第一元件包含一裝置且該裝置包含該第一接觸結構,該方法包含:在形成該裝置之前形成該通道及該通道中之該第一導電材料。
- 如請求項56之方法,其包含:使用化學機械研磨法移除該第一元件之該部分。
- 如請求項61之方法,其包含:選擇該第一導電材料以具有一與該第一元件之該部分之一研磨速率近似相同的研磨速率。
- 如請求項56之方法,其包含:將該第一元件與該第二元件接合,使得該第一接觸結構直接連接至該第二接觸結構。
- 如請求項56之方法,其包含:在該接合之後在一低於約400℃之溫度下加熱該第一接觸結構及該第二接觸結構。
- 如請求項56之方法,其包含:在一經選擇以避免降級該第一接觸結構及該第二接觸結構與該第一導電材料之溫度下加熱該第一接觸結構及該第二接觸結構。
- 如請求項56之方法,其中:該第一元件包含一裝置,及該第二元件包含一具有至少一裝置之基板。
- 如請求項56之方法,其中:該第一元件包含一具有一裝置之單一化晶粒(singulated die);及該第二元件包含一具有至少一裝置之基板。
- 如請求項56之方法,其中:該第一元件包含一裝置;及該第二元件包含一基板。
- 如請求項56之方法,其包含:將各具有一第一接觸結構、一通道及形成於該通道中之第一導電材料的複數個第一元件接合至一具有複數個第二接觸結構的第二元件,使得該等第一元件中之每一者具有直接連接至該等第二接觸結構中之一者的該第一接觸結構及該第一導電材料中之一者。
- 如請求項69之方法,其包含:接合該第一元件及該第二元件,使得該第一接觸結構係直接連接至該第二接觸結構。
- 如請求項56之方法,其包含:在約室溫下以一在一約500-2000mJ/m2 之範圍內之接合強度,將該第一元件與該第二元件接合。
- 如請求項56之方法,其包含:在約室溫下將該第一元件與該第二元件化學地接合。
- 如請求項56之方法,其包含:將該第一元件之接近該第一接觸結構之一側接合至一基板; 薄化該第一元件以暴露該通道;在該薄化之後,將該第一元件接合至該第二元件,使得該第一導電材料直接連接至該第二接觸結構;及移除該基板。
- 一種整合方法,其包含:在一具有一第一基板之第一元件中形成一通道;在該通道中形成一導電材料;在形成該通道及該導電材料之後,在該第一元件中形成一第一接觸結構,其中該第一接觸結構係電連接至該導電材料;形成一具有至少一第二接觸結構之第二元件;移除該第一基板之一部分以暴露該通道及該導電材料;在該移除之後,將該第一基板接合至該第二基板;及在該第二接觸結構與該第一接觸結構及該導電材料中之一者之間形成一連接,作為該接合步驟的一部分。
- 如請求項74之方法,其包含:將該第一接觸結構直接連接至該第二接觸結構,作為該接合步驟之結果。
- 如請求項74之方法,其中該接合步驟包含加熱該導電材料與該第一接觸結構及該第二接觸結構。
- 如請求項76之方法,其包含:在一低於400℃之溫度下加熱。
- 如請求項76之方法,其包含: 在一經選擇以避免降級該第一接觸結構及該第二接觸結構與該導電材料之溫度下加熱該第一接觸結構及該第二接觸結構。
- 如請求項78之方法,其包含:在一低於400℃之溫度下加熱。
- 如請求項74之方法,其包含:在該第一元件中形成一裝置,該裝置包含該第一接觸結構;及在一經選擇以避免損壞該裝置的溫度下加熱該導電材料及該第二接觸結構。
- 如請求項74之方法,其包含:形成一與該導電材料及該第一接觸結構接觸之導電部件。
- 如請求項81之方法,其包含:形成一導電通道結構作為該導電部件。
- 如請求項81之方法,其包含:形成一實質上橫向互連作為該導電部件。
- 如請求項74之方法,其包含:將一具有一第三接觸結構之第三元件接合至該第一元件,使得該第三接觸結構連接至該導電材料。
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