TW202322181A - 用於脈衝式dc偏壓及箝位基板的系統及方法 - Google Patents

用於脈衝式dc偏壓及箝位基板的系統及方法 Download PDF

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TW202322181A
TW202322181A TW112103845A TW112103845A TW202322181A TW 202322181 A TW202322181 A TW 202322181A TW 112103845 A TW112103845 A TW 112103845A TW 112103845 A TW112103845 A TW 112103845A TW 202322181 A TW202322181 A TW 202322181A
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詹姆士 羅傑斯
崔琳鍈
雷歐尼德 朵夫
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美商應用材料股份有限公司
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Abstract

本揭示案的實施例大體上係關於一種在半導體製造中使用的系統。更具體而言，本揭示案的實施例係關於一種用於脈衝式DC偏壓及箝位基板的系統。在一個實施例中，系統包括電漿腔室，此電漿腔室具有ESC用於支撐基板。將電極嵌入ESC中且電耦合至偏壓與箝位電路。偏壓與箝位電路至少包括整形DC脈衝電壓源及箝位網路。箝位網路包括DC電壓源及二極體，以及電阻器。整形DC脈衝電壓源與箝位網路並聯連接。當用脈衝式DC電壓偏壓基板時，偏壓與箝位網路自動維持實質恆定的箝位電壓，此電壓為跨電極與基板的壓降，導致改良了基板的箝位。

Description

用於脈衝式DC偏壓及箝位基板的系統及方法
本揭示案的實施例大體上係關於一種在半導體製造中使用的系統。更具體而言，本揭示案的實施例係關於一種用於偏壓及箝位基板的系統。
離子轟擊通常用作電漿蝕刻中的化學及物理製程及電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition; PECVD)製程的活化能來源，以便處理半導體基板。由電漿鞘加速的高能離子亦具有很高的方向性，並且可用於蝕刻高深寬比特徵。習知地，可使用來自射頻(radio frequency; RF)源的RF功率來偏壓基板。RF源將RF電壓供應給嵌在靜電卡盤(electrostatic chuck; ESC)中的第一電極。經由陶瓷層將第一電極電容耦合至處理系統的電漿，陶瓷層為ESC的一部分。電漿鞘的非線性類二極體特性導致所施加RF場的整流，使得在基板與電漿之間出現直流(direct-current; DC)壓降或自偏壓。此壓降決定朝基板加速的離子的平均能量。
ESC藉由向嵌在ESC中的第二電極施加固定DC電壓以在ESC與基板之間建立電場來緊固安置在其上的基板。電場感應相反極性電荷，分別在基板及第二電極上累積。極性相反的電荷之間的靜電引力將基板拉向ESC，以緊固基板。然而，靜電力可受到供應給ESC中的第一電極的RF偏壓功率的影響，導致基板箝位不足或箝位過度。另外，隨著大偏壓變為數千伏，自偏壓相對於固定DC電壓的波動可導致增加電弧放電或突然解除箝位及損壞基板的風險。對於產生脈衝的非常高的偏壓功率（千伏(kV)範圍），此尤其是一個問題。
因此，需要一種用於偏壓及箝位基板的改良的系統。
本揭示案的實施例大體上係關於一種在半導體製造中使用的系統。更具體而言，本揭示案的實施例係關於一種用於脈衝式DC偏壓及箝位基板的系統。在一個實施例中，一種系統包括電漿處理腔室及耦接至電漿處理腔室的偏壓與箝位電路。偏壓與箝位電路包括第一整形DC脈衝電壓源及並聯連接至整形DC脈衝電壓源的箝位網路。箝位網路包括DC電壓源及二極體。
在另一實施例中，一種系統包括電漿處理腔室及耦接至電漿處理腔室的偏壓與箝位電路。偏壓與箝位電路經配置以向安置在電漿處理腔室中的基板提供脈衝式偏置電壓及恆定箝位電壓。
在另一實施例中，一種方法包括脈衝式DC偏壓及箝位安置在靜電卡盤上的基板，此靜電卡盤安置在電漿處理腔室中。在實質恆定的電壓下箝位基板。脈衝式DC偏壓及箝位基板包括向基板提供第一電壓，第一電壓為脈衝式，以及向嵌在靜電卡盤中的電極提供第二電壓。實質恆定的電壓為第一電壓與第二電壓之間的差。
本揭示案的實施例大體上係關於一種在半導體製造中使用的系統。更具體而言，本揭示案的實施例係關於一種用於偏壓及箝位基板的系統。在一個實施例中，系統包括電漿腔室，此電漿腔室具有ESC用於支撐基板。將電極嵌入ESC中且電耦合至偏壓與箝位電路。偏壓與箝位電路至少包括整形DC脈衝電壓源及箝位網路。箝位網路包括DC電壓源及二極體。整形DC脈衝電壓源與箝位網路並聯連接。當用脈衝式DC電壓偏壓基板時，箝位網路自動維持實質恆定的箝位電壓，此電壓為跨電極與基板的恆定壓降，導致改良了基板的箝位。
第1圖係用於偏壓及箝位基板的系統102的示意性橫截面圖。系統102包括電漿處理腔室120及偏壓與箝位電路108。在可包括本文描述的一或更多個實施例或與之組合的一個實施例中，如第1圖所示，電漿處理腔室120為反應性離子蝕刻(reactive ion etch; RIE)電漿腔室。在一些實施例中，電漿處理腔室120為PECVD腔室、電漿增強物理氣相沉積(plasma enhanced physical vapor deposition; PEPVD)腔室或電漿增強原子層沉積(plasma enhanced atomic layer deposition; PEALD)腔室。在一些實施例中，電漿處理腔室120為電漿處置腔室，或基於電漿的離子佈植腔室，例如電漿摻雜(plasma doping; PLAD)腔室。此處，電漿處理腔室120包括電漿源112，諸如電感耦合電漿(inductively coupled plasma; ICP)源，電耦合至RF電源190。在一些實施例中，電漿源112為電容耦合電漿(capacitively coupled plasma; CCP)源，諸如安置在面向基板支撐件的處理體積中的電漿電極，其中電漿電極電耦合至RF電源。
電漿處理腔室120包括腔室主體175及腔室蓋180，兩者界定處理體積170。經由噴嘴104將一或更多種處理氣體自處理氣體源185引入到處理體積170中。將電漿源112安置在處理體積170外側的腔室蓋180上方，在一個實施例中電漿源為一或更多個感應線圈。經由RF匹配電路195將電漿源112電耦合至RF電源190。RF電源190及電漿源112用於使用處理體積170中的處理氣體及感應能量來點燃及維持電漿。經由真空出口194將處理體積170流體地耦接至一或更多個真空泵192，此將處理體積170維持在低於大氣壓的條件下，且從中抽空處理氣體及/或其他氣體。在處理體積170中安置基板支撐組件100。基板支撐組件100包括ESC 122用於支撐及緊固基板130。在一或更多個層165上安置ESC 122。
在一些實施例中，一或更多個層165包括安置在其中的一或更多個流體導管（未圖示），此等流體導管流體地耦接至冷卻劑源（未圖示）或與冷卻劑源流體連通，冷卻劑源諸如具有相對較高電阻的製冷劑源或水源，以控制基板支撐組件100的溫度。ESC 122由介電材料形成，諸如塊狀燒結的陶瓷材料，諸如耐腐蝕金屬氧化物或金屬氮化物材料，例如氧化鋁(Al 2O 3)、氮化鋁(AlN)、氧化鈦(TiO)、氮化鈦(TiN)、氧化釔(Y 2O 3)、上述的混合物或上述的組合。ESC 122包括嵌在其中的電極110。電極110用於偏壓及箝位基板130。電極110由導電材料形成，諸如一或更多個金屬網、箔、板或上述的組合。
將電極110電耦合至偏壓與箝位電路108。偏壓與箝位電路108包括整形DC脈衝電壓源106及箝位網路160。當用脈衝式DC電壓由整形DC脈衝電壓源106偏壓基板130時，箝位網路160自動維持實質恆定的箝位電壓，導致改良了基板的箝位，此實質恆定的箝位電壓為跨電極110與基板130的恆定壓降。在第2圖、第4圖、第5圖及第6圖中詳細描述了偏壓與箝位電路108。
系統102進一步包括系統控制器130。系統控制器130包括中央處理單元(central processing unit; CPU) 132、記憶體134及支援電路136。使用系統控制器130控制用於處理基板130的處理次序，包括本文描述的基板偏壓及箝位。CPU 132為經配置用於工業設定以控制系統102的通用電腦處理器及與其相關的子處理器。記憶體134包括隨機存取記憶體、唯讀記憶體、軟碟或硬碟機，或本端或遠端的其他適宜形式的數位儲存器。支援電路136經耦接至CPU 132且包括快取記憶體、時脈電路、輸入/輸出子系統、電源及類似者，以及上述的組合。在一些實施例中，系統控制器130進一步包括一或更多個電腦可讀取媒體（未圖示）。
電腦可讀取媒體包括位於系統控制器130本端或遠端的任何裝置，此能夠儲存可由計算裝置擷取的資訊。可與本揭示案的實施例一起使用的電腦可讀取媒體的實例包括固態記憶體、軟碟、內部或外部硬碟機，以及光學記憶體（CD、DVD、BR-D等）。在可包括本文描述的一或更多個實施例或與之組合的一個實施例中，電腦可讀取媒體包括記憶體134。當由CPU 132執行時，軟體常式將CPU 132轉換成專用電腦，在此為系統控制器130，控制系統102的操作，使得根據本揭示案的實施例執行製程。在一些實施例中，藉由位於系統102遠端的第二控制器（未圖示）儲存及/或執行軟體常式。在一些實施例中，本文描述的製程或製程的部分由一或更多個特殊應用積體電路(application specific integrated circuit; ASIC)或其他類型的硬體實現來執行。在一些實施例中，藉由軟體常式、ASIC及/或其他類型的硬體實現的組合來執行本文描述的製程。儲存在記憶體內的軟體常式包括程式碼，程式碼可由CPU 132執行以便執行與本文描述的偏壓與箝位方案及方法相關的各種功能。
第2圖係在第1圖的系統102中執行的製程的偏壓及箝位方案的示意性電路圖。使用電路圖中所示的電路200對偏壓與箝位電路108及電漿處理腔室120的互動的主要態樣模型化。實際上，本文描述的偏壓與箝位方案與處理體積170（如第1圖所示）中的電漿的互動可伴有複雜的物理現象。
如第2圖所示，電路200包括位於電漿處理腔室120內的部件及位於偏壓與箝位電路108內的部件。電極110（如第1圖所示）、ESC 122（如第1圖所示）的介電材料及基板130（如第1圖所示）在電路200中由電容器202表示。形成於處理區域170（如第1圖所示）中的電漿鞘204在電路200中由三部分電路元件表示：a)二極體206，當導電時表示電漿鞘崩潰，b)電流源208，表示電漿鞘存在的情況下流動的離子電流，及c)電容器210，表示用於偏壓及箝位循環的主要部分（約90%）的電漿鞘，亦即，離子電流階段，在此期間發生離子加速及蝕刻（或沉積）。
偏壓與箝位電路108、電極110（如第1圖所示）及將偏壓與箝位電路108與電極110連接在一起的外部電導體（諸如電纜）具有接地的一些組合寄生電容，此在電路200中由寄生電容器212表示。外部電導體可為同軸傳輸線，此在電路200中由電感器215表示。
偏壓與箝位電路108包括整形DC脈衝電壓源106及箝位網路160，如第2圖所示。在節點N3與接地節點GND之間連接整形DC脈衝電壓源106。在節點N3與節點N1之間進一步連接電容器218。箝位網路160至少包括二極體216、電容器222、DC電壓源214及電阻器220。亦在節點N1與接地節點GND之間連接箝位網路160。在節點N1與節點N2之間連接二極體216及電阻器220，以及在節點N2與接地節點GND之間連接DC電壓源214及電容器222。使用整形DC脈衝電壓源106或脈衝式偏壓產生器在電極110（如第1圖所示）處建立脈衝式偏壓波形。使用DC電壓源214及電極216建立實質恆定的箝位電壓，此箝位電壓為跨電容器202（例如，跨電極110、ESC 122的介電材料及基板130（如第1圖所示））的電壓差。
第3A圖圖示使用第2圖的電路200的第一電壓波形302及第二電壓波形304。參看第2圖及第3A圖，在系統102（如第1圖所示）的操作期間，第一電壓波形302為基板130（如第1圖所示）處的電壓。將第一電壓波形302的峰值電壓設定為等於來自電漿的基板130（如第1圖所示）的表面上的電壓。第二電壓波形304為電極110（如第1圖所示）處的電壓。利用二極體216，第二電壓波形304自動跟蹤第一電壓波形302。二極體216的存在維持第一波形302與第二波形304之間的恆定電壓差。如第3A圖所示，第一電壓波形302及第二電壓波形304具有恆定差，此為跨電極110、ESC 122的介電材料及基板130的恆定箝位電壓。換言之，恆定箝位電壓為第一電壓波形302與第二電壓波形304之間的差。
例如，將整形DC脈衝電壓源106設定為提供自0 kV至-4 kV的DC電壓的脈衝，及將DC電壓源214設定為提供-2 kV處的恆定DC電壓。當第一電壓波形302處於0 kV（亦即，高狀態）時，第二電壓波形304處於-2 kV，因為二極體216導通。跨電容器218建立-2 kV的壓降（節點N3處的電壓比節點N1處的電壓高2 kV）。當第一電壓波形302隨後自0 kV變為-4 kV（亦即，低狀態）時，由於跨電容器218的2 kV的壓降，節點N1處的電壓變為-6 kV，此電壓基本上為第二電壓波形304。二極體216在此刻不導通，因為二極體216為反向偏壓。當第一電壓波形302自-4 kV變回0 kV時，二極體216再次導通，將電極110處的電壓波形304設定回-2 kV。因此，藉由整形DC脈衝電壓源106、二極體216及DC電壓源214自動執行箝位電壓的偏壓補償。在一些實施例中，整形DC脈衝電壓源106可提供整形DC脈衝，此等整形DC脈衝具有比第3A圖所示的電壓波形302更複雜的波形，且在第3B圖中圖示實例。
第3B圖圖示使用第2圖的電路200的第一電壓波形306及第二電壓波形308。參看第2圖及第3B圖，在系統102（如第1圖所示）的操作期間，第一電壓波形306為基板130（如第1圖所示）處的電壓。將第一電壓波形306的峰值電壓設定為等於來自電漿的基板130（如第1圖所示）的表面上的電壓。第二電壓波形308為電極110（如第1圖所示）處的電壓。利用二極體216，第二電壓波形308自動跟蹤第一電壓波形306。二極體216的存在維持第一波形306與第二波形308之間的恆定電壓差。如第3B圖所示，第一電壓波形306及第二電壓波形308具有恆定差，此為跨電極110、ESC 122的介電材料及基板130的恆定箝位電壓。換言之，恆定箝位電壓為第一電壓波形306與第二電壓波形308之間的差。
第4圖至第7圖係在第1圖的系統中執行的製程的偏壓及箝位方案的示意性電路圖。電路400、500、600及700包括電漿處理腔室120中的部件及偏壓與箝位電路108中的部件。在一些實施例中，整形DC脈衝電壓源106輸出複數個短正脈衝的脈衝串，而不是長負脈衝的脈衝串。在此情況下，由於電壓波形302（如第3A圖所示）停止在更負的電壓狀態，可在脈衝串之間發生過箝位。隨後，基板可藉由離子電流自電流源208（如第2圖所示）放電，且電壓波形302返回0 kV。然而，由於電阻器220及電容器202、212及218的RC時間常數，與基板相比，電極110需要更長的時間來放電。作為結果，電壓波形304的電壓量值保持較高，並且發生基板的過箝位。電路500、600及700提供一種解決方案，以避免在脈衝的每個脈衝串末端處的長放電時間。如第5圖所示，電路500包括具有開關502的偏壓與箝位電路108。在每個脈衝串的末端處，導通開關502以使電容器218及212在電路500中放電。
如第6圖所示，電路600包括具有整形DC脈衝電壓源網路602的偏壓與箝位電路108，此整形DC脈衝電壓源網路用於減少脈衝串之間的過度箝位。在每個脈衝串末端或在脈衝的脈衝串之間，第二整形DC脈衝電壓源603導通，以將多餘電荷自電容器202、212及218泵送至電容器604，使得留在電容器202、212及218中的電荷正好足以在電極110處維持預定箝位電壓。如第6圖所示，在節點N4與節點N5之間連接二極體216，及在節點N4與接地節點之間連接DC電壓源214。在節點N4與節點N5之間連接整形DC脈衝電壓源網路602。整形DC脈衝電壓源網路602包括串聯連接的整形DC脈衝電壓源603、二極體605及阻抗（例如，電容器604及電阻器606）。
類似地，如第7圖所示，電路700包括具有整形DC脈衝電壓源網路702的偏壓與箝位電路108，此整形DC脈衝電壓源網路用於減少脈衝串之間的過度箝位。在每個脈衝串結束時，第二整形DC脈衝電壓源703導通，以將儲存在電容器202、212及218中的多餘電荷放電。使用電路500、600及700中的一者，箝位電壓可在脈衝串導通與脈衝串關斷狀態期間均保持恆定。如第7圖所示，在節點N6與節點N7之間連接二極體216，及節點N7與接地節點之間連接DC電壓源214。在節點N6與接地節點之間連接整形DC脈衝電壓源網路702。整形DC脈衝電壓源網路702包括整形DC脈衝電壓源703、二極體704、電阻器706、DC電壓源708、電阻器710及電容器712。在節點N6與節點N7之間連接整形DC脈衝電壓源703、二極體704及電阻器706，及在節點N7與接地節點之間連接DC電壓源708、電阻器710及電容器712。
當用脈衝式DC電壓偏壓基板時，偏壓與箝位電路自動維持基板上實質恆定的箝位電壓，導致改善了基板的箝位。偏壓與箝位電路包括DC電壓源、二極體、電容器及整形DC脈衝電壓源。二極體引發電極處的電壓跟蹤脈衝式偏置電壓。作為結果，基板上的箝位電壓為實質恆定的。
儘管前述內容係針對本揭示案的實施例，但在不脫離本揭示案的基本範疇的情況下，可設計本揭示案的其他及進一步實施例，並且本揭示案的範疇由隨附申請專利範圍決定。
100:基板支撐組件 102:系統 104:噴嘴 106:整形DC脈衝電壓源 108:偏壓與箝位電路 110:電極 112:電漿源 120:電漿處理腔室 122:ESC 130:系統控制器 132:中央處理單元 134:記憶體 136:支援電路 160:箝位網路 165:層 170:處理體積 175:腔室主體 180:腔室蓋 185:處理氣體源 190:RF電源 192:真空泵 194:真空出口 195:RF匹配電路 200:電路 202:電容器 204:電漿鞘 206:二極體 208:電流源 210:電容器 212:寄生電容器 214:DC電壓源 215:電感器 216:二極體 218:電容器 220:電阻器 222:電容器 302:第一電壓波形 304:第二電壓波形 306:第一電壓波形 308:第二電壓波形 400:電路 500:電路 502:開關 600:電路 602:整形DC脈衝電壓源網路 603:第二整形DC脈衝電壓源 604:電容器 605:二極體 606:電阻器 700:電路 702:整形DC脈衝電壓源網路 703:第二整形DC脈衝電壓源 704:二極體 706:電阻器 708:DC電壓源 710:電阻器 712:電容器 N1:節點 N2:節點 N3:節點 N4:節點 N5:節點 N6:節點 N7:節點
因此，為了可詳細理解本揭示案的上述特徵結構，可參照實施例更具體描述上文簡要概述的本揭示案，一些實施例圖示於隨附圖式中。然而，應注意，隨附圖式僅圖示示例性實施例，且因此不應視為對其範疇的限制，且可允許其他同等有效的實施例。
第1圖係用於偏壓及箝位基板的系統的示意性橫截面圖。
第2圖係在第1圖的系統中執行的製程的偏壓及箝位方案的示意性電路圖。
第3A圖及第3B圖圖示第2圖的電路的電壓波形。
第4圖至第7圖係在第1圖的系統中執行的製程的偏壓及箝位方案的示意性電路圖。
為了促進理解，已儘可能使用相同元件符號來指示諸圖共有的相同元件。應設想，一個實施例的元件及特徵可有利地併入其他實施例，而無需贅述。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
106:整形DC脈衝電壓源
108:偏壓與箝位電路
120:電漿處理腔室
160:箝位網路
200:電路
202:電容器
204:電漿鞘
206:二極體
208:電流源
210:電容器
212:寄生電容器
214:DC電壓源
215:電感器
216:二極體
218:電容器
220:電阻器
222:電容器
N1:節點
N2:節點
N3:節點

Claims (14)

  1. 一種用於在一處理腔室中箝位一基板的系統，該系統包含： 一基板支撐組件，該基板支撐組件包含一電極；及 一偏壓與箝位電路，該偏壓與箝位電路耦接至該電極並經配置成產生該電極與該基板之間的一箝位電壓，該偏壓與箝位電路包含一第一整形直流(DC)脈衝電壓源、一二極體及一DC電壓源，其中該第一整形直流脈衝電壓源、該二極體及該DC電壓源經配置成偏壓該電極與該基板之間的該箝位電壓。
  2. 如請求項1所述之系統，其中該第一整形DC脈衝電壓源經配置成向該電極提供在一第一電壓與一第二電壓之間轉換的一DC電壓脈衝，且該DC電壓源經配置成通過該二極體向該電極提供一第三電壓，其中該第三電壓小於該第一電壓且大於該第二電壓。
  3. 如請求項2所述之系統，其中當該DC電壓源具有該第一電壓時，該二極體經配置成導通且在該電極處的一電壓為該第三電壓。
  4. 如請求項3所述之系統，其中當該DC電壓脈衝具有該第二電壓時，該二極體為反向偏壓且在該電極處的該電壓為該第二電壓與該第三電壓的一組合。
  5. 如請求項1所述之系統，其中該二極體與該DC電壓源串聯耦接，且其中該二極體和該DC電壓源與該第一整形DC脈衝電壓源並聯安置。
  6. 如請求項5所述之系統，其中該偏壓與箝位電路進一步包含： 一電容器，該電容器經安置在該第一整形DC脈衝電壓源與該二極體之間，及 一開關，該開關經配置成在該第一整形DC脈衝電壓源的一脈衝之後使該電容器放電。
  7. 如請求項5所述之系統，其中該偏壓與箝位電路進一步包含一整形DC脈衝電壓源網路，該整形DC脈衝電壓源網路包含一第二整形DC脈衝電壓源和一電容器，該第二整形DC脈衝電壓源和該電容器經配置成減少該電極與該基板之間的電荷。
  8. 一種偏壓與箝位電路，其經配置成： 在一處理腔室的一基板支撐件內的一電極與一基板之間產生一箝位電壓，其中該偏壓與箝位電路包含一第一整形直流(DC)脈衝電壓源、一二極體及一DC電壓源，其中該第一整形直流脈衝電壓源、該二極體及該DC電壓源經配置成偏壓該電極與該基板之間的該箝位電壓。
  9. 如請求項8所述之偏壓與箝位電路，其中該第一整形DC脈衝電壓源經配置成向該電極提供在一第一電壓與一第二電壓之間轉換的一DC電壓脈衝，且該DC電壓源經配置成通過該二極體向該電極提供一第三電壓，其中該第三電壓小於該第一電壓且大於該第二電壓。
  10. 如請求項9所述之偏壓與箝位電路，其中當該DC電壓源具有該第一電壓時，該二極體經配置成導通且在該電極處的一電壓為該第三電壓。
  11. 如請求項10所述之偏壓與箝位電路，其中當該DC電壓脈衝具有該第二電壓時，該二極體為反向偏壓且在該電極處的該電壓為該第二電壓與該第三電壓的一組合。
  12. 如請求項8所述之偏壓與箝位電路，其中該二極體與該DC電壓源串聯耦接，且其中該二極體和該DC電壓源與該第一整形DC脈衝電壓源並聯安置。
  13. 如請求項12所述之偏壓與箝位電路，進一步包含： 一電容器，該電容器經安置在該第一整形DC脈衝電壓源與該二極體之間，及 一開關，該開關經配置成在該第一整形DC脈衝電壓源的一脈衝之後使該電容器放電。
  14. 如請求項12所述之偏壓與箝位電路，進一步包含： 一整形DC脈衝電壓源網路，該整形DC脈衝電壓源網路包含一第二整形DC脈衝電壓源和一電容器，該第二整形DC脈衝電壓源和該電容器經配置成減少該電極與該基板之間的電荷。
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