CN112868083B - 使用脉冲式dc偏压时的自动esc偏压补偿 - Google Patents

使用脉冲式dc偏压时的自动esc偏压补偿 Download PDF

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CN112868083B
CN112868083B CN201980068179.5A CN201980068179A CN112868083B CN 112868083 B CN112868083 B CN 112868083B CN 201980068179 A CN201980068179 A CN 201980068179A CN 112868083 B CN112868083 B CN 112868083B
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J·罗杰斯
L·崔
L·多尔夫
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Abstract

本公开的实施例总体上涉及一种在半导体制造中使用的系统。更具体地，本公开的实施例涉及一种用于脉冲式DC偏压和箝位基板的系统。在一个实施例中，系统包括等离子体腔室，所述等离子体腔室具有ESC以用于支撑基板。电极嵌入在ESC中并电耦合至偏压与箝位电路。偏压与箝位电路至少包括整形DC脉冲电压源和箝位网络。箝位网络包括DC电压源和二极管，以及电阻器。整形DC脉冲电压源与箝位网络并联连接。当用脉冲式DC电压偏压基板时，偏压与箝位网络自动维持基本上恒定的箝位电压，所述箝位电压是跨电极与基板的压降，从而导致改良了基板的箝位。

Description

使用脉冲式DC偏压时的自动ESC偏压补偿
背景技术
技术领域
本公开的实施例总体上涉及一种在半导体制造中使用的系统。更具体地，本公开的实施例涉及一种用于偏压和箝位基板的系统。
相关技术说明
离子轰击通常用作等离子体蚀刻中的化学和物理工艺以及等离子体增强化学气相沉积(PECVD)工艺的活化能来源，以用于处理半导体基板。由等离子体壳层加速的高能离子还是高度定向的，并且可用于蚀刻高深宽比特征。常规地，可使用来自射频(RF)源的RF功率来偏压基板。RF源将RF电压供应给嵌入在静电卡盘(ESC)中的第一电极。通过陶瓷层将第一电极电容耦合至处理系统的等离子体，陶瓷层是ESC的一部分。等离子体壳层的非线性的、类似二极管的特性导致所施加的RF场的整流，使得在基板与等离子体之间出现直流(DC)压降或自偏压。此压降确定朝向基板加速的离子的平均能量。
ESC通过向嵌入在ESC中的第二电极施加固定DC电压以在ESC与基板之间建立电场来紧固设置在ESC上的基板。电场感应相反极性电荷，分别在基板和第二电极上累积。相反极化的电荷之间的静电引力将基板拉向ESC以紧固基板。然而，静电力可受到供应给ESC中的第一电极的RF偏压功率的影响，导致基板箝位不足或箝位过度。另外，随着大偏压变为数千伏，自偏压相对于固定DC电压的波动可导致电弧放电或突然去箝位和损坏基板的风险增加。对于产生脉冲的非常高的偏压功率(千伏(kV)范围)，这尤其是一个问题。
因此，需要一种用于偏压和箝位基板的改良的系统。
发明内容
本公开的实施例总体上涉及一种在半导体制造中使用的系统。更具体地，本公开的实施例涉及一种用于脉冲式DC偏压和箝位基板的系统。在一个实施例中，系统包括等离子体工艺腔室和耦接至等离子体工艺腔室的偏压与箝位电路。偏压与箝位电路包括第一整形DC脉冲电压源和并联连接至整形DC脉冲电压源的箝位网络。箝位网络包括DC电压源和二极管。
在另一实施例中，一种系统包括等离子体工艺腔室和耦接至等离子体工艺腔室的偏压与箝位电路。偏压与箝位电路被配置成向设置在等离子体工艺腔室中的基板提供脉冲式偏压电压和恒定箝位电压。
在另一实施例中，一种方法包括脉冲式DC偏压和箝位设置在静电卡盘上的基板，所述静电卡盘设置在等离子体工艺腔室中。在基本上恒定的电压下箝位基板。脉冲式DC偏压和箝位基板包括向基板提供第一电压，第一电压为脉冲式，以及向嵌入在静电卡盘中的电极提供第二电压。基本上恒定的电压为第一电压与第二电压之间的差。
附图说明
因此，为了可详细理解本公开的上述特征的方式，可参照实施例来对上文简要概述的本公开进行更具体的描述，所述实施例中的一些实施例在附图中示出。然而，应注意，附图仅示出示例性实施例，并且因此不应视为对其范围的限制，并且可允许其他同等有效的实施例。
图1是用于偏压和箝位基板的系统的示意性横截面图。
图2是在图1的系统中执行的工艺的偏压和箝位方案的示意性电路图。
图3A和图3B示出图2的电路的电压波形。
图4至图7是在图1的系统中执行的工艺的偏压和箝位方案的示意性电路图。
为了促进理解，已尽可能使用相同附图标记来指示附图共有的相同元件。构想到一个实施例的元件和特征可有利地并入其他实施例，而无需进一步叙述。
具体实施方式
本公开的实施例总体上涉及一种在半导体制造中使用的系统。更具体地，本公开的实施例涉及一种用于偏压和箝位基板的系统。在一个实施例中，系统包括等离子体腔室，所述等离子体腔室具有ESC以用于支撑基板。电极嵌入在ESC中并电耦合至偏压与箝位电路。偏压与箝位电路至少包括整形DC脉冲电压源和箝位网络。箝位网络包括DC电压源和二极管。整形DC脉冲电压源与箝位网络并联连接。当用脉冲式DC电压偏压基板时，箝位网络自动维持基本上恒定的箝位电压，所述箝位电压是跨电极与基板的恒定压降，从而导致改良了基板的箝位。
图1是用于偏压和箝位基板的系统102的示意性横截面图。系统102包括等离子体工艺腔室120和偏压与箝位电路108。在可包括本文描述的一个或多个实施例或与本文描述的一个或多个实施例组合的一个实施例中，如图1所示，等离子体工艺腔室120为反应性离子蚀刻(RIE)等离子体腔室。在一些实施例中，等离子体工艺腔室120为PECVD腔室、等离子体增强物理气相沉积(PEPVD)腔室或等离子体增强原子层沉积(PEALD)腔室。在一些实施例中，等离子体工艺腔室120为等离子体处置腔室，或基于等离子体的离子注入腔室，例如等离子体掺杂(PLAD)腔室。在本文中，等离子体工艺腔室120包括电耦合至RF电源190的等离子体源112，诸如电感耦合等离子体(ICP)源。在一些实施例中，等离子体源112为电容耦合等离子体(CCP)源，诸如设置在面向基板支撑件的处理空间中的等离子体电极，其中等离子体电极电耦合至RF电源。
等离子体工艺腔室120包括腔室主体175和腔室盖180，腔室主体175和腔室盖180界定处理空间170。经由喷嘴104将一种或多种处理气体从处理气体源185引入到处理空间170中。将等离子体源112设置在处理空间170外侧的腔室盖180之上，在一个实施例中等离子体源112为一个或多个感应线圈。经由RF匹配电路195将等离子体源112电耦合至RF电源190。RF电源190和等离子体源112用于使用处理空间170中的处理气体和感应能量来点燃和维持等离子体。通过真空出口194将处理空间170流体地耦接至一个或多个真空泵192，这将处理空间170维持在低于大气压的条件下，并且从处理空间170中抽空处理气体和/或其他气体。基板支撑组件100设置在处理空间170中。基板支撑组件100包括ESC 122以用于支撑和紧固基板130。ESC 122设置在一个或多个层165上。
在一些实施例中，一个或多个层165包括设置在一个或多个层165中的一个或多个流体导管(未示出)，所述流体导管流体地耦接至冷却剂源(未示出)并与冷却剂源流体连通，冷却剂源诸如具有相对高电阻的制冷剂源或水源，以控制基板支撑组件100的温度。ESC122由介电材料形成，诸如块状烧结的陶瓷材料，诸如耐腐蚀金属氧化物或金属氮化物材料，例如氧化铝(Al2O3)、氮化铝(AlN)、氧化钛(TiO)、氮化钛(TiN)、氧化钇(Y2O3)、它们的混合物或它们的组合。ESC 122包括嵌入在ESC 122中的电极110。电极110用于偏压和箝位基板130两者。电极110由导电材料形成，诸如一个或多个金属网、箔、板或它们的组合。
将电极110电耦合至偏压与箝位电路108。偏压与箝位电路108包括整形DC脉冲电压源106和箝位网络160。当由整形DC脉冲电压源106用脉冲式DC电压来偏压基板130时，箝位网络160自动维持基本上恒定的箝位电压，所述箝位电压为跨电极110与基板130的恒定压降，从而导致改良了基板的箝位。在图2、图4、图5和图6中详细描述了偏压与箝位电路108。
系统102进一步包括系统控制器130。系统控制器130包括中央处理单元(CPU)132、存储器134和支持电路136。系统控制器130用于控制用于处理基板130的工艺序列，包括本文描述的基板偏压和箝位。CPU 132是配置用于在工业设置中使用以用于控制系统102和与其相关的子处理器的通用计算机处理器。存储器134包括随机存取存储器、只读存储器、软盘或硬盘驱动器，或本地或远程的其他适当形式的数字储存。支持电路136耦接至CPU 132并且包括高速缓存、时钟电路、输入/输出子系统、电源等，以及它们的组合。在一些实施例中，系统控制器130进一步包括一个或多个计算机可读介质(未示出)。
计算机可读介质包括位于系统控制器130本地或远程的任何装置，所述装置能够储存可由计算装置检取的信息。可与本公开的实施例一起使用的计算机可读介质的示例包括固态存储器、软盘、内部或外部硬盘驱动器、以及光学存储器(CD、DVD、BR-D等)。在可包括本文描述的一个或多个实施例或与本文描述的一个或多个实施例组合的一个实施例中，计算机可读介质包括存储器134。软件例程在由CPU 132执行时将CPU 132转换成专用计算机，在本文中为系统控制器130，系统控制器130控制系统102的操作，使得根据本公开的实施例来执行工艺。在一些实施例中，通过位于系统102远程的第二控制器(未示出)来储存和/或执行软件例程。在一些实施例中，本文描述的工艺或工艺的部分由一个或多个专用集成电路(ASIC)或其他类型的硬件实现来执行。在一些实施例中，通过软件例程、ASIC和/或其他类型的硬件实现的组合来执行本文描述的工艺。储存在存储器内的软件例程包括程序代码，所述程序代码可由CPU 132执行以便执行与本文描述的偏压和箝位方案和方法相关联的各种功能。
图2是在图1的系统102中执行的工艺的偏压和箝位方案的示意性电路图。电路图中所示的电路200用于对偏压与箝位电路108和等离子体工艺腔室120的交互的主要方面进行建模。实际上，本文描述的偏压和箝位方案与处理空间170(如图1所示)中的等离子体的交互可伴有复杂的物理现象。
如图2所示，电路200包括位于等离子体工艺腔室120内的部件和位于偏压与箝位电路108内的部件。电极110(如图1所示)、ESC 122(如图1所示)的介电材料、以及基板130(如图1所示)在电路200中由电容器202表示。形成在处理区域170(如图1所示)中的等离子体壳层204在电路200中由三部分电路元件表示，所述三部分电路元件包括：a)二极管206，在导通时表示等离子体壳层崩溃，b)电流源208，表示在等离子体壳层存在的情况下流动的离子电流，以及c)电容器210，表示用于偏压和箝位循环的主要部分(约90％)(即，离子电流阶段，在离子电流阶段期间发生离子加速和蚀刻(或沉积))的等离子体壳层。
偏压与箝位电路108、电极110(如图1所示)和将偏压与箝位电路108和电极110连接在一起的外部电导体(诸如电缆)具有对接地的一些组合寄生电容，这在电路200中由寄生电容器212来表示。外部电导体可为同轴传输线，这在电路200中由电感器215表示。
偏压与箝位电路108包括整形DC脉冲电压源106和箝位网络160，如图2所示。在节点N3与接地节点GND之间连接整形DC脉冲电压源106。在节点N3与节点N1之间进一步连接电容器218。箝位网络160至少包括二极管216、电容器222、DC电压源214和电阻器220。还在节点N1与接地节点GND之间连接箝位网络160。在节点N1与节点N2之间连接二极管216和电阻器220，以及在节点N2与接地节点GND之间连接DC电压源214和电容器222。整形DC脉冲电压源106或脉冲式偏压发生器用于在电极110(如图1所示)处建立脉冲式偏压波形。DC电压源214和二极管216用于建立基本上恒定的箝位电压，所述箝位电压为跨电容器202(例如，跨电极110、ESC 122的介电材料和基板130(如图1所示))的电压差。
图3A示出使用图2的电路200的第一电压波形302和第二电压波形304。参考图2和图3A，在系统102(如图1所示)的操作期间，第一电压波形302为基板130(如图1所示)处的电压。将第一电压波形302的峰值电压设定为等于来自等离子体的基板130(如图1所示)的表面上的电压。第二电压波形304为电极110(如图1所示)处的电压。利用二极管216，第二电压波形304自动跟踪第一电压波形302。二极管216的存在维持第一波形302与第二波形304之间的恒定电压差。如图3A所示，第一电压波形302和第二电压波形304具有恒定差，这是跨电极110、ESC 122的介电材料和基板130的恒定箝位电压。换言之，恒定箝位电压为第一电压波形302与第二电压波形304之间的差。
例如，将整形DC脉冲电压源106设定为提供自0kV至-4kV的DC电压的脉冲，并将DC电压源214设定为提供-2kV的恒定DC电压。当第一电压波形302处于0kV(即，高状态)时，第二电压波形304处于-2kV，因为二极管216导通。跨电容器218建立-2kV的压降(节点N3处的电压比节点N1处的电压高2kV)。当第一电压波形302随后从0kV变为-4kV(即，低状态)时，由于跨电容器218的2kV的压降，节点N1处的电压变为-6kV，此电压本质上为第二电压波形304。二极管216在此刻不导通，因为二极管216为反向偏压。当第一电压波形302从-4kV变回0kV时，二极管216再次导通，将电极110处的电压波形304设定回-2kV。因此，通过整形DC脉冲电压源106、二极管216和DC电压源214来自动执行箝位电压的偏压补偿。在一些实施例中，整形DC脉冲电压源106可提供整形DC脉冲，所述整形DC脉冲具有比图3A所示的电压波形302更复杂的波形，并且在图3B中示出示例。
图3B示出使用图2的电路200的第一电压波形306和第二电压波形308。参考图2和图3B，在系统102(如图1所示)的操作期间，第一电压波形306为基板130(如图1所示)处的电压。将第一电压波形306的峰值电压设定为等于来自等离子体的基板130(如图1所示)的表面上的电压。第二电压波形308为电极110(如图1所示)处的电压。利用二极管216，第二电压波形308自动跟踪第一电压波形306。二极管216的存在维持第一波形306与第二波形308之间的恒定电压差。如图3B所示，第一电压波形306和第二电压波形308具有恒定差，这是跨电极110、ESC 122的介电材料和基板130的恒定箝位电压。换言之，恒定箝位电压为第一电压波形306与第二电压波形308之间的差。
图4至图7是在图1的系统中执行的工艺的偏压和箝位方案的示意性电路图。电路400、500、600和700包括等离子体工艺腔室120中的部件和偏压与箝位电路108中的部件。在一些实施例中，整形DC脉冲电压源106输出多个短正脉冲的脉冲串，而不是长负脉冲的脉冲串。在此情况下，由于电压波形302(如图3A所示)停止在更负的电压状态，所以可能在脉冲串之间发生过箝位。随后，基板可通过离子电流从电流源208(如图2所示)放电，并且电压波形302返回0kV。然而，由于电阻器220和电容器202、212和218的RC时间常数，所以与基板相比，电极110花费更长的时间来放电。作为结果，电压波形304的电压幅值保持在高，并且发生基板的过箝位。电路500、600和700提供一种解决方案，以避免在脉冲的每个脉冲串末端处的长放电时间。如图5所示，电路500包括具有开关502的偏压与箝位电路108。在每个脉冲串的末端处，导通开关502以使电容器218和212在电路500中放电。
如图6所示，电路600包括具有整形DC脉冲电压源网络602的偏压与箝位电路108，整形DC脉冲电压源网络602用于减少脉冲串之间的过度箝位。在每个脉冲串末端或在脉冲的脉冲串之间，第二整形DC脉冲电压源603导通，以将多余电荷从电容器202、212和218泵送至电容器604，使得留在电容器202、212和218中的电荷正好足以在电极110处维持预定的箝位电压。如图6所示，在节点N4与节点N5之间连接二极管216，并在节点N4与接地节点之间连接DC电压源214。在节点N4与节点N5之间连接整形DC脉冲电压源网络602。整形DC脉冲电压源网络602包括串联连接的整形DC脉冲电压源603、二极管605和阻抗(例如，电容器604和电阻器606)。
类似地，如图7所示，电路700包括具有整形DC脉冲电压源网络702的偏压与箝位电路108，整形DC脉冲电压源网络702用于减少脉冲串之间的过度箝位。在每个脉冲串结束时，第二整形DC脉冲电压源703导通，以将储存在电容器202、212和218中的多余电荷放电。使用电路500、600和700中的一者，箝位电压可在脉冲串导通与脉冲串关断状态期间均保持恒定。如图7所示，在节点N6与节点N7之间连接二极管216，并在节点N7与接地节点之间连接DC电压源214。在节点N6与接地节点之间连接整形DC脉冲电压源网络702。整形DC脉冲电压源网络702包括整形DC脉冲电压源703、二极管704、电阻器706、DC电压源708、电阻器710和电容器712。在节点N6与节点N7之间连接整形DC脉冲电压源703、二极管704和电阻器706，并在节点N7与接地节点之间连接DC电压源708、电阻器710和电容器712。
当用脉冲式DC电压偏压基板时，偏压与箝位电路自动维持基板上基本上恒定的箝位电压，导致改善了基板的箝位。偏压与箝位电路包括DC电压源、二极管、电容器和整形DC脉冲电压源。二极管使电极处的电压跟踪脉冲式偏压电压。作为结果，基板上的箝位电压为基本上恒定的。
尽管前述内容是针对本公开的实施例，但在不脱离本公开的基本范围的情况下，可设计本公开的其他和进一步实施例，并且本公开的范围由所附权利要求确定。

Claims (17)

1.一种用于偏压与箝位基板的系统，包含：
等离子体工艺腔室，所述等离子体工艺腔室包含基板支撑组件，所述基板支撑组件包含静电卡盘，其中所述静电卡盘包含介电材料和嵌入在所述介电材料中的电极，其中第一整形DC脉冲电压源和箝位网络连接至所述电极；以及
偏压与箝位电路，所述偏压与箝位电路耦接至所述等离子体工艺腔室，所述偏压与箝位电路包含：
第一整形DC脉冲电压源，所述第一整形DC脉冲电压源输出脉冲串；以及
箝位网络，所述箝位网络在第一节点与接地节点之间与所述第一整形DC脉冲电压源并联，所述箝位网络包含：
直流电压源，所述直流电压源耦合到所述接地节点和第二节点；
二极管，所述二极管耦合到所述第一节点和所述第二节点，所述直流电压源和所述二极管用于建立恒定的箝位电压；
电容器，所述电容器耦合到所述接地节点和所述第二节点；以及
电阻器，所述电阻器耦合到所述第一节点和所述第二节点并且与所述二极管并联。
2.如权利要求1所述的系统，其中所述等离子体工艺腔室包含：
腔室主体；
腔室盖，其中所述腔室主体与所述腔室盖界定处理空间；并且
所述基板支撑组件设置在所述处理空间中。
3.如权利要求2所述的系统，其中所述偏压与箝位电路被配置成向设置在所述等离子体工艺腔室中的所述基板提供脉冲式偏压电压和恒定箝位电压。
4.如权利要求1所述的系统，其中所述偏压与箝位电路进一步包含与所述二极管并联的第二整形DC脉冲电压源，所述第二整形DC脉冲电压源在每个脉冲串末端或在脉冲串之间导通，以将储存在所述电容器中的多余电荷放电。
5.如权利要求1所述的系统，其中所述偏压与箝位电路进一步包含与所述二极管并联的开关，所述开关在每个脉冲串末端导通，以将所述电容器在所述电路中放电。
6.一种用于偏压与箝位基板的系统，包含：
等离子体工艺腔室；以及
耦接至所述等离子体工艺腔室的偏压与箝位电路，所述偏压与箝位电路被配置成向设置在所述等离子体工艺腔室中的所述基板提供脉冲式偏压电压和恒定箝位电压，其中所述偏压与箝位电路包含：
第一整形DC脉冲电压源，所述第一整形DC脉冲电压源输出脉冲串；以及
箝位网络，所述箝位网络在第一节点与接地节点之间与所述第一整形DC脉冲电压源并联，其中所述箝位网络包含：
第一二极管，所述第一二极管连接在所述第一节点与第二节点之间；
第一直流电压源，所述第一直流电压源连接在所述第二节点与所述接地节点之间，所述第一直流电压源和所述第一二极管用于建立恒定的箝位电压；
第一电容器，所述第一电容器耦合到所述接地节点和所述第二节点；以及
第一电阻器，所述第一电阻器耦合到所述第一节点和所述第二节点并且与所述第一二极管并联。
7.如权利要求6所述的系统，其中所述偏压与箝位电路进一步包含第一整形DC脉冲电压源网络，并且其中在所述第一节点与所述第二节点之间连接所述第一整形DC脉冲电压源网络。
8.如权利要求7所述的系统，其中所述第一整形DC脉冲电压源网络包含串联连接的第二整形DC脉冲电压源、第二二极管和阻抗。
9.如权利要求6所述的系统，其中所述偏压与箝位电路进一步包含第二整形DC脉冲电压源网络，并且其中在所述第一节点与所述接地节点之间连接所述第二整形DC脉冲电压源网络。
10.如权利要求9所述的系统，其中所述第二整形DC脉冲电压源网络包含第三整形DC脉冲电压源、第三二极管、第二电阻器、第二直流电压源、第三电阻器和第二电容器，其中在所述第一节点与所述第二节点之间连接所述第三整形DC脉冲电压源、所述第三二极管和所述第二电阻器，并且其中所述第三整形DC脉冲电压源和所述第三二极管串联并且所述第二电阻器与所述第三整形DC脉冲电压源和所述第三二极管的连接并联，并且其中在所述第二节点与所述接地节点之间连接所述第二直流电压源、所述第三电阻器和所述第二电容器，并且其中所述第二直流电压源和所述第三电阻器串联并且所述第二电容器与所述第二直流电压源和所述第三电阻器的连接并联。
11.一种用于偏压与箝位基板的方法，包含：
利用偏压与箝位电路来对设置在静电卡盘上的所述基板进行偏压和箝位，所述静电卡盘设置在等离子体工艺腔室中，在基本上恒定的电压下箝位所述基板，对所述基板进行偏压和箝位包含：
向所述基板提供第一电压，所述第一电压为脉冲式；以及
向嵌入在所述静电卡盘中的电极提供第二电压，所述基本上恒定的电压为所述第一电压与所述第二电压之间的差，其中所述方法由所述偏压与箝位电路执行，所述偏压与箝位电路包含：
第一整形DC脉冲电压源，所述第一整形DC脉冲电压源输出脉冲串；以及
箝位网络，所述箝位网络在第一节点与接地节点之间与所述第一整形DC脉冲电压源并联，所述箝位网络包含：
直流电压源，所述直流电压源耦合到所述接地节点和第二节点；
二极管，所述二极管耦合到所述第一节点和所述第二节点，所述直流电压源和所述二极管用于建立恒定的箝位电压；
电容器，所述电容器耦合到所述接地节点和所述第二节点；以及
电阻器，所述电阻器耦合到所述第一节点和所述第二节点并且与所述二极管并联。
12.如权利要求11所述的方法，其中由第一整形DC脉冲电压源和箝位网络来执行所述偏压和箝位所述基板，并且由所述第一整形DC脉冲电压源来提供所述第一电压。
13.如权利要求12所述的方法，其中当所述第一电压处于高状态时，所述二极管导通，并且当所述第一电压处于低状态时，所述二极管处于反向偏压模式。
14.如权利要求12所述的方法，其中所述第一电压包含正脉冲的脉冲串。
15.如权利要求14所述的方法，其中所述箝位网络包含与所述二极管并联的开关，并且所述开关在所述正脉冲的脉冲串之间导通，以将所述电容器在所述电路中放电。
16.如权利要求15所述的方法，其中所述箝位网络包括与所述二极管并联的第二整形DC脉冲电压源，并且所述第二整形DC脉冲电压源在所述正脉冲的脉冲串之间导通，以将储存在所述电容器中的多余电荷放电。
17.如权利要求12所述的方法，其中所述第一电压包含负脉冲的脉冲串。
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