KR100921287B1 - 불휘발성 반도체 메모리 및 그 제조 방법 - Google Patents
불휘발성 반도체 메모리 및 그 제조 방법 Download PDFInfo
- Publication number
- KR100921287B1 KR100921287B1 KR1020070134562A KR20070134562A KR100921287B1 KR 100921287 B1 KR100921287 B1 KR 100921287B1 KR 1020070134562 A KR1020070134562 A KR 1020070134562A KR 20070134562 A KR20070134562 A KR 20070134562A KR 100921287 B1 KR100921287 B1 KR 100921287B1
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- South Korea
- Prior art keywords
- semiconductor substrate
- layer
- gate electrode
- insulating film
- semiconductor
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- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D30/693—Vertical IGFETs having charge trapping gate insulators
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JPJP-P-2006-00344803 | 2006-12-21 | ||
| JP2006344803A JP4772656B2 (ja) | 2006-12-21 | 2006-12-21 | 不揮発性半導体メモリ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20080058251A KR20080058251A (ko) | 2008-06-25 |
| KR100921287B1 true KR100921287B1 (ko) | 2009-10-09 |
Family
ID=39640393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020070134562A Expired - Fee Related KR100921287B1 (ko) | 2006-12-21 | 2007-12-20 | 불휘발성 반도체 메모리 및 그 제조 방법 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US7875922B2 (https=) |
| JP (1) | JP4772656B2 (https=) |
| KR (1) | KR100921287B1 (https=) |
| TW (1) | TW200845312A (https=) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8115259B2 (en) | 2009-02-02 | 2012-02-14 | Samsung Electronics Co., Ltd. | Three-dimensional memory device |
| US8541831B2 (en) | 2008-12-03 | 2013-09-24 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method for fabricating the same |
| US8786007B2 (en) | 2008-12-03 | 2014-07-22 | Samsung Electronics Co., Ltd. | Three-dimensional nonvolatile memory device |
Families Citing this family (179)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005051417A1 (de) * | 2005-10-27 | 2007-05-03 | X-Fab Semiconductor Foundries Ag | Simulations- bzw. Layoutverfahren für vertikale Leistungstransistoren mit variierbarer Kanalweite und variierbarer Gate-Drain-Kapazität |
| JP4821516B2 (ja) * | 2006-08-31 | 2011-11-24 | 旭光電機株式会社 | 多関節構造体 |
| JP5016928B2 (ja) * | 2007-01-10 | 2012-09-05 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
| JP4445514B2 (ja) * | 2007-04-11 | 2010-04-07 | 株式会社東芝 | 半導体記憶装置 |
| US8633537B2 (en) | 2007-05-25 | 2014-01-21 | Cypress Semiconductor Corporation | Memory transistor with multiple charge storing layers and a high work function gate electrode |
| US20090179253A1 (en) | 2007-05-25 | 2009-07-16 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
| US9449831B2 (en) | 2007-05-25 | 2016-09-20 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
| US8614124B2 (en) | 2007-05-25 | 2013-12-24 | Cypress Semiconductor Corporation | SONOS ONO stack scaling |
| US9299568B2 (en) | 2007-05-25 | 2016-03-29 | Cypress Semiconductor Corporation | SONOS ONO stack scaling |
| US8221345B2 (en) | 2007-05-30 | 2012-07-17 | Smiths Medical Asd, Inc. | Insulin pump based expert system |
| JP5376789B2 (ja) * | 2007-10-03 | 2013-12-25 | 株式会社東芝 | 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の制御方法 |
| US9431549B2 (en) | 2007-12-12 | 2016-08-30 | Cypress Semiconductor Corporation | Nonvolatile charge trap memory device having a high dielectric constant blocking region |
| KR101559868B1 (ko) | 2008-02-29 | 2015-10-14 | 삼성전자주식회사 | 수직형 반도체 소자 및 이의 제조 방법. |
| US7906818B2 (en) * | 2008-03-13 | 2011-03-15 | Micron Technology, Inc. | Memory array with a pair of memory-cell strings to a single conductive pillar |
| JP4649487B2 (ja) * | 2008-03-17 | 2011-03-09 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
| US7910973B2 (en) * | 2008-03-17 | 2011-03-22 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
| JP2009238874A (ja) * | 2008-03-26 | 2009-10-15 | Toshiba Corp | 半導体メモリ及びその製造方法 |
| JP5288877B2 (ja) * | 2008-05-09 | 2013-09-11 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| JP2009277770A (ja) * | 2008-05-13 | 2009-11-26 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
| KR101052921B1 (ko) * | 2008-07-07 | 2011-07-29 | 주식회사 하이닉스반도체 | 버티컬 플로팅 게이트를 구비하는 플래시 메모리소자의제조방법 |
| US8044448B2 (en) * | 2008-07-25 | 2011-10-25 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
| JP5430890B2 (ja) | 2008-07-25 | 2014-03-05 | 株式会社東芝 | 半導体記憶装置 |
| JP2010050127A (ja) * | 2008-08-19 | 2010-03-04 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
| KR101498676B1 (ko) * | 2008-09-30 | 2015-03-09 | 삼성전자주식회사 | 3차원 반도체 장치 |
| KR101502585B1 (ko) * | 2008-10-09 | 2015-03-24 | 삼성전자주식회사 | 수직형 반도체 장치 및 그 형성 방법 |
| KR100979906B1 (ko) * | 2008-10-09 | 2010-09-06 | 서울대학교산학협력단 | 고집적 플래시 메모리 셀 스택, 셀 스택 스트링 및 그 제조방법 |
| JP2010098067A (ja) * | 2008-10-15 | 2010-04-30 | Toshiba Corp | 半導体装置 |
| KR101503876B1 (ko) * | 2009-03-06 | 2015-03-20 | 삼성전자주식회사 | 비휘발성 메모리 소자 |
| US7994011B2 (en) * | 2008-11-12 | 2011-08-09 | Samsung Electronics Co., Ltd. | Method of manufacturing nonvolatile memory device and nonvolatile memory device manufactured by the method |
| JP2010123600A (ja) * | 2008-11-17 | 2010-06-03 | Toshiba Corp | 不揮発性半導体記憶装置 |
| US8148763B2 (en) | 2008-11-25 | 2012-04-03 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor devices |
| KR101511764B1 (ko) * | 2008-12-03 | 2015-04-13 | 삼성전자주식회사 | 비휘발성 메모리 장치 |
| JP5356005B2 (ja) | 2008-12-10 | 2013-12-04 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
| KR101468595B1 (ko) * | 2008-12-19 | 2014-12-04 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
| KR101495806B1 (ko) | 2008-12-24 | 2015-02-26 | 삼성전자주식회사 | 비휘발성 기억 소자 |
| KR101551901B1 (ko) * | 2008-12-31 | 2015-09-09 | 삼성전자주식회사 | 반도체 기억 소자 및 그 형성 방법 |
| KR101524823B1 (ko) * | 2009-01-05 | 2015-06-01 | 삼성전자주식회사 | 3차원 반도체 소자 |
| KR101512494B1 (ko) | 2009-01-09 | 2015-04-16 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
| KR101481104B1 (ko) * | 2009-01-19 | 2015-01-13 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그 제조 방법 |
| US8644046B2 (en) | 2009-02-10 | 2014-02-04 | Samsung Electronics Co., Ltd. | Non-volatile memory devices including vertical NAND channels and methods of forming the same |
| US8614917B2 (en) | 2010-02-05 | 2013-12-24 | Samsung Electronics Co., Ltd. | Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors |
| JP5383241B2 (ja) * | 2009-02-16 | 2014-01-08 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
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| KR101532366B1 (ko) | 2009-02-25 | 2015-07-01 | 삼성전자주식회사 | 반도체 기억 소자 |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW200845312A (en) | 2008-11-16 |
| TWI358107B (https=) | 2012-02-11 |
| JP4772656B2 (ja) | 2011-09-14 |
| US8148216B2 (en) | 2012-04-03 |
| KR20080058251A (ko) | 2008-06-25 |
| US20110092033A1 (en) | 2011-04-21 |
| US20080173928A1 (en) | 2008-07-24 |
| US7875922B2 (en) | 2011-01-25 |
| JP2008159699A (ja) | 2008-07-10 |
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