JP5613506B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5613506B2 JP5613506B2 JP2010203164A JP2010203164A JP5613506B2 JP 5613506 B2 JP5613506 B2 JP 5613506B2 JP 2010203164 A JP2010203164 A JP 2010203164A JP 2010203164 A JP2010203164 A JP 2010203164A JP 5613506 B2 JP5613506 B2 JP 5613506B2
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- gate electrode
- region
- insulating film
- film
- memory
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Description
まず、本発明者らによって検討された不揮発性メモリについて説明する。
前述した実施の形態1と相違する点は、メモリセル形成領域の選択用nMIS(Qnc)の選択ゲート電極CGを構成する第1導電膜の上面に絶縁膜を介してキャップ絶縁膜CAPが形成されていることである。
本発明は、不揮発性メモリ(不揮発性記憶素子、フラッシュメモリ、不揮発性半導体記憶装置)を備えた半導体装置であり、不揮発性メモリは、主として電荷蓄積部にトラップ性絶縁膜(電荷を蓄積可能な絶縁膜)を用いたものである。以下の実施の形態では、不揮発性メモリは、nチャネル型MISFET(MISFET:Metal Insulator Semiconductor Field Effect Transistor)を基本としトラップ性絶縁膜を用いたメモリセルをもとに説明を行う。また、以下の実施の形態での極性(書込・消去・読出時の印加電圧の極性やキャリアの極性)は、nチャネル型MISFETを基本としたメモリセルの場合の動作を説明するためのものであり、pチャネル型MISFETを基本とする場合は、印加電位やキャリアの導電型等の全ての極性を反転させることで、原理的には同じ動作を得ることができる。
図95〜図97は、本実施の形態の半導体装置の製造工程中の要部平面図である。図95は、上記実施の形態3の図58に対応し、図96は、上記実施の形態3の図61に対応し、図97は、上記実施の形態3の図73に対応する。
図100は、本実施の形態の半導体装置の要部断面図であり、上記実施の形態3の図39に対応するものである。図100には、上記実施の形態3の図39と同様に、メモリセル領域61Aの断面(上記A1−A1線に相当する位置での断面)が示されている。
2ad n−型の半導体領域
2as n−型の半導体領域
2b n+型の半導体領域
3 シリサイド層
4 ゲート絶縁膜(第1ゲート絶縁膜または第3ゲート絶縁膜)
4A ゲート絶縁膜
5 p型の半導体領域
6b 絶縁膜(第4絶縁膜)
6t 絶縁膜(第5絶縁膜)
6b/CSL/6t 絶縁膜/電荷蓄積層/絶縁膜(第2ゲート絶縁膜)
7b、7t 酸化シリコン膜
7m 窒化シリコン膜
8 n型の半導体領域
9 層間絶縁膜
9a 窒化シリコン膜
9b 酸化シリコン膜
10 導電膜
10n n型の導電膜(第1導電膜)
10na n型の導電膜
10p p型の導電膜
10E 下部電極
11 サイドウォール
11E 上部電極
13 n−型の半導体領域
14 p−型の半導体領域
15 サイドウォール
16,17 フォトレジストパターン
18 n−型の半導体領域
19 p−型の半導体領域
20 フォトレジストパターン
21 p+型の半導体領域
22 フォトレジストパターン
23 n+型の半導体領域
25 酸化膜(第6絶縁膜)
51 パッド電極
61 半導体基板
61A メモリセル領域
61B ソースダミー領域
61C ワードシャント領域
62 素子分離領域
63 絶縁膜
64 シリコン膜
65 絶縁膜
65a,65c 酸化シリコン膜
65b 窒化シリコン膜
66 シリコン膜
67a,67b n−型半導体領域
68 側壁絶縁膜
69a,69b n+型半導体領域
71,71a 金属シリサイド層
72 絶縁膜
73a バリア導体膜
73b 主導体膜
74 絶縁膜
77 最頂部
79 矢印
81,82 絶縁膜
168 側壁絶縁膜
171 金属シリサイド層
172,174 絶縁膜
ACT 活性領域
CA コンタクトホール
CAP キャップ絶縁膜
CB コンタクトホール
CC コンタクトホール(第2コンタクトホール)
CG 選択ゲート電極
CM コンタクトホール(第1コンタクトホール)
CNT コンタクトホール(第3コンタクトホール)
CT,CT1,CT2,CT3,CT4,CT101 コンタクトホール
CSL 電荷蓄積層
Dc 半導体領域
DMY ダミー部
Drm ドレイン領域
GHn,GHp,GLn,GLp ゲート電極
HNW nウェル
HPW pウェル
M1 第1層配線
MC メモリセル
MC1 メモリセル
MD,MS 半導体領域
MG メモリゲート電極
MG1,MG101 メモリゲート電極
MG1a,MG1b,MG1d,MG1e,MG101a コンタクト部
MM1,MM1a,MM1b,MM101 配線
NISO 埋め込みnウェル
NW nウェル
OP1 開口部
PAD パッド電極
PA プラグ
PB プラグ
PC プラグ(第2プラグ)
PLG プラグ(第3プラグ)
PG,PG1,PG2,PG3,PG4,PG101 プラグ
PM プラグ(第1プラグ)
PW pウェル
PW1 p型ウエル
Qnc 選択用nMIS
Qnm メモリ用nMIS
RP フォトレジストパターン
RP1,RP2,RP3,RP4 フォトレジストパターン(レジストパターン)
SD ソース・ドレイン領域
SG,SG1,SG2,SG101 選択ゲート電極
SGa コンタクト部
SP1 シリコンスペーサ
STI 素子分離部
Srm ソース領域
SW サイドウォール
Claims (9)
- 半導体基板と、
前記半導体基板の上部に形成された第1ゲート電極と、
前記第1ゲート電極の一方の側壁上に形成され、前記第1ゲート電極とともに前記半導体基板上に延在する第2ゲート電極と、
前記第2ゲート電極と前記半導体基板との間および前記第1ゲート電極と前記第2ゲート電極との間に形成された絶縁膜であって、その内部に電荷蓄積部を有する前記絶縁膜と、
前記半導体基板上に前記第1ゲート電極および前記第2ゲート電極を覆うように形成された層間絶縁膜と、
を有し、
前記第2ゲート電極は、前記第1ゲート電極の前記一方の側壁に隣接する位置から前記第1ゲート電極から離れる方向に延在する第1コンタクト部を含み、
前記第2ゲート電極の前記第1コンタクト部上の前記層間絶縁膜に第1コンタクトホールが形成され、前記第1コンタクトホールに埋め込まれた第1導電体部と前記第2ゲート電極の前記第1コンタクト部とが電気的に接続されており、
前記第1コンタクト部は、前記第1ゲート電極上には乗り上げておらず、
前記第2ゲート電極の上部に第1金属シリサイド層が形成され、
前記第1ゲート電極は、前記第1ゲート電極と前記第1ゲート電極上の第2絶縁膜との積層膜パターンとして形成されており、
前記第1ゲート電極は、前記第2ゲート電極から離れる方向に延在する第2コンタクト部を含み、
前記第2コンタクト部の上面の少なくとも一部は、前記第2絶縁膜で覆われておらず、第2金属シリサイド層が形成されており、
前記第1ゲート電極の上面のうち前記第2絶縁膜で覆われた部分には、前記第2金属シリサイド層が形成されておらず、
前記第1ゲート電極の前記第2コンタクト部上の前記層間絶縁膜に第2コンタクトホールが形成され、前記第2コンタクトホールに埋め込まれた第2導電体部と前記第1ゲート電極の前記第2コンタクト部とが電気的に接続されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2ゲート電極は、前記第1ゲート電極上に位置する部分を有していないことを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記層間絶縁膜上に形成され、前記第1導電体部を介して前記第1コンタクト部に電気的に接続された第1配線を有することを特徴とする半導体装置。 - 請求項3記載の半導体装置において、
前記半導体基板に形成された素子分離領域を有し、
前記第1コンタクト部は前記素子分離領域上に形成されていることを特徴とする半導体装置。 - 請求項4記載の半導体装置において、
前記第1コンタクト部以外の前記第2ゲート電極は、前記第1ゲート電極の一方の側壁上にサイドウォールスペーサ状に形成されていることを特徴とする半導体装置。 - 請求項5記載の半導体装置において、
前記第1コンタクト部は、前記第2ゲート電極が延在する方向に垂直な方向に延在していることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記第1コンタクト部の高さが、前記第2ゲート電極の高さ以下であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1ゲート電極の上面のうち、前記第2金属シリサイド層が形成された領域と、前記第2ゲート電極に隣接する側の端部との間には、前記第2絶縁膜で覆われた領域が介在していることを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記第1ゲート電極および前記第2ゲート電極は、前記半導体基板上に複数延在しており、
前記第2ゲート電極を挟まずに前記第1ゲート電極の延在方向に交差する方向に隣り合う前記第1ゲート電極同士は、前記第2コンタクト部の形成位置が、前記第1ゲート電極の延在方向にずれていることを特徴とする半導体装置。
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JP4647175B2 (ja) * | 2002-04-18 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
JP4477422B2 (ja) | 2004-06-07 | 2010-06-09 | 株式会社ルネサステクノロジ | 不揮発性半導体記憶装置の製造方法 |
JP4758625B2 (ja) * | 2004-08-09 | 2011-08-31 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4773073B2 (ja) | 2004-08-11 | 2011-09-14 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2007189063A (ja) | 2006-01-13 | 2007-07-26 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
JP5191633B2 (ja) * | 2006-04-04 | 2013-05-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP4817980B2 (ja) * | 2006-06-19 | 2011-11-16 | ルネサスエレクトロニクス株式会社 | 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法 |
JP2008166325A (ja) * | 2006-12-27 | 2008-07-17 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2010067645A (ja) * | 2008-09-08 | 2010-03-25 | Renesas Technology Corp | 半導体装置およびその製造方法 |
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US20130126960A1 (en) | 2013-05-23 |
US20150054045A1 (en) | 2015-02-26 |
US20110095348A1 (en) | 2011-04-28 |
JP2011222938A (ja) | 2011-11-04 |
US8373216B2 (en) | 2013-02-12 |
US8896053B2 (en) | 2014-11-25 |
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