JP5288877B2 - 不揮発性半導体記憶装置 - Google Patents
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- JP5288877B2 JP5288877B2 JP2008123023A JP2008123023A JP5288877B2 JP 5288877 B2 JP5288877 B2 JP 5288877B2 JP 2008123023 A JP2008123023 A JP 2008123023A JP 2008123023 A JP2008123023 A JP 2008123023A JP 5288877 B2 JP5288877 B2 JP 5288877B2
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- 239000004065 semiconductor Substances 0.000 title claims description 138
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- 239000011229 interlayer Substances 0.000 description 56
- 238000004519 manufacturing process Methods 0.000 description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 23
- 229910052814 silicon oxide Inorganic materials 0.000 description 23
- 238000000034 method Methods 0.000 description 15
- 229910021332 silicide Inorganic materials 0.000 description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- 239000005368 silicate glass Substances 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- 229910052698 phosphorus Inorganic materials 0.000 description 7
- 239000011574 phosphorus Substances 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 4
- 101000739175 Trichosanthes anguina Seed lectin Proteins 0.000 description 3
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
(不揮発性半導体記憶装置の回路構成)
図1は、本発明の実施の形態に係る不揮発性半導体記憶装置の回路図である。本実施の形態に係る不揮発性半導体記憶装置は、いわゆるNAND型フラッシュメモリである。
次に、図2A及び図2Bを参照して、本実施の形態に係る不揮発性半導体記憶装置の具体的構成について説明する。図2Aは、本実施の形態に係る不揮発性半導体記憶装置の上面図であり、図2Bは、図2AのA−A’断面図である。なお、図2Aは、上部に設けられたビット線BL(後述する配線層133)、ソース線SL(後述する配線層135)及び後述する絶縁層131を省略して示している。図2A及び図2Bにおいて、上述したビット線BLの延びる方向をX方向とし、上述したソース線SL(後述する配線層134)の延びる方向をY方向とする。
次に、図3A〜図17A、図3B〜図17Bを参照して、本実施の形態に係る不揮発性半導体記憶装置の製造工程について説明する。図3A〜図17Aは、製造工程における上面図であり、図3B〜図17Bは、製造工程におけるA−A’方向の断面図である。
次に、本実施の形態に係る不揮発性半導体記憶装置の効果について説明する。本実施の形態に係る不揮発性半導体記憶装置は、メモリセルMCを縦型にし、且つ積層しているために、NAND型フラッシュメモリの面積を削減することができる。
Claims (3)
- 第1選択トランジスタ及び第2選択トランジスタが半導体基板上に形成された第1積層部と、
前記第1積層部の上面に設けられ且つ第1絶縁層及び第1導電層が交互に積層された第2積層部と
を備え、
前記第2積層部は、
前記第1絶縁層の側壁及び前記第1導電層の側壁に接して設けられた第2絶縁層と、
前記第2絶縁層に接して設けられ且つ電荷を蓄積する電荷蓄積層と、
前記電荷蓄積層に接して設けられた第3絶縁層と、
前記第3絶縁層に接して積層方向に延びるように設けられ且つ一端が第1選択トランジスタの一の拡散層に接続し他端が第2選択トランジスタの一の拡散層に接続するように形成された第1半導体層と
を備え、
前記第1選択トランジスタ及び前記第2選択トランジスタは、前記半導体基板上に前記拡散層を有するプレーナ型のトランジスタである
ことを特徴とする不揮発性半導体記憶装置。 - 前記第1半導体層は、前記積層方向の上方で折り返し下方で前記第1選択トランジスタ及び第2選択トランジスタにそれぞれ接する逆U字形状の断面形状を有するように形成された
ことを特徴とする請求項1記載の不揮発性半導体記憶装置。 - 前記第2積層部の上部に位置する第3積層部をさらに備え、
前記第3積層部は、
前記第1選択トランジスタの他の拡散層に接続された第1コンタクトプラグ層と、
前記第1コンタクトプラグ層に接して設けられ且つ前記積層方向と直交する第1方向に延びる第1配線層と、
前記第2選択トランジスタの他の拡散層に接続された第2コンタクトプラグ層と、
前記第2コンタクトプラグ層に接して設けられ且つ前記第1方向と直交する第2方向に延びる第2配線層と
を備える
ことを特徴とする請求項1又は2記載の不揮発性半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008123023A JP5288877B2 (ja) | 2008-05-09 | 2008-05-09 | 不揮発性半導体記憶装置 |
US12/434,305 US8026546B2 (en) | 2008-05-09 | 2009-05-01 | Nonvolatile semiconductor memory device and method of manufacturing the same |
US13/226,224 US8237218B2 (en) | 2008-05-09 | 2011-09-06 | Nonvolatile semiconductor memory device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008123023A JP5288877B2 (ja) | 2008-05-09 | 2008-05-09 | 不揮発性半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009272513A JP2009272513A (ja) | 2009-11-19 |
JP5288877B2 true JP5288877B2 (ja) | 2013-09-11 |
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JP2008123023A Expired - Fee Related JP5288877B2 (ja) | 2008-05-09 | 2008-05-09 | 不揮発性半導体記憶装置 |
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US (2) | US8026546B2 (ja) |
JP (1) | JP5288877B2 (ja) |
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JPH1093083A (ja) * | 1996-09-18 | 1998-04-10 | Toshiba Corp | 半導体装置の製造方法 |
WO2004090984A1 (en) * | 2003-04-03 | 2004-10-21 | Kabushiki Kaisha Toshiba | Phase change memory device |
JP2006073939A (ja) * | 2004-09-06 | 2006-03-16 | Toshiba Corp | 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法 |
JP2006128390A (ja) * | 2004-10-28 | 2006-05-18 | Toshiba Corp | 半導体装置及びその製造方法 |
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JP4822841B2 (ja) | 2005-12-28 | 2011-11-24 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
JP2007317874A (ja) * | 2006-05-25 | 2007-12-06 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP5010192B2 (ja) * | 2006-06-22 | 2012-08-29 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP5100080B2 (ja) * | 2006-10-17 | 2012-12-19 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
JP4772656B2 (ja) * | 2006-12-21 | 2011-09-14 | 株式会社東芝 | 不揮発性半導体メモリ |
JP5016928B2 (ja) * | 2007-01-10 | 2012-09-05 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
FR2913523B1 (fr) * | 2007-03-09 | 2009-06-05 | Commissariat Energie Atomique | Disposistif de memorisation de donnees multi-niveaux a materiau a changement de phase |
JP2008277543A (ja) * | 2007-04-27 | 2008-11-13 | Toshiba Corp | 不揮発性半導体記憶装置 |
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US8026546B2 (en) | 2011-09-27 |
US20090278193A1 (en) | 2009-11-12 |
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