JP5059204B2 - 半導体記憶装置の製造方法 - Google Patents
半導体記憶装置の製造方法 Download PDFInfo
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- JP5059204B2 JP5059204B2 JP2011034963A JP2011034963A JP5059204B2 JP 5059204 B2 JP5059204 B2 JP 5059204B2 JP 2011034963 A JP2011034963 A JP 2011034963A JP 2011034963 A JP2011034963 A JP 2011034963A JP 5059204 B2 JP5059204 B2 JP 5059204B2
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- memory cell
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 230000015654 memory Effects 0.000 claims abstract description 137
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 42
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 42
- 230000002093 peripheral effect Effects 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 3
- 239000011800 void material Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 description 15
- 239000003795 chemical substances by application Substances 0.000 description 14
- 239000010410 layer Substances 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
半導体基板上に配列された複数のメモリセルのゲートおよび選択トランジスタのゲートを形成し、
隣接する前記メモリセル間の第1の間隙および隣接する前記メモリセルと前記選択トランジスタとの間の第2の間隙を、シリコン窒化膜を用いて充填し、
隣接する前記選択トランジスタ間の第3の間隙に堆積された前記シリコン窒化膜を除去し、
前記第3の間隙内において、前記選択トランジスタのゲートの側面にシリコン酸化膜を用いてスペーサを形成し、
前記第3の間隙を絶縁膜で充填し、
前記第3の間隙をマスク材で被覆し、
前記スペーサを残しつつ、前記第3の間隙を前記マスク材で被覆した状態で、前記第1の間隙および前記第2の間隙に充填された前記シリコン窒化膜を選択的に除去し、
前記第1の間隙および前記第2の間隙にシリコン酸化膜を堆積することによって、前記第1の間隙および前記第2の間隙内に空隙を形成することを具備する。
Claims (3)
- 半導体基板上に配列された複数のメモリセルのゲートおよび選択トランジスタのゲートを形成し、
隣接する前記メモリセル間の第1の間隙および隣接する前記メモリセルと前記選択トランジスタとの間の第2の間隙を、シリコン窒化膜を用いて充填し、
隣接する前記選択トランジスタ間の第3の間隙に堆積された前記シリコン窒化膜を除去し、
前記第3の間隙内において、前記選択トランジスタのゲートの側面にシリコン酸化膜を用いてスペーサを形成し、
前記第3の間隙を絶縁膜で充填し、
前記第3の間隙をマスク材で被覆し、
前記スペーサを残しつつ、前記第3の間隙を前記マスク材で被覆した状態で、前記第1の間隙および前記第2の間隙に充填された前記シリコン窒化膜を選択的に除去し、
前記第1の間隙および前記第2の間隙にシリコン酸化膜を堆積することによって、前記第1の間隙および前記第2の間隙内に空隙を形成することを具備する半導体記憶装置の製造方法。 - 前記スペーサの形成時に、複数の前記メモリセルを含むメモリセルアレイを制御する周辺回路領域にあるトランジスタのゲート側面にも前記スペーサを形成することを特徴とする請求項1に記載の半導体記憶装置の製造方法。
- 前記マスク材は、前記周辺回路領域をも被覆することを特徴とする請求項2に記載の半導体記憶装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011034963A JP5059204B2 (ja) | 2011-02-21 | 2011-02-21 | 半導体記憶装置の製造方法 |
US13/401,126 US8957469B2 (en) | 2011-02-21 | 2012-02-21 | Semiconductor storage device and manufacturing method of semiconductor storage device |
Applications Claiming Priority (1)
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JP2011034963A JP5059204B2 (ja) | 2011-02-21 | 2011-02-21 | 半導体記憶装置の製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2012166250A Division JP5613203B2 (ja) | 2012-07-26 | 2012-07-26 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2012174869A JP2012174869A (ja) | 2012-09-10 |
JP5059204B2 true JP5059204B2 (ja) | 2012-10-24 |
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JP2011034963A Expired - Fee Related JP5059204B2 (ja) | 2011-02-21 | 2011-02-21 | 半導体記憶装置の製造方法 |
Country Status (2)
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US (1) | US8957469B2 (ja) |
JP (1) | JP5059204B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9136128B2 (en) | 2011-08-31 | 2015-09-15 | Micron Technology, Inc. | Methods and apparatuses including memory cells with air gaps and other low dielectric constant materials |
US9608065B1 (en) | 2016-06-03 | 2017-03-28 | International Business Machines Corporation | Air gap spacer for metal gates |
US10680006B2 (en) | 2017-08-11 | 2020-06-09 | Micron Technology, Inc. | Charge trap structure with barrier to blocking region |
US10164009B1 (en) | 2017-08-11 | 2018-12-25 | Micron Technology, Inc. | Memory device including voids between control gates |
US10446572B2 (en) | 2017-08-11 | 2019-10-15 | Micron Technology, Inc. | Void formation for charge trap structures |
US10453855B2 (en) | 2017-08-11 | 2019-10-22 | Micron Technology, Inc. | Void formation in charge trap structures |
JP2020031113A (ja) * | 2018-08-21 | 2020-02-27 | キオクシア株式会社 | 半導体記憶装置およびその製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3205306B2 (ja) * | 1998-12-08 | 2001-09-04 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
US6894341B2 (en) * | 2001-12-25 | 2005-05-17 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method |
TWI252565B (en) * | 2002-06-24 | 2006-04-01 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
JP5525695B2 (ja) | 2007-06-20 | 2014-06-18 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP4703669B2 (ja) | 2008-02-18 | 2011-06-15 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
JP2009212218A (ja) | 2008-03-03 | 2009-09-17 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP2009231300A (ja) | 2008-03-19 | 2009-10-08 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP2009277897A (ja) * | 2008-05-15 | 2009-11-26 | Toshiba Corp | 半導体記憶装置の製造方法 |
JP2010080853A (ja) * | 2008-09-29 | 2010-04-08 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
JP2010087160A (ja) * | 2008-09-30 | 2010-04-15 | Toshiba Corp | 不揮発性半導体記憶装置の製造方法および不揮発性半導体記憶装置 |
JP4923078B2 (ja) | 2009-03-23 | 2012-04-25 | 株式会社東芝 | 半導体記憶装置及びその半導体記憶装置の製造方法 |
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2011
- 2011-02-21 JP JP2011034963A patent/JP5059204B2/ja not_active Expired - Fee Related
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2012
- 2012-02-21 US US13/401,126 patent/US8957469B2/en not_active Expired - Fee Related
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US20120213006A1 (en) | 2012-08-23 |
US8957469B2 (en) | 2015-02-17 |
JP2012174869A (ja) | 2012-09-10 |
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