JP2014116342A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 238000002955 isolation Methods 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
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- 239000007789 gas Substances 0.000 description 21
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 238000005530 etching Methods 0.000 description 9
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- 238000010438 heat treatment Methods 0.000 description 7
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- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
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- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 1
- 239000005977 Ethylene Substances 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
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- -1 for example Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
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- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
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- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
Abstract
【構成】
実施形態の半導体装置の製造方法では、半導体基板上に、炭素(C)を上部に含有するシリコン(Si)膜を形成する工程と、第1の領域においてSi膜の寸法幅が狭く、第2の領域においてSi膜の寸法幅が広くなるように前記Si膜と前記半導体基板とに対して素子分離を行う工程と、素子分離後、少なくとも前記第1の領域において前記Si膜の側面を露出させる工程と、前記第1の領域における前記Si膜の側面からボロン(B)を前記Si膜内へと拡散させる工程と、を備えたことを特徴とする。
【選択図】図1
Description
以下、第1の実施形態は、シリコン(Si)膜へのp型の不純物のドーピングをガスフェーズドーピング法により行う場合について説明する。
Claims (5)
- 半導体基板上に、炭素(C)を上部に含有するシリコン(Si)膜を形成する工程と、
第1の領域でSi膜の寸法幅が狭く、第2の領域でSi膜の寸法幅が広くなるように前記Si膜と前記半導体基板とに対して素子分離を行う工程と、
素子分離後、前記第1と第2の領域のうち、前記第1の領域のみ前記Si膜の側面を露出させるとともに、前記Si膜における前記炭素を含有する上部の部分を除去する工程と、
ガスフェーズドーピング法を用いて、前記第1の領域における前記Si膜の側面からボロン(B)を前記Si膜内へと拡散させる工程と、
を備え、
前記第1の領域は、メモリセル領域であり、第2の領域は、メモリセルの周辺回路領域であることを特徴とする半導体装置の製造方法。 - 半導体基板上に、炭素(C)を上部に含有するシリコン(Si)膜を形成する工程と、
第1の領域でSi膜の寸法幅が狭く、第2の領域でSi膜の寸法幅が広くなるように前記Si膜と前記半導体基板とに対して素子分離を行う工程と、
素子分離後、少なくとも前記第1の領域で前記Si膜の側面を露出させる工程と、
前記第1の領域における前記Si膜の側面からボロン(B)を前記Si膜内へと拡散させる工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 前記第1と第2の領域のうち、前記第1の領域のみ前記Si膜の側面を露出させることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記Si膜の側面を露出させる際、前記第1の領域では、さらに、前記Si膜における前記炭素を含有する上部の部分を除去することを特徴とする請求項2又は3記載の半導体装置の製造方法。
- 前記Bを拡散させる際、ガスフェーズドーピング法を用いることを特徴とする請求項2〜4いずれか記載の半導体装置の製造方法。
Priority Applications (2)
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JP2012267056A JP2014116342A (ja) | 2012-12-06 | 2012-12-06 | 半導体装置の製造方法 |
US13/896,808 US9281383B2 (en) | 2012-12-06 | 2013-05-17 | Method for fabricating a semiconductor device |
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JP2012267056A JP2014116342A (ja) | 2012-12-06 | 2012-12-06 | 半導体装置の製造方法 |
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JP2014116342A true JP2014116342A (ja) | 2014-06-26 |
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JP2012267056A Abandoned JP2014116342A (ja) | 2012-12-06 | 2012-12-06 | 半導体装置の製造方法 |
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JP (1) | JP2014116342A (ja) |
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JP2014116342A (ja) * | 2012-12-06 | 2014-06-26 | Toshiba Corp | 半導体装置の製造方法 |
KR20170007928A (ko) * | 2015-07-13 | 2017-01-23 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 소자 제조 방법 |
TWI691019B (zh) | 2019-03-19 | 2020-04-11 | 華邦電子股份有限公司 | 快閃記憶體裝置及其製造方法 |
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JPH0878674A (ja) * | 1993-09-16 | 1996-03-22 | Mitsubishi Electric Corp | 半導体装置およびその製造方法ならびにバイポーラトランジスタ |
JP2011176207A (ja) * | 2010-02-25 | 2011-09-08 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
JP2012038835A (ja) * | 2010-08-05 | 2012-02-23 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
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