JP5376789B2 - 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の制御方法 - Google Patents
不揮発性半導体記憶装置及び不揮発性半導体記憶装置の制御方法 Download PDFInfo
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Description
図1は、本発明の実施形態1に係る不揮発性半導体記憶装置100の概略構成図を示す。本発明の実施形態1に係る不揮発性半導体記憶装置100は、メモリ素子領域2、ワード線駆動回路3、ソース側選択ゲート線(SGS)駆動回路4、ドレイン側選択ゲート線(SGD)駆動回路5等を備えている。メモリ素子領域2には、半導体基板の主平面と垂直な方向に複数積層されたワード線WL7と、このワード線WL7を積層部の上面から前記半導体基板に到達する複数の半導体層(後述の図2の符号301〜304参照。)が形成されている。メモリ素子領域2の構成については後述する。
本発明の実施形態1では、マーカ層の材料を他の絶縁層(または導電体層)の材料と変更する場合に説明した。本発明の実施形態2では、絶縁層(または導電体層)の層の厚さを他の絶縁層(または導電体層)と変えることで、マーカ層を形成する場合について説明する。例えば、マーカ層になる絶縁層(または導電体層)を他の絶縁層(または導電体層)よりも薄くしたり、逆に厚くしたりする。また、本実施形態では、マーカ層になる絶縁層(または導電体層)は、他の絶縁層(または導電体層)と異なるようにしてもよい。ただし、導電体層と絶縁層とを積層する際の工程数を考えると、マーカ層になる絶縁層(または導電体層)は、他の絶縁層(または導電体層)と同じ材料を用いて厚さを変えてもよい。
本発明の実施形態2では、マーカ層となる絶縁層の厚さを他の絶縁層よりも大きくする場合について、主に説明した。本発明の実施形態3では、導電体層をマーカ層とし、マーカ層の厚さを他の導電体層よりも厚くする場合について説明する。なお、本実施形態では、マーカ層となる導電体層の材料を他の導電体層の材料と変えるようにしてもよい。
202、203、204、205、206、207、208、209、210、211、212、213、214、215、216、217、1601…導電体層
218、219、220、221、222、223、224、225、226、227、228、229、230、231、232、233、1201、1202,1203、1301…絶縁層
Claims (5)
- 基板層と、
前記基板層の上に交互に積層され二次元状に広がる複数の導電体層及び複数の絶縁層を有し、前記複数の導電体層又は前記複数の絶縁層のうち少なくとも一層が他の前記複数の導電体層又は前記複数の絶縁層とは材料が異なり、かつ、物理的性質が異なる層である積層部と、
前記積層部の上面から前記基板層に到達し、前記複数の導電体層及び前記複数の絶縁層に周囲を囲まれた複数のメモリプラグホールによって露出された前記導電体層及び前記絶縁層の表面に形成された半導体層と、
前記半導体層と前記導電体層の交点に形成された電気的に書き換え可能な複数のメモリ素子であって、前記複数のメモリ素子はそれぞれ制御電極を有し、前記制御電極それぞれが前記複数の導電体層にそれぞれ接続されている複数のメモリ素子を有するメモリストリングと、
を有し、
前記物理的性質が異なる層は、前記複数のメモリプラグホールを形成したときのエッチングストッパ層として機能したことを特徴とする不揮発性半導体記憶装置。 - 前記物理的性質が異なる層は、
SEMまたはTEMにより他の層と区別することができることを特徴とする請求項1に記載の不揮発性半導体記憶装置。 - 基板層と、
前記基板層の上に交互に積層され二次元状に広がる複数の導電体層及び複数の絶縁層を有し、前記複数の導電体層又は前記複数の絶縁層のうち少なくとも一層が他の前記複数の導電体層又は前記複数の絶縁層とは材料が異なり、かつ、膜厚が異なる層である積層部と、
前記積層部の上面から前記基板層に到達し、前記複数の導電体層及び前記複数の絶縁層に周囲を囲まれた複数のメモリプラグホールによって露出された前記導電体層及び前記絶縁層の表面に形成された半導体層と、
前記半導体層と前記導電体層の交点に形成された電気的に書き換え可能な複数のメモリ素子であって、前記複数のメモリ素子はそれぞれ制御電極を有し、前記制御電極それぞれが前記複数の導電体層にそれぞれ接続されている複数のメモリ素子を有するメモリストリングと、
を有し、
前記膜厚が異なる層は、前記複数のメモリプラグホールを形成するときのエッチングストッパ層として機能したことを特徴とする不揮発性半導体記憶装置。 - 基板層と、
前記基板層の上に交互に積層され二次元状に広がる複数の導電体層及び複数の絶縁層を有し、前記複数の導電体層のうち少なくとも一層が他の前記複数の導電体層とは材料が異なり、かつ、膜厚が異なる導電体層である積層部と、
前記積層部の上面から前記基板層に到達し、前記複数の導電体層及び前記複数の絶縁層に周囲を囲まれた複数のメモリプラグホールによって露出された前記導電体層及び前記絶縁層の表面に形成された半導体層と、
前記半導体層と前記導電体層の交点に形成された電気的に書き換え可能な複数のメモリ素子であって、前記複数のメモリ素子はそれぞれ制御電極を有し、前記制御電極それぞれが前記複数の導電体層にそれぞれ接続されている複数のメモリ素子を有するメモリストリングとを有し、
膜厚が異なる前記導電体層はトランジスタの制御ゲートとして機能し、
前記膜厚が異なる前記導電体層は、前記複数のメモリプラグホールを形成するときのエッチングストッパ層として機能したことを特徴とする不揮発性半導体記憶装置。 - 基板層と、
前記基板層の上に交互に積層された複数の導電体層及び複数の絶縁層を有し、前記複数の導電体層のうち少なくとも一層が他の前記複数の導電体層の厚さより大きく、かつ、材料が異なるマーカ層である積層部と、
前記積層部の上面から前記基板層に到達する複数のメモリプラグホールによって露出された前記導電体層及び前記絶縁層の表面に形成された半導体層と、
前記半導体層と前記導電体層の交点に形成された電気的に書き換え可能な複数のメモリ素子であって、前記複数のメモリ素子はそれぞれ制御電極を有し、前記制御電極それぞれが前記複数の導電体層にそれぞれ接続されている複数のメモリ素子を有するメモリストリングと、
前記メモリストリングの端部に配置された第1及び第2の選択トランジスタと、
前記マーカ層と前記半導体層の交点に形成された第3の選択トランジスタとを有し、
前記メモリストリングは、前記第1トランジスタと前記第2トランジスタとに接続される端部を有する不揮発性半導体記憶装置の制御方法であって、
前記第1の選択トランジスタをカットオフ状態とし、
前記第2の選択トランジスタと前記第3の選択トランジスタをオン状態として、前記メモリストリングに電荷を充電した後、
前記第3の選択トランジスタをカットオフ状態にし、
前記第3の選択トランジスタと第2の選択トランジスタとの間のメモリ素子にデータ書き込みを行う、
ことを特徴とする不揮発性半導体記憶装置の制御方法。
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JP2007259827A JP5376789B2 (ja) | 2007-10-03 | 2007-10-03 | 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の制御方法 |
CN2008101785691A CN101409291B (zh) | 2007-10-03 | 2008-09-27 | 非易失性半导体存储装置以及控制非易失性半导体存储装置的方法 |
TW097137820A TWI380411B (en) | 2007-10-03 | 2008-10-01 | Nonvolatile semiconductor storage device, and method for controlling nonvolatile semiconductor storage device |
US12/244,307 US7884417B2 (en) | 2007-10-03 | 2008-10-02 | Nonvolatile semiconductor storage device, and method for controlling nonvolatile semiconductor storage device |
KR1020080097301A KR100983451B1 (ko) | 2007-10-03 | 2008-10-02 | 비휘발성 반도체 기억 장치 및 비휘발성 반도체 기억 장치를 제어하기 위한 방법 |
US12/974,128 US8557695B2 (en) | 2007-10-03 | 2010-12-21 | Nonvolatile semiconductor storage device, and method for controlling nonvolatile semiconductor storage device |
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JP4772656B2 (ja) * | 2006-12-21 | 2011-09-14 | 株式会社東芝 | 不揮発性半導体メモリ |
JP2009016400A (ja) | 2007-06-29 | 2009-01-22 | Toshiba Corp | 積層配線構造体及びその製造方法並びに半導体装置及びその製造方法 |
US8044448B2 (en) * | 2008-07-25 | 2011-10-25 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
KR101468595B1 (ko) * | 2008-12-19 | 2014-12-04 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
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US8644046B2 (en) * | 2009-02-10 | 2014-02-04 | Samsung Electronics Co., Ltd. | Non-volatile memory devices including vertical NAND channels and methods of forming the same |
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US7884417B2 (en) | 2011-02-08 |
KR20090034776A (ko) | 2009-04-08 |
US8557695B2 (en) | 2013-10-15 |
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