US20170133099A1 - 3d nand array with divided string architecture - Google Patents

3d nand array with divided string architecture Download PDF

Info

Publication number
US20170133099A1
US20170133099A1 US15/348,869 US201615348869A US2017133099A1 US 20170133099 A1 US20170133099 A1 US 20170133099A1 US 201615348869 A US201615348869 A US 201615348869A US 2017133099 A1 US2017133099 A1 US 2017133099A1
Authority
US
United States
Prior art keywords
cell string
cell
internal select
select gates
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/348,869
Inventor
Fu-Chang Hsu
Original Assignee
Fu-Chang Hsu
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US201562253683P priority Critical
Application filed by Fu-Chang Hsu filed Critical Fu-Chang Hsu
Priority to US15/348,869 priority patent/US20170133099A1/en
Publication of US20170133099A1 publication Critical patent/US20170133099A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11521Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
    • H01L27/11524Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11568Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
    • H01L27/1157Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]

Abstract

A 3D NAND array with divided string architecture. In one aspect, an apparatus includes a plurality of charge storing devices connected to form a cell string. The apparatus also includes one or more internal select gates connected between selected charge storing devices in the cell string. The one or more internal select gates divide the cell string into two or more segments of charge storing devices. Selectively enabling and disabling the one or more internal select gates during programming operates to isolate one or more selected segments to reduce program-disturb to remaining segments. In another embodiment, a method is provided for programming a memory cell of a cell string having internal select gates that isolate the memory cell to reduce the effects of program-disturb. In another embodiment, multiple memory cells of a cell string having internal select gates are programmed with reduced program-disturb.

Description

    PRIORITY
  • This application claims the benefit of priority based upon U.S. Provisional Patent Application having Application No. 62/253,683, filed on Nov. 11, 2015, and entitled “3D NAND ARRAY WITH DIVIDED STRING ARCHITECTURE,” which is hereby incorporated herein by reference in its entirety.
  • FIELD OF THE INVENTION
  • The exemplary embodiments of the present invention relate generally to the field of semiconductors and integrated circuits, and more specifically to memory and storage devices.
  • BACKGROUND OF THE INVENTION
  • Memory devices are widely used in a variety of digital electronics. One type of memory device is a dynamic random access memory (DRAM) device. DRAM devices can be used to form low cost high density memory arrays. For example, one of the largest applications for DRAM is as the main memory in modern computers. Unfortunately, due to the dynamic nature of its configuration, the information stored in DRAM will eventually degrade unless periodic memory refresh cycles are performed. Thus, though DRAM memory cells may be small in size, they may also consume large amounts of power due to the refresh requirements.
  • Another type of memory device is a non-volatile memory (NVM) device that has long data retention without the use of refresh cycles. This memory may also be referred to as static memory. In contrast to DRAM, NVM memory devices maybe more expensive but consume less power. Some examples of non-volatile memory include read-only memory (ROM) and Flash memory.
  • System designers therefore need to select the appropriate memory type for the systems they are designing. This means accounting for the trade-offs between size, cost, speed, power consumption, and volatility of the different memory types. In some cases, more resources (e.g., size and cost) are allocated for memory where multiple types of memory are needed to obtain the desired memory characteristics.
  • FIG. 1 shows a cross-section view of a conventional 3D NAND cell string 100 for use in a flash memory array. The cell string 100 includes a metal bit line 101 and a polysilicon or silicon channel 102. The cell string 100 also includes source 103 and drain 104 regions that may have the opposite types of doping. A silicon source line 105, a drain select gate (DSG) 106 and source select gate (SSG) 107 are also included. Memory cells are formed where word lines (WL0-WLn) (e.g., 108 and 109) intersect with a charge-trapping layer. For example, the cell string 100 also includes a gate oxide layer 110 and a charge-trapping layer 111, such as an Oxide-Nitride-Oxide (ONO) layer that traps electric charge to represent the cell's data. FIG. 2 shows a circuit representation of the 3D NAND cell string 100.
  • One significant drawback of conventional 3D NAND array structures that utilize the architecture of the cell string 100 is that of “program-disturb.” During programming, a selected word line (e.g., WL0) is supplied with a high voltage, such as +10V to +20V. All the unselected word lines (e.g., WL1-WLn) are supplied with a medium high voltage, such as +5V to +10V. This will boost the channel 102 of the cells to about +5V to +10V to program-inhibit the cell. However, this condition will cause significant program-disturb to some or all of the cells associated with the unselected word lines.
  • Furthermore, as the density of the 3D NAND array is increased, more word line layers will be stacked in one string, and thus the problem of program-disturb is increased. This problem will become even more severe for Multi-Level Cell (MLC) configurations because each level has a narrower voltage threshold (Vt) window.
  • Thus, the program-disturb problem has become a technical challenge for increasing the density of 3D NAND memory. It is therefore desirable to have a mechanism that overcomes the problem of program-disturb associated with convention memory arrays.
  • SUMMARY
  • A novel 3D NAND array with divided string architecture is disclosed to address the issue of program-disturb in 3D memory arrays. In various exemplary embodiments, the divided string architecture enables more layers to be stacked in a 3D array without increasing the risk of program-disturb.
  • In various exemplary embodiments, the divided string architecture includes internal select gates within the cell string that divide the cell string into segments. Each segment contains a selected number of memory cells. During programming, the internal select gates can be enabled or disabled to isolate selected segments of the cell string. When programming an isolated segment, the problem of program-disturb for the remaining segments is reduced or eliminated. Thus, even with memory cell strings having many layers, the effects of program-disturb can be mitigated. In addition to the novel cell structure, several novel programming bias conditions are disclosed that allow programming of cells in one or multiple segments while reducing or eliminating the effects of program-disturb on the remaining segments of the cell string.
  • In one aspect, an apparatus is provided that includes a plurality of charge storing devices connected to form a cell string. The apparatus also includes one or more internal select gates connected between selected charge storing devices in the cell string. The one or more internal select gates divide the cell string into two or more segments of charge storing devices. Selectively enabling and disabling the one or more internal select gates during programming operates to isolate one or more selected segments to reduce program-disturb to remaining segments.
  • In one aspect, a method is provided for programming memory cells of a cell string having internal select gates that divides the cell string into segments. The method includes identifying a segment of the cell string containing a memory cell to be programmed and applying a first voltage to a source selected gate of the cell string. The method also includes applying a second voltage to a drain select gate and the internal select gates of the cell string, and applying a third voltage to a bit line of the cell string. The method also includes ramping up a fourth voltage to a selected word line of the segment, and ramping up a fifth voltage to unselected word lines of the segment.
  • Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The exemplary embodiments of the present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.
  • FIGS. 1-2 show a conventional 3D NAND cell string and an equivalent circuit;
  • FIGS. 3A-B show exemplary embodiments of a divided linear cell string structure and an equivalent circuit in accordance with the present invention;
  • FIGS. 4A-B show exemplary embodiments of a divided linear cell string structure and an equivalent circuit in accordance with the present invention;
  • FIGS. 5A-B show exemplary embodiments of a divided non-linear cell string structure constructed using a folded ‘U’ shape string and an equivalent circuit in accordance with the present invention;
  • FIGS. 6A-B show exemplary embodiments of a divided non-linear cell string structure constructed using a folded ‘U’ shape string and an equivalent circuit in accordance with the present invention;
  • FIG. 7 shows an exemplary embodiment of a 3D NAND array structure constructed using the novel linear cell string shown in FIG. 3A;
  • FIG. 8 shows an exemplary embodiment of a 3D NAND array structure constructed using the novel non-linear (U-shaped) cell string structure shown in FIG. 5A;
  • FIG. 9 shows an exemplary embodiment of a 3D NAND array structure constructed using horizontal cell strings comprising the novel linear cell string structure shown in FIG. 3A;
  • FIG. 10 shows an exemplary embodiment of method for programming a single memory element in a single segment in a cell string with reduced program-disturb;
  • FIG. 11 shows an exemplary embodiment of method for programming multiple memory elements in multiple segments in a cell string with reduced program-disturb; and
  • FIG. 12 shows an exemplary timing diagram illustrating signal timing waveforms to program multiple memory elements in multiple segments in a cell string with reduced program-disturb.
  • DETAILED DESCRIPTION
  • Exemplary embodiments of the present invention are described herein in the context of a process, device, method, and apparatus for providing a novel dual function hybrid memory cell.
  • Those of ordinary skilled in the art will realize that the following detailed description is illustrative only and is not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to skilled persons having the benefit of this disclosure. Reference will now be made in detail to implementations of the exemplary embodiments of the present invention as illustrated in the accompanying drawings. The same reference indicators or numbers will be used throughout the drawings and the following detailed description to refer to the same or like parts.
  • It should be noted that the exemplary embodiments are not limited to ONO cells only and the disclosed aspects can be applied to other types of charge-trapping cells. To realize the low-cost, high-flexibility memory arrays using the disclosed ONO or other charge-trapping type of cells, the exemplary embodiments disclose a novel cell string and novel operating bias conditions. These embodiments and conditions allow novel cell strings and corresponding 3D NAND arrays to operate without experiencing program-disturb.
  • In various exemplary embodiments, a novel 3D array structure with divided cell string architecture is disclosed. For example, each cell string of a 3D NAND array includes internal select gates that divided the cell string into multiple segments. Each segment contains multiple memory cells. During programming, high voltage is applied only to the selected segment. The unselected segments remain at lower voltages; thus the program-disturb problem for unselected segments is reduced or eliminated.
  • FIGS. 3A-B show exemplary embodiments of a divided linear cell string structure 300 and an equivalent circuit 316 in accordance with the present invention. As illustrated in FIGS. 3A-B, the 3D NAND cell string 300 comprises a metal bit line 301 and a polysilicon or silicon channel 302. Also shown are source 303 and drain 304 junctions that may have the opposite type of doping as the silicon channel 302. A polysilicon or silicon source line 305, a DSG 306, and a source select gate SSG 307 are also shown. The string 300 is divided into multiple segments 309 a, 309 b, and 309 c by “internal select gates” 308 a and 308 b. In an exemplary embodiment, the internal select gates 308 a and 308 b are enhancement devices having channel lengths that are longer than the channels of the memory cells. The internal select gates 308 a and 308 b are connected to control signals ISG0 and ISG1, respectively, as shown in the circuit 316. In an exemplary embodiment, memory controller 320 operates to generate the control signals ISG0 and ISG1 as well as other memory control signals.
  • The first segment 309 a contains multiple word lines, WL0 310 a to WLk 310 b. The second segment 309 b contains WLk+1 311 a to WLm 311 b. The third segment 309 c contains WLm+1 312 a to WLn 312 b. It should be noted that the segments 309 a, 309 b, and 309 c may have the same or a different number of word lines (e.g., memory cells). The internal select gates 308 a and 308 b may have longer channel length than the memory cells to sustain high voltage during program operations. In an exemplary embodiment, the internal select gates 308 a and 308 b may be shared with the adjacent NAND strings, or decoded for each NAND string. For example, as shown in FIG. 8, internal select gate 805 a can be used to control (divide) an individual cell string and internal select gate 805 d is shared and can be used to control (divide) multiple cell strings. In addition, gate oxide layer 313 a, 313 b, 313 c, and 313 d and charge-trapping layers 314 a, 314 b, and 314 c, such as ONO layers, are also shown.
  • It should also be noted that within the scope of the exemplary embodiments, the cell structures may be modified according to different process technologies. For example, in another embodiment, the cell string 300 may contain a “core” comprising an insulator layer such as oxide, or vacant space in the center of the channel. In another embodiment, the cell string 300 may use other NVM storage elements, such as floating gates (FG), Ferroelectric layer, resistive switching material, and/or other storage elements to store data. In another embodiment, the cell string 300 may contain multiple charge trapping layers such as Oxide-Nitride-Oxide-Nitride-Oxide (ONONO) or Oxide-Nitride-Oxide-Nitride (ONON) as storage elements. In another embodiment, the select gates 308 a and 308 b and the cells may be formed by ‘junction-less’ transistors, where the source and drain junctions 303 and 304 may be removed and the channel 302 is heavily doped. Moreover, the select gates 308 a and 308 b and memory cells may be formed by either PMOS or NMOS devices. A person skilled in the art would recognize these variations within the scope of the exemplary embodiments of the invention.
  • An advantageous feature of the exemplary 3D NAND cell string 300 is to reduce the program-disturb of the unselected cells. For example, assuming the segment 309 b is selected for programming, after the bit line voltage is set, the selected word line will be supplied with a high program voltage such as +10V to +20V. The unselected word lines in the same segment will be supplied with an inhibit voltage such as +5V to +10V. The internal select gate 308 a is supplied with VDD and internal select gate 308 b is supplied with 0V. This prevents the high voltage in the channel of segment 309 b from being passed to segments 309 a and 309 c. Thus, the word lines of the segments 309 a and 309 c can be floating at a lower voltage to reduce or eliminate program-disturb to memory elements in those segments.
  • The drain select gate 306, source select gate 307, and the word lines of the unselected segments 309 a and 309 c may be supplied with a proper voltage to pass (VDD or 0V) from the bit line, and VDD from the source line to the selected segment 309 b. If the bit line voltage is 0V, it will discharge the channel of the segment 309 b to 0V, thus the selected cell will be programmed. If the bit line voltage is VDD, it will turn off the internal select gate 308 a to allow the channel of the segment 309 b to be self-boosted to about +5V to +10V by the word lines of the segment 309 b, and thus the selected cell is program-inhibited. The channel of the segment 309 c may be supplied with VDD or a proper voltage from the source line to reduce the leakage current of the internal select gate 308 b. It should be noted that in another embodiment, the unselected word lines of the segments 309 a and 309 c may be supplied with a medium high voltage to slightly boost the channel of the segments 309 a and 309 c for the case when the bit line is supplied with VDD. This may further reduce the leakage current of the internal select gates 308 a and 308 b.
  • Another advantage of the invention is that cells associated with multiple word lines and segments can be programmed simultaneously. For example, the program data may be supplied from the bit line to the segment 309 c, and then the internal select gate 308 b is turned off to isolate the segment 309 c, while programming occurs. Then, second program data is supplied from the bit line to the second segment 309 b, and then the internal select gate 308 a is turned off to isolate the segment 309 b, while programming occurs. Then, third program data is supplied from the bit line to the segment 309 a. In this way, different data may be programmed to the cells of selected word lines of multiple segments simultaneously, thus reducing the programming time.
  • Another advantage of the invention is the multiple word line groups may be used as MOS capacitors to temporarily store the program data and read data, thus achieving multiple word lines' simultaneous programming or reading. In another embodiment, the multiple word line groups may use a Dynamic Random-Access Memory (DRAM) to store data as the charge in the channel of each word line groups.
  • According to another exemplary embodiment of the invention, the internal select gates (e.g., 308 a and 308 b) may be formed by two or more transistors connected in series. The gates of the transistors may be connected to the same or different control signals. This arrangement may have higher punch-through voltage and lower leakage current than a single transistor.
  • In one exemplary embodiment, the multiple layers of the 3D NAND string's pattern may be defined or formed by a single lithography step. For example, the holes for all the layers including drain select gates, word lines, internal select gates, and source select gates, etc. may be etched in one step. In another exemplary embodiment, the pattern may be defined and etched using multiple steps, such as using a first step to form the segment 309 c, and a second step to form the segment 309 b, and a third step to form the segment 309 a.
  • FIGS. 4A-B show exemplary embodiments of a divided linear cell string structure 400 and an equivalent circuit 416 in accordance with the present invention. The 3D NAND cell string 400 is similar to the cell string 300 shown in FIG. 3A except that the gate dielectric layer of the internal select gates 308 a and 308 b is formed by the same charge trapping layer 314 as the cells. In an exemplary embodiment, this may reduce process steps during manufacture. However, during operations, the bias conditions should be carefully controlled to prevent unwanted programming of the internal select gates 308 a and 308 b. In another embodiment, the internal select gates 308 a and 308 b may be supplied with proper inhibit conditions during erase and program operations. In another embodiment, the voltage threshold (Vt) of the internal select gates 308 a and 308 b may be checked and erased or programmed back to the desired value.
  • FIGS. 5A-B show exemplary embodiments of a divided non-linear cell string structure 500 constructed using a folded ‘U’ shape string and an equivalent circuit 516 in accordance with the present invention. The 3D NAND cell string 500 comprises a metal bit line 501 and a polysilicon or silicon channel 502. Also shown are source 503 and drain 504 junctions that may have the opposite type of doping as the channel 502. A metal source line 505, drain select gate (DSG) 506, and source select gate (SSG) 507 are also shown. The string 500 is divided into multiple segments 509 a, 509 b, 509 c, 509 d, 509 e, and 509 f by “internal select gates” 508 a, 508 b, 508 c, and 508 d. The internal select gates 508 a, 508 b, 508 c, and 508 d are connected to control signals ISG0, ISG1, ISG2 and ISG1, respectively. The first segment 509 a contains multiple word lines, WL0 to WLk. The second segment 509 b contains word lines WLk+1 to WLi, and so forth. It should be noted that the segments may have the same or different number of word lines. The internal select gates 508 a, 508 b, 508 c, and 508 d may have longer channel lengths than the memory cells to sustain high voltage during program operations. The internal select gates 508 a to 508 d may be shared with the adjacent NAND strings, or decoded for each NAND string. The internal select gates may have an oxide layer as the gate dielectric, as shown 510. Charge-trapping layers 511 comprise, for example, ONO layers.
  • FIGS. 6A-B show exemplary embodiments of a divided non-linear cell string structure 600 constructed using a folded ‘U’ shape string and an equivalent circuit 614 in accordance with the present invention. As illustrated in FIG. 6A the cell string 600 is similar to the cell string 500 shown in FIG. 5A except that the gate dielectric layer of the internal select gates 508 a, 508 b, 508 c, and 508 d is formed by the same charge trapping layer 511 as the cells. In an exemplary embodiment, this may reduce process steps during manufacture. Thus, there are many other cell string structures that may be used to implement the multiple word line groups described herein. A person skilled in the art would recognize that these variations are within the scope of the exemplary embodiments.
  • FIGS. 7-9 show exemplary embodiments of 3D NAND array architectures comprising exemplary embodiments of divided cell string structures in accordance with the present invention.
  • FIG. 7 shows an exemplary embodiment of a 3D NAND array structure 700 constructed using the novel linear cell string structure 300 shown in FIG. 3A. The array structure 700 comprises metal bit lines 701 a, 701 b, 701 c, and 701 d, drain select gates (e.g., 702 a through 702 d), source select gate 703 and source line 706. Also shown are internal select gates 704 a and 704 b. The internal select gates 704 a and 704 b divide the word lines into multiple segments 705 a, 705 b, and 705 c. It should also be noted that each of the internal select gates 704 a and 704 b are shared by multiple cell strings. Thus, the novel linear cell string structure 300 allows the segments of the 3D NAND array 700 to be programmed while reducing or eliminating program-disturb for the unselected segments.
  • FIG. 8 shows an exemplary embodiment of a 3D NAND array structure 800 constructed using the novel non-linear (U-shaped) cell string structure 500 shown in FIG. 5A. The array structure 800 comprises metal bit lines 801 a, 801 b, 801 c, and 801 d, a metal source line 802, drain select gate 803, source select gate 804, and back gate 807. Also shown are internal select gates 805 a, 805 b, 805 c, and 805 d that divide the word lines into multiple segments indicated at 806 a, 806 b, and 806 c. Thus, the novel non-linear cell string structure 500 allows the segments of the 3D NAND array 800 to be programmed while reducing or eliminating program-disturb for the unselected segments.
  • FIG. 9 shows an exemplary embodiment of a 3D NAND array structure 900 constructed using horizontal cell strings comprising the novel linear cell string structure 300 shown in FIG. 3A. The array structure 900 comprises polysilicon bit lines 901 a, 901 b, 901 c, and 901 d, drain select gates (e.g., 902 a through 902 d), source select gate 903, source line 906, and internal select gates 904 a and 904 b. The internal select gates 904 a and 904 b divide the word lines (of the cell strings) into multiple segments indicated at 905 a, 905 b, and 905 c. Thus, the novel linear cell string structure 300 allows the segments of the 3D NAND array 900 to be programmed while reducing or eliminating program-disturb for the unselected segments.
  • FIG. 10 shows an exemplary embodiment of method 1000 for programming memory cells in a segment of a cell string with reduced program-disturb. For example, the method is suitable for use with the novel cell strings shown in FIGS. 3-6 and with the 3D NAND devices shown in FIGS. 7-9.
  • At block 1002, a segment of a cell string formed by internal select gates and containing a memory cell to be programmed is determined. For example, as illustrated in FIG. 3A, the segment 309 c containing memory cell 312 a is to be programmed.
  • At block 1004, drain select gate (DSG), source select gate (SSG) and internal select gate (ISG) voltages are set. For example, in an exemplary embodiment, the DSG 306 is set to VDD, SSG 307 is set to 0 volts and the ISG0 and ISG1 are set to VDD. In an embodiment, the controller 320 sets these voltages.
  • At block 1004, a bit line voltage is set. For example, in an exemplary embodiment, the bit line 301 is set to either VDD for inhibit or zero volts for program. In an embodiment, the controller 320 sets the bit line voltage.
  • At block 1008, word line voltages are ramped up. For example, the selected word line WLm+1 is set to approximately 20 volts and the unselected word lines WLm+2 to WLn are set to approximately 10 volts. This begins the programming of the memory cell 312 a.
  • At block 1010, the voltage on the ISG1 is set to zero. For example, the controller 320 set the voltage ISG1 to zero. This isolates the segment 309 c from the other segments. Thus, during the programming of memory element 312 a, memory elements in segments 309 a and 309 b are protected from the effects of program-disturb.
  • Thus, the method 1000 operates to program memory cells in a segment of a cell string with reduced program-disturb. It should be noted that the method 1000 is exemplary and that the disclosed operations may be combined, rearranged, added to, deleted, and/or modified within the scope of the embodiments.
  • FIG. 11 shows an exemplary embodiment of method 1100 for programming memory cells in multiple segments of a cell string with reduced program-disturb. For example, the method is suitable for use with the novel cell strings shown in FIGS. 3-6 and with the 3D NAND devices shown in FIGS. 7-9.
  • Blocks 1102 through 1110 are identical to the blocks 1002 through 1010 shown in FIG. 10 and so their description will not be repeated here. At the end of block 1110, the memory cell 312 a in segment 309 c is being programmed and the internal select gate 308 b is turned off. The method now continues at block 1112.
  • At block 1112, a segment of a cell string formed by internal select gates and containing a memory cell to be programmed is determined. For example, as illustrated in FIG. 3A, the segment 309 b containing memory cell 311 a is to be programmed. It should be noted that at this point the internal select gate ISG0 is turned on to allow the bit line voltage to pass to the segment 309 b. If, however, it is desirable to program a cell in segment 309 a, the internal select gate ISG0 can be turned off.
  • At block 1114, a bit line voltage is set. For example, in an exemplary embodiment, the bit line 301 is set to either VDD for inhibit or zero volts for program. In an embodiment, the controller 320 sets the bit line voltage.
  • At block 1116, word line voltages are ramped up. For example, the word line WLk+1 is set to approximately 20 volts and the word lines WLk+2 to WLm are set to approximately 10 volts. This begins the programming of the memory cell 311 a. Note that since the programming operation takes far longer than the biasing operation described, the biasing operation is quickly completed and thus both memory elements 312 a and 311 a continue to be programmed essentially simultaneously.
  • At block 1118, the voltage on the ISG0 is set to zero. For example, the controller 320 set the voltage ISG0 to zero. Thus, during the programming of memory element 311 a, memory elements in segments 309 a are protected from the effects of program-disturb.
  • Thus, the method 1100 operates to program multiple memory cells in multiple segments of a cell string with reduced program-disturb. It should be noted that the method 1100 is exemplary and that the disclosed operations may be combined, rearranged, added to, deleted, and/or modified within the scope of the embodiments.
  • FIG. 12 shows an exemplary timing diagram 1200 illustrating signal timing waveforms to program multiple memory elements in multiple segments in a cell string with reduced program-disturb. For example, signal timing shown in the diagram 1200 is suitable for use to program multiple cells in multiple segments of the cell string structure shown in FIGS. 3A-B. In an exemplary embodiment, the memory controller 320 sets the signal line voltages as described below.
  • At a first timing interval shown at 1202, the DSG, ISG0, ISG1 are set to VDD volts, and the SSG, and word lines (WL0-WLn) are set to zero volts. This initializes the cell string for programming.
  • At a second timing interval shown at 1204, data (Data1) is loaded for programming into the third segment 309 c. For example, the bit line data is set to the appropriate value (Data1) and the word lines for the third segment (WLm+1-WLn) are set to either the selected (20) or unselected (10) voltage level. This begins the programming of the selected cells in the third segment. The voltage on ISG1 is then set to zero voltage to isolate the third segment from the remaining segments.
  • At a third timing interval shown at 1206, data (Data2) is loaded for programming into the second segment 309 b. For example, the bit line data is set to the appropriate value (Data2) and the word lines for the second segment (WLk+1-WLm) are set to either the selected (20) or unselected (10) voltage level. This begins the programming of the selected cells in the second segment. The voltage on ISG0 is then set to zero voltage to isolate the second segment from the remaining segments.
  • At a fourth timing interval shown at 1208, data (Data3) is loaded for programming into the first segment 309 a. For example, the bit line data is set to the appropriate value (Data3) and the word lines for the first segment (WL0-WLk) are set to either the selected (20) or unselected (10) voltage level. This begins the programming of the selected cells in the first segment. The voltage on DSG is then set to zero.
  • At a fifth timing interval shown at 1210, simultaneous programming of the cells in the three segments continues for approximately 30 microseconds (us).
  • Thus, the exemplary timing diagram 1200 illustrating signal timing waveforms to program multiple bits in multiple segments of a novel cell string structure in accordance with the present invention. It should be noted that the signal timing and voltage levels disclosed are exemplary and not limiting of the embodiments of the invention. It should also be noted that multiple segments can be programmed without programming all segments. For example, modifications to the above signal timing can be made to program segment 3 and segment 1 or to program segment 2 and segment 1.
  • It should be noted that the voltage values shown in the description and figures are exemplary and do not limit the described voltages to exact voltage values. It is obvious that the actual voltages used depend on the technology, process, and/or other factors. It should also be noted that the disclosed cells and bias conditions can be utilized with any type of array structures and that the bias conditions are not limited to specific array types.
  • While exemplary embodiments of the present invention have been shown and described, it will be obvious to those with ordinary skills in the art that based upon the teachings herein, changes and modifications may be made without departing from the exemplary embodiments and their broader aspects. Therefore, the appended claims are intended to encompass within their scope all such changes and modifications as are within the true spirit and scope of the exemplary embodiments of the present invention.

Claims (20)

What is claimed is:
1. An apparatus, comprising:
a plurality of charge storing devices connected to form a cell string; and
one or more internal select gates connected between selected charge storing devices in the cell string, wherein the one or more internal select gates divide the cell string into two or more segments of charge storing devices, and wherein selectively enabling and disabling the one or more internal select gates during programming isolates one or more selected segments to reduce program-disturb to remaining segments.
2. The apparatus of claim 1, wherein the cell string comprises a channel and at least one internal select gate blocks current flow through the channel when the at least one internal select gate is disabled.
3. The apparatus of claim 1, wherein the one or more internal select gates are charge storing devices.
4. The apparatus of claim 1, wherein the one or more internal select gates are non-charge storing devices.
5. The apparatus of claim 1, wherein the plurality of charge storing devices and the one or more internal select gates form a linear cell string.
6. The apparatus of claim 1, wherein the plurality of charge storing devices and the one or more internal select gates form a non-linear cell string.
7. A 3D memory array, comprising:
a plurality of cell strings, wherein each cell string has a plurality of charge storing devices; and
one or more internal select gates connected between selected charge storing devices in the cell strings, wherein the one or more internal select gates divide each cell string into two or more segments of charge storing devices, and wherein selectively enabling and disabling the one or more internal select gates during programming isolates one or more selected segments to reduce program-disturb to remaining segments.
8. The array of claim 7, wherein at least two cell strings have a common internal select gate.
9. The array of claim 7, wherein the one or more internal select gates are charge storing devices.
10. The array of claim 7, wherein the one or more internal select gates are non-charge storing devices.
11. The apparatus of claim 7, wherein the cell strings are linear cell strings.
12. The apparatus of claim 7, wherein the cell strings are non-linear cell strings.
13. A method for programming memory cells of a cell string having internal select gates that divides the cell string into segments, comprising:
identifying a segment of the cell string containing a memory cell to be programmed;
applying a first voltage to a source selected gate of the cell string;
applying a second voltage to a drain select gate and the internal select gates of the cell string;
applying a third voltage to a bit line of the cell string;
ramping up a fourth voltage to a selected word line of the segment; and
ramping up a fifth voltage to unselected word lines of the segment.
14. The method of claim 13, wherein the first voltage is zero volts.
15. The method of claim 13, wherein the second voltage is VDD.
16. The method of claim 13, wherein the fourth voltage is 20 volts.
17. The method of claim 13, wherein the fifth voltage is in the range of 8 to 10 volts.
18. The method of claim 13, disabling a first internal select gate after ramping up voltages to the selected and unselected word lines to prevent program-disturb to other segments.
19. The method of claim 18, further comprising
identifying a second segment of the cell string containing a second memory cell to be programmed;
applying a sixth voltage to the bit line of the cell string;
ramping up an eighth voltage to a selected word line of the second segment; and
ramping up a ninth voltage to unselected word lines of the second segment.
20. The method of claim 19, disabling a second internal select gate after ramping up voltages to the selected and unselected word lines of the second segment to prevent program-disturb to other segments, and wherein the memory cell and the second memory cell are programmed substantially simultaneously.
US15/348,869 2015-11-11 2016-11-10 3d nand array with divided string architecture Abandoned US20170133099A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US201562253683P true 2015-11-11 2015-11-11
US15/348,869 US20170133099A1 (en) 2015-11-11 2016-11-10 3d nand array with divided string architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/348,869 US20170133099A1 (en) 2015-11-11 2016-11-10 3d nand array with divided string architecture
US16/138,897 US10553293B2 (en) 2015-11-11 2018-09-21 3D NAND array with divided string architecture

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/138,897 Division US10553293B2 (en) 2015-11-11 2018-09-21 3D NAND array with divided string architecture

Publications (1)

Publication Number Publication Date
US20170133099A1 true US20170133099A1 (en) 2017-05-11

Family

ID=58667835

Family Applications (2)

Application Number Title Priority Date Filing Date
US15/348,869 Abandoned US20170133099A1 (en) 2015-11-11 2016-11-10 3d nand array with divided string architecture
US16/138,897 Active US10553293B2 (en) 2015-11-11 2018-09-21 3D NAND array with divided string architecture

Family Applications After (1)

Application Number Title Priority Date Filing Date
US16/138,897 Active US10553293B2 (en) 2015-11-11 2018-09-21 3D NAND array with divided string architecture

Country Status (2)

Country Link
US (2) US20170133099A1 (en)
WO (1) WO2017083584A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190189177A1 (en) * 2017-12-18 2019-06-20 Micron Technology, Inc. Single plate configuration and memory array operation
US11017831B2 (en) 2019-07-15 2021-05-25 Micron Technology, Inc. Ferroelectric memory cell access

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6285587B1 (en) * 1999-06-24 2001-09-04 Samsung Electronics Co., Ltd. Memory cell string structure of a flash memory device
US6295227B1 (en) * 1998-11-26 2001-09-25 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US6850439B1 (en) * 2003-10-10 2005-02-01 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device with NAND string memory transistor controlled as block separation transistor
US20050056869A1 (en) * 2003-08-04 2005-03-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory cell matrix, a mehtod for operating the same, monolithic integrated circuits and systems
US20090097309A1 (en) * 2007-10-03 2009-04-16 Kabushiki Kaisha Toshiba Nonvolatile semiconductor storage device, and method for controlling nonvolatile semiconductor storage device
US8908431B2 (en) * 2010-02-17 2014-12-09 Samsung Electronics Co., Ltd. Control method of nonvolatile memory device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7233522B2 (en) * 2002-12-31 2007-06-19 Sandisk 3D Llc NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
US7612411B2 (en) * 2005-08-03 2009-11-03 Walker Andrew J Dual-gate device and method
US7433241B2 (en) * 2006-12-29 2008-10-07 Sandisk Corporation Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data
KR101487524B1 (en) * 2008-08-27 2015-01-29 삼성전자주식회사 Program method of nonvolatile memory device
US9589644B2 (en) * 2012-10-08 2017-03-07 Micron Technology, Inc. Reducing programming disturbance in memory devices
US9214235B2 (en) * 2013-04-16 2015-12-15 Conversant Intellectual Property Management Inc. U-shaped common-body type cell string
JP2015060602A (en) * 2013-09-17 2015-03-30 株式会社東芝 Nonvolatile semiconductor storage device
TW201621670A (en) * 2014-09-06 2016-06-16 Neo半導體股份有限公司 Method and apparatus for writing nonvolatile memory using multiple-page programming

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6295227B1 (en) * 1998-11-26 2001-09-25 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US6285587B1 (en) * 1999-06-24 2001-09-04 Samsung Electronics Co., Ltd. Memory cell string structure of a flash memory device
US20050056869A1 (en) * 2003-08-04 2005-03-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory cell matrix, a mehtod for operating the same, monolithic integrated circuits and systems
US6850439B1 (en) * 2003-10-10 2005-02-01 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device with NAND string memory transistor controlled as block separation transistor
US20090097309A1 (en) * 2007-10-03 2009-04-16 Kabushiki Kaisha Toshiba Nonvolatile semiconductor storage device, and method for controlling nonvolatile semiconductor storage device
US8908431B2 (en) * 2010-02-17 2014-12-09 Samsung Electronics Co., Ltd. Control method of nonvolatile memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190189177A1 (en) * 2017-12-18 2019-06-20 Micron Technology, Inc. Single plate configuration and memory array operation
US10762944B2 (en) * 2017-12-18 2020-09-01 Micron Technology, Inc. Single plate configuration and memory array operation
US11017831B2 (en) 2019-07-15 2021-05-25 Micron Technology, Inc. Ferroelectric memory cell access

Also Published As

Publication number Publication date
US10553293B2 (en) 2020-02-04
US20190027227A1 (en) 2019-01-24
WO2017083584A1 (en) 2017-05-18

Similar Documents

Publication Publication Date Title
US6160739A (en) Non-volatile memories with improved endurance and extended lifetime
US10672487B2 (en) Semiconductor memory device
US10643714B2 (en) Shielded vertically stacked data line architecture for memory
KR100366741B1 (en) Nonvolatile semiconductor memory
US8565018B2 (en) Reducing effects of erase disturb in a memory device
US10090056B2 (en) Semiconductor memory device
US7751243B2 (en) Semiconductor memory device provided with MOS transistor having charge accumulation layer and control gate and data write method of NAND flash memory
KR20090102262A (en) Operating method of memory device reducing lateral movement of charges
US10553293B2 (en) 3D NAND array with divided string architecture
US20140226415A1 (en) Non-Volatile Memory Including Bit Line Switch Transistors Formed In A Triple-Well
US7768833B2 (en) Method of programming non-volatile memory device
US8493796B2 (en) Nonvolatile semiconductor memory device
US9972392B2 (en) SONOS byte-erasable EEPROM
US7613042B2 (en) Decoding system capable of reducing sector select area overhead for flash memory
US9136004B2 (en) Semiconductor memory device and programming method for flash memory for improving reliabilty of insulating layer of memory cell
Micheloni et al. 3d stacked nand flash memories
KR20210070219A (en) Apparatus and methods for seeding operations concurrently with data line set operations
US10381085B2 (en) Erasing memory cells
KR20090056267A (en) Method for programming-verifying of non volatile memory device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION