JP5430890B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP5430890B2 JP5430890B2 JP2008191829A JP2008191829A JP5430890B2 JP 5430890 B2 JP5430890 B2 JP 5430890B2 JP 2008191829 A JP2008191829 A JP 2008191829A JP 2008191829 A JP2008191829 A JP 2008191829A JP 5430890 B2 JP5430890 B2 JP 5430890B2
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- 239000004065 semiconductor Substances 0.000 title claims description 40
- 239000000758 substrate Substances 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 185
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 72
- 229910052710 silicon Inorganic materials 0.000 description 72
- 239000010703 silicon Substances 0.000 description 72
- 238000000034 method Methods 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000013500 data storage Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Description
図2は、同半導体記憶装置における、1本(1列)のメモリストリングの模式断面図である。
図3は、同1本のメモリストリングの模式斜視図である。
なお、図1及び図3においては、図を見易くするために、導電部分のみを示し、絶縁部分は図示を省略している。
Claims (4)
- 半導体基板と、
前記半導体基板上に設けられ、複数の絶縁層と複数の導電層とが交互に積層された積層体と、
前記積層体を貫通して形成された貫通ホールの内部に設けられ、前記絶縁層と前記導電層との積層方向に延びる半導体層と、
前記導電層と前記半導体層との間に設けられた電荷蓄積層と、
前記積層方向において直列接続され、前記導電層と、前記積層体と前記半導体層との間に設けられた前記電荷蓄積層と、をそれぞれ有する複数のメモリセルと、
を備え、
前記貫通ホールは上部から下部にかけて細くなる領域を有し、前記領域において、前記導電層は最上層から最下層にかけて薄くなっていることを特徴とする半導体記憶装置。 - 上層側の前記メモリセルと下層側の前記メモリセルは、スイッチング特性が等しいことを特徴とする請求項1記載の半導体記憶装置。
- 前記電荷蓄積層は絶縁膜であることを特徴とする請求項1または2に記載の半導体記憶装置。
- 前記貫通ホールは前記領域において上部から下部にかけて段階的に細くなっていることを特徴とする請求項1〜3のいずれか1つに記載の半導体記憶装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008191829A JP5430890B2 (ja) | 2008-07-25 | 2008-07-25 | 半導体記憶装置 |
US12/405,544 US8030700B2 (en) | 2008-07-25 | 2009-03-17 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008191829A JP5430890B2 (ja) | 2008-07-25 | 2008-07-25 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010034112A JP2010034112A (ja) | 2010-02-12 |
JP5430890B2 true JP5430890B2 (ja) | 2014-03-05 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2008191829A Expired - Fee Related JP5430890B2 (ja) | 2008-07-25 | 2008-07-25 | 半導体記憶装置 |
Country Status (2)
Country | Link |
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US (1) | US8030700B2 (ja) |
JP (1) | JP5430890B2 (ja) |
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JP2008078404A (ja) | 2006-09-21 | 2008-04-03 | Toshiba Corp | 半導体メモリ及びその製造方法 |
JP2008140912A (ja) | 2006-11-30 | 2008-06-19 | Toshiba Corp | 不揮発性半導体記憶装置 |
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