CN105023926A - 一种存储器元件及其制作方法 - Google Patents
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Abstract
本发明公开了一种存储器元件及其制作方法，该存储器元件包括一串接存储单元阵列，包括：由绝缘材质所分离的多个导电条纹的多个叠层，包括至少由多个导电条纹所构成的一底部阶层、由多个导电条纹所构成的多个中间阶层、以及由多个导电条纹所构成的一顶部阶层；多个垂直有源条纹，位于这些叠层之间；多个电荷储存结构，位于这些叠层中的这些中间阶层的这些导电条纹的多个侧壁表面，与这些垂直有源条纹之间的多个交错处的接口区中；以及一栅介电层，具有与这些电荷储存结构相异的材质，且位于该顶部阶层的这些导电条纹和该底部阶层的这些导电条纹二者至少一者的多个侧壁表面，与这些垂直有源条纹之间的多个交错处的接口区中。
Description
技术领域
本发明是有关于一种高密度存储元件，且特别是有关于一种将存储单元的多阶层排列成三维空间的立体阵列的存储元件及其制作方法。
背景技术
三维立体存储元件，已经发展出多种不同的结构形态。其中包含由被绝缘材料所隔离的导电条纹(conductive strips)所构成的叠层(Stacks ofconductive strips)，以及位于这些叠层之间的垂直有源条纹(vertical activestrips)。包含电荷储存结构的存储单元，则位于叠层中导电条纹的中间阶层(intermediate planes of conductive strips in the stacks)和垂直有源条纹之间的接口区(interface regions)之中。串行选择开关，位于叠层中导电条纹的顶部阶层(top plane of conductive strips in the stacks)与垂直有源条纹之间的接口区之中。参考选择开关(reference select switch)，位于叠层中导电条纹的底部阶层(bottom plane of conductive strips)与垂直有源条纹之间的接口区之中。为了可靠地控制存储单元的操作，串行选择开关和参考选择开关的阈值电压，必须保持稳定。当串行选择开关和参考选择开关，纳入电荷储存结构，用来作为存储单元时，串行选择开关和参考选择开关会被充电，因而造成这些开关阈值电压改变，需要额外的电流来对这些开关进行写入与擦除。
因此，有需提供三维立体集成电路存储器一种结构，可提供串行选择开关和参考选择开关稳定的阈值电压，使其在存储单元写入及擦除时，不需要额外电流来控制其阈值电压。
发明内容
本发明是有关于一种包含串接存储单元阵列的存储元件。此一元件包括由绝缘材质所分离的多个导电条纹的多个叠层，至少由多个导电条纹所构成的一底部阶层(GSL)、由多个导电条纹所构成的多个中间阶层(WLs)、以及由多个导电条纹所构成的一顶部阶层(SSLs)；多个垂直有源条纹，位于这些叠层之间；多个电荷储存结构，位于这些叠层中的这些中间阶层的这些导电条纹的多个侧壁表面(side surfaces of the conductive strips in theplurality of intermediate planes in the stacks)，与这些垂直有源条纹之间的多个交错处的接口区(interface regions at cross-points)中；以及一栅介电层，具有与这些电荷储存结构相异的材质，且位于该顶部阶层的这些导电条纹和该底部阶层的这些导电条纹二者至少一者的多个侧壁表面，与这些垂直有源条纹中的垂直有源条纹(the vertical active strips in the plurality ofvertical active strips以下简称为「垂直有源条纹」)之间的多个交错处的接口区中。
此一元件包括形成在导电条纹的顶部阶层(SSL)上方的金属硅化物层。此一元件包括，用来隔离导电条纹的顶部阶层和垂直有源条纹的间隙壁，以及形成在垂直有源条纹顶部的金属硅化物层。栅介电层，包含一层厚度比电荷储存结构还要薄的氧化硅材质层。其中，栅介电层的厚度约为7奈米(nanometer，nm)。
一参考导体层，位于导电条纹的底部阶层和集成电路基材之间，并且与多个垂直有源条纹连接。此参考导体层，包含N+掺杂的半导体材质。
本发明的实施例，也提供制作前述存储器元件的方法。
为了对本发明的上述及其他方面有更佳的了解，下文特举较佳实施例，并配合所附图式，作详细说明如下：
附图说明
图1是根据本发明的一实施例所绘示的一种三维立体存储器元件的剖面结构示意图。
图1A是根据本发明的另一实施例所绘示的一种三维立体存储元件的剖面结构示意图。
图1B是根据本发明的又一实施例所绘示的一种三维立体存储元件的剖面结构示意图。
图2是根据本发明的一实施例所绘示的一种集成电路的简化方块图。
图3是根据本发明的一实施例所绘示的制作存储器元件的方法流程图。
图4至图15是根据本发明的一实施例所绘示，制作存储器元件的一系列工艺结构剖面示意图。
图16至图27是根据本发明的另一实施例所绘示，制作存储器元件的一系列工艺结构剖面示意图。
【符号说明】
100：存储器元件 105：绝缘材质
111：导电条纹 111g：栅介电层
111m：电荷储存结构 112：导电条纹
112m：电荷储存结构 112g：栅介电层
113：导电条纹 113g：栅介电层
113m：电荷储存结构 114：导电条纹
114g：栅介电层 114m：电荷储存结构
115：绝缘材质 121：导电条纹
122：导电条纹 123：导电条纹
124：导电条纹 125：绝缘材质
131：导电条纹 132：导电条纹
133：导电条纹 134：导电条纹
135：绝缘材质 141：导电条纹
141m：电荷储存结构 142：导电条纹
142m：电荷储存结构 143：导电条纹
143m：电荷储存结构 144：导电条纹
144m：电荷储存结构 145：绝缘材质
151：导电条纹 151m：电荷储存结构
152：导电条纹 152m：电荷储存结构
153：导电条纹 153m：电荷储存结构
154：导电条纹 154m：电荷储存结构
155：栅介电层 156：栅介电层
157：栅介电层 158：栅介电层
161：垂直有源条纹 162：垂直有源条纹
170：绝缘材料 181：间隙壁
183：间隙壁 185：间隙壁
187：间隙壁 191：金属硅化物层
192：金属硅化物层 193：金属硅化物层
195：金属硅化物层 196：金属硅化物层
197：金属硅化物层 200：集成电路
258：阶层译码器 259：串行选择线
260：垂直通道存储器阵列 261：行译码器
262：字线 263：列译码器
266：感测放大器和数据输入结构
267：数据总线 268：方块
269：偏压配置状态机 271：数据输入线
272：数据输出线 274：其他电路
275：集成电路
310、320、330、340、350、360、370、380：步骤
405：绝缘层 410：导电层
410a：牺牲层 411：导电条纹
411a：导电条纹 411m：存储层
412：导电条纹 412a：导电条纹
412m：存储层 413：导电条纹
413a：导电条纹 413m：存储层
414：导电条纹 414a：导电条纹
414m：存储层 415：绝缘层
420：牺牲层 421：导电条纹
422：导电条纹 423：导电条纹
424：导电条纹 425：绝缘层
430：牺牲层 431：导电条纹
432：导电条纹 433：导电条纹
434：导电条纹 435：绝缘层
440：牺牲层 441：导电条纹
441m：存储层 442：导电条纹
442m：存储层 443：导电条纹
443m：存储层 444：导电条纹
444m：存储层 445：绝缘层
450：导电层 451：导电条纹
452：导电条纹 453：导电条纹
454：导电条纹 455：绝缘层
460：硬掩模层 510：开口
520：开口 615：栅介电层
616：栅介电层 617：栅介电层
618：栅介电层 655：栅介电层
656：栅介电层 657：栅介电层
658：栅介电层 661：氧化硅材质层
663：氧化硅材质层 665：氧化硅材质层
761：垂直有源条纹 762：垂直有源条纹
810：开口 905：水平开口
906：水平开口 1001：导电材质
1270：绝缘材料 1481：间隙壁
1483：间隙壁 1485：间隙壁
1487：间隙壁 1591：金属硅化物层
1592：金属硅化物层 1593：金属硅化物层
1595：金属硅化物层 1596：金属硅化物层
1597：金属硅化物层
具体实施方式
以下将配合图示，对本发明的实施例提供更详细的说明。虽然以下说明将会参照特定的结构与方法。但必须注意的是，这些特定的实施案例与方法，并非用以限定本发明。本发明仍可采用其他特征、元件方法及实施例，来加以实施。较佳实施例的提出，仅是用以例示本发明的技术特征，并非用以限定本发明的权利要求范围。该技术领域中具有通常知识者，将可根据以下说明书的描述，在不脱离本发明的精神范围内，作均等的修饰与变化。在不同实施例之中，相同的元件，将以相同的元件符号加以表示。
图1是根据本发明的一实施例所绘示的一种三维立体存储器元件100在X-Z平面上的剖面结构示意图。如图1所绘示的例子中，存储器元件100包括形成在一集成电路基材上的串接存储单元的与非门(NANDstrings)阵列。存储器元件100包括多个由被绝缘材质(例如，绝缘材质105、115、125、125、135和145)所隔离的多个导电条纹所构成的叠层。其中，这些叠层至少包括导电条纹(例如，导电条纹111、112、113和114)的底部阶层(GSL)、多个导电条纹(例如，导电条纹121、122、123、124、131、132、133、134、141、142、143和144)的中间阶层(WLs)以及一个导电条纹(例如，导电条纹151、152、153和154)的顶部阶层(SSLs)。多个垂直有源条纹(例如，垂直有源条纹161和162)设置在叠层之间。电荷储存结构(例如，电荷储存结构141m、142m、143m和144m)，位于叠层中构成中间阶层的导电条纹的侧壁表面与垂直有源条纹之间的交错处的接口区中。绝缘材料(例如，绝缘材料170)，用来将由多个导电条纹(例如导电条纹112、122、132、142和152)所构成的叠层，与另一个相邻且由多个导电条纹(例如导电条纹113、123、133、143和153)所构成的叠层加以隔离。
栅介电层(例如，栅介电层111g、112g、113g、114g、155、156、157和158)位于顶部阶层的导电条纹及底部阶层的导电条纹二者至少一者的侧壁表面，与垂直有源条纹之间的交错处的接口区中，藉此形成串行选择线(string select lines，SSL)以及接地选择线(ground select lines，GSL)。其中，构成栅介电层(例如，栅介电层111g、112g、113g、114g、155、156、157和158)的材质，与构成电荷储存结构的材质不同。由于，由栅介电层所构成的串行选择线(SSL)和接地选择线(GSL)并不能充电，因此具有固定的阈值电压。
栅介电层可以包含一个比电荷储存结构还薄的氧化硅材质层。例如，栅介电层的厚度可约为7nm，而电荷储存结构的厚度可约为20nm。由栅介电层所构成的串行选择线(SSL)和参考选择开关，可以在较低操作电压(例如，3.3V)下进行操作。即可在小于由电荷储存结构所构成的存储单元所需的操作电压(例如，介于约5V至约20V之间)下进行操作。
存储器元件100可以包括，形成于导电条纹的顶部阶层上方的金属硅化物层(例如，金属硅化物层191、193、195和197)，用来降低构成顶部阶层的导电条纹的电阻。存储器元件100可以包括，用来隔离垂直有源条纹与导电条纹的顶部阶层的间隙壁(例如间隙壁181、183、185和187)，以及形成于垂直有源条纹顶端的金属硅化物层(例如，金属硅化物层192和196)。
在存储器元件之中，构成这些叠层的导电条纹，是沿着垂直X-Z平面的Y方向设置，且与译码电路连接。参考导体层(未绘示)设在导电条纹的底部阶层和集成电路基材之间的层次中，并且与这些垂直有源条纹连接。此参考导体层可包含N+掺杂的半导体材质。存储器元件100可以包括连接至这些垂直有源条纹的上方图案化导电层(未绘示)，其包括多个耦接感应电路的全局位线(global bit lines)。
图1A是根据本发明的另一实施例所绘示的一种三维立体存储元件的剖面结构示意图。与图1的存储器元件的差别在于，栅介电层(例如，栅介电层155、156、157和158)，只设于垂直有源条纹与叠层中构成顶部阶层的导电条纹的侧壁表面之间的交错处的接口区中。电荷储存结构(例如，电荷储存结构111m、112m、113m、和114m)，设于垂直有源条纹与叠层中构成底部阶层的导电条纹的侧壁表面之间的交错处的接口区中。
图1B是根据本发明的第二另一实施例所绘示的一种三维立体存储元件的剖面结构示意图。第二另一实施例中的一个差别在于，栅介电层(例如，栅介电层111g、112g、113g和114g)，只设于垂直有源条纹与叠层中构成底部阶层的导电条纹的侧壁表面之间的交错处的接口区中。电荷储存结构(例如，电荷储存结构151m、152m、153m和154m)，设于垂直有源条纹与叠层中构成顶部阶层的导电条纹的侧壁表面之间的交错处的接口区中。另外一个差异点是，金属硅化物层(例如，金属硅化物层192和196)只形成于垂直有源条纹(例如，垂直有源条纹161和162)的顶端上，而不形成于电荷储存结构(例如，电荷储存结构151m、152m、153m和154m)之上。与图1和图1A所绘示的结构有所不同，在图1和图1A中，金属硅化物层(例如，金属硅化物层191、193、195和197)，还同时形成于导电条纹(例如，导电条纹151、152、153和154)的顶部阶层(SSLs)上方，其包括多晶硅。
图2是根据本发明的一实施例所绘示的一种集成电路的简化方块图。图2所示的例子中，集成电路200包括位于集成电路基板上的垂直通道存储器阵列260。其中，垂直通道存储器阵列260，是通过位于导电条纹的顶部阶层(SSLs)以及导电条纹的底部阶层(GSL)的至少一者上的栅介电层来加以实现。其中，构成栅介电层的材料与构成电荷储存结构的材质不同。而此一电荷储存结构形成于多个导电条纹的中间阶层(WLs)上。
行译码器(row decoder)261与多条字线262耦接，并且沿着存储器阵列260中的行线进行配置。列译码器(column decoder)263与沿着存储器阵列260中的列线配置的多条位线264(或如前所述的串行选择线(SSL))耦接，用以从存储器阵列260中的存储单元读取并写入数据。阶层译码器258与多个位于串行选择(SSL)线259(或如前所述的位线)上的存储器阵列260耦接。地址由总线265提供给列译码器263、行译码器261和阶层译码器258。在本实施例之中，感测放大器和数据输入结构(sense amplifiers and data-instructures)266是经由数据总线267和列译码器263耦接。由集成电路275上的输入/输出端，或由集成电路275内部或外部的其他数据源输入的数据，是透过数据输入(data-in)线271，提供至方块266中的数据输入结构。在本实施例之中，集成电路中还包括其他电路274，例如一般用途处理器(general purpose processor)或是特定用途应用电路(special purposeapplication circuit)，抑或是提供系统芯片(system-on-a-chip)功能且受到可编程电阻单元阵列(programmable resistance cell array)所支持的整合模块。来自于方块266中感测放大器的数据，则是透过数据输出(data-out)线272，提供至集成电路275上的输入/输出端，或至集成电路275内部或外部的其他数据目的地址。
本实施例所采用的控制器，是使用偏压配置状态机(bia arrangementstate machine)269，来控制透过方块268中的电压供应器所产生或提供的偏压配置供给电压，例如读取或写入电压的应用。可以采用已知的特定用途逻辑电路，来作为控制器。在另一实施例之中，控制器可以包括，可在同一集成电路中实施控制，且可执行计算机程序以控制元件操作的一般用途处理器。在又一实施例之中，可以整合特定用途逻辑电路和一般用途的处理器来完成此一控制器。
图3是根据本发明的一实施例所绘示的制作垂直通道结构的方法流程图。此一方法由步骤310开始：在集成电路基材上形成多个牺牲层，以及顶部导电层和底部导电层其中至少一个，其中这些牺牲层和导电层被多个绝缘层所隔离。接着，刻蚀这些牺牲层和导电层，以形成第一开口(请参照步骤320)。在第一开口中的顶部导电层和底部导电层其中至少一个的侧壁表面上形成一栅介电层(请参照步骤330)。于第一开口之中，形成多个垂直有源条纹，使垂直有源条纹与栅介电层接触(请参照步骤340)。
之后，刻蚀这些牺牲层和导电层，以在相邻的垂直有源条纹之间形成第二开口，藉此将牺牲层暴露于外，且藉此形成顶部导电层和底部导电层至少其中之一中的导电条纹的顶部阶层和导电条纹的底部阶层至少其中之一(请参照步骤350)。移除由第二开口暴露于外的牺牲层，藉以在绝缘层之间形成多个水平开口(请参照步骤360)。于水平开口中垂直有源条纹的侧壁表面上形成存储层(请参照步骤370)。于水平开口中形成多个由导电条纹所构成的阶层。阶层中的导电条纹的侧壁表面与存储层接触(请参照步骤380)。这些阶层包括多个导电条纹的中间阶层(WLs)。这些阶层可以包括的导电条纹的顶部阶层(SSL)与导电条纹的底部阶层(GSL)其中之一个，如图1B所绘示，导电条纹的顶部阶层(SSL)与存储层接触，如图1A所绘示，导电条纹的底部阶层(GSL)与存储层接触。之后，于第二开口中形成绝缘材料。
构成栅介电层的材料与构成存储层者不同。栅介电层可以包含氧化硅。存储层包括多层介电材质的电荷储存结构。以闪存技术来说，多层介电材质的电荷储存结构包括，闪存技术所已知的氧化物-氮化物-氧化物(Oxide-Nitride-Oxide，ONO)结构、氧化物-氮化物-氧化物-氮化物-氧化物(Oxide-Nitride-Oxide-Nitride-Oxide，ONONO)结构、硅-氧化物-氮化物-氧化物-硅(Silicon-Oxide-Nitride-Oxide-Silicon，SONOS)结构、能隙带工程-硅-氧化物-氮化物-氧化物-硅(Bandgap Engineered SONOS，BE-SONOS)结构、氮化坦-氧化铝-氮化硅-氧化硅-硅(Tantalum nitride，Aluminum oxide，Silicon nitride，Silicon oxide，Silicon，TANOS)结构以及金属高介电常数能隙带工程-硅-氧化物-氮化物-氧化物-硅(Metal-high-k Bandgap-EngineeredSONOS，MA BE-SONOS)结构。
栅介电层可以包含厚度小于存储层的氧化硅层。例如，栅介电层的厚度可约为7nm，而电荷储存结构的厚度可约为20nm。
间隙壁可形成在垂直有源条纹侧壁上，用来隔离垂直有源条纹和导电条纹的顶部阶层。金属硅化物层可形成在垂直有源条纹的顶部上。金属硅化物层可形成在导电条纹的顶部阶层上，例如，在同一工艺步骤中，金属硅化物层也可形成在垂直有源条纹的顶部上。
在一实施例中，构成顶部阶层的导电条纹和构成底部阶层的导电条纹，二者都具有和栅介电层接触的侧壁表面。在另一实施例之中，构成顶部阶层的导电条纹具有和栅介电层接触的侧壁表面；同时构成底部阶层的导电条纹则是具有和存储层接触的侧壁表面。而在又一实施例之中，构成顶部阶层的导电条纹具有和存储层接触的侧壁表面；同时构成底部阶层的导电条纹则具有和栅介电层接触的侧壁表面。
此一方法还可包括，在这些牺牲层和导电层以及集成电路基材之间的层次中形成一参考导体层。其中，参考导体层与这些垂直有源条纹连接，且参考导体层可包括N+掺杂的半导体材料。
图4至图15是根据本发明的一实施例所绘示，制作存储器元件的一系列工艺结构剖面示意图。图4是沿着X-Z平面所绘示的存储器元件半成品的结构剖面示意图。在图4中，存储器元件包括位于集成电路基材上方的，多个用来形成字线(WLs)的牺牲层(例如，牺牲层420、430和440)、用来形成串行选择线(SSL)的顶部导电层(例如，导电层450)以及用来形成接地选择线(GSL)的底部导电层(例如，导电层410)。其中，这些牺牲层和导电层彼此被绝缘层(例如，绝缘层405、415、425、435、445和445)所隔离。这些牺牲层可包含氮化硅。底部导电层(例如，导电层410)和顶部导电层(例如，导电层450)可包含N+掺杂的多晶硅。
用来图案化这些牺牲层和导电层的硬掩模层(例如，硬掩模层460)，位于这些牺牲层和导电层的上方。硬掩模层可包含多晶硅，其与用于牺牲层中的氮化硅，以及用于绝缘层的氧化材质之间，具有有高度的选择性。
图5是绘示使用硬掩模层来刻蚀牺牲层及导电层以形成多个第一开口(例如开口510和520)之后的工艺结构剖面示意图。在一实施例中，可以使用反应离子刻蚀(Reactive Ion Etch，RIE)，来对牺牲层及导电层进行刻蚀。其中，第一开口穿透多个牺牲层(例如，牺牲层420、430和440)、底部导电层(例如，导电层410)和顶部导电层(例如，导电层450)。而这些多个第一开口是用来形成多个垂直有源条纹。
图6是绘示在第一开口(例如，开口510和520)中的顶部导电层的侧壁表面以及底部导电层的侧壁表面上，形成栅介电层(例如，在顶部导电层的侧壁表面上形成栅介电层655、656、657和658；以及在底部导电层的侧壁表面上形成栅介电层615、616、617和618)之后的工艺结构剖面示意图。其中，栅介电层包括一层氧化硅材质层。栅介电层的厚度约7nm。而此氧化硅材质层可以通过热氧化的方式形成于底部导电层(例如，导电层410)和顶部导电层(例如，导电层450)上，且热氧化的温度范围介于800℃至900℃之间。而此热氧化工艺，同时也会在硬掩模层(例如，硬掩模层460)上形成氧化硅材质层(例如，氧化硅材质层661、663和665)。氧化硅材质层不会形成在牺牲层(例如，牺牲层420、430和440)上。
图7是绘示在第一开口之中形成多个垂直有源条纹(例如，垂直有源条纹761和762)之后的工艺结构剖面示意图。其中，这些多个垂直有源条纹，与形成在顶部导电层的侧壁表面上的栅介电层(例如，栅介电层655、656、657和658)以及形成在底部导电层的侧壁表面上的栅介电层(例如，栅介电层615、616、617和618)接触。且这些多个垂直有源条纹可以延伸至位于牺牲与导电层下方的参考导体层(未绘示)。硬掩模层(例如，硬掩模层460)则例如使用化学机械平坦化(Chemical-Mechanical-Planarization，CMP)工艺平坦化。其中，此平坦化工艺是停止于硬掩模层下方的绝缘层(例如绝缘层455)。
图8是绘示在刻蚀牺牲层及导电层，藉以在相邻的垂直有源条纹(例如，垂直有源条纹761和762)之间形成第二开口(例如开口810)之后的工艺结构剖面示意图。其中，牺牲层(例如，牺牲层420、430和440)经由第二开口暴露于外。形成由多个导电条纹(例如，导电条纹451、452、453和454)所构成的顶部阶层，以及由多个导电条纹(例如，导电条纹411、412、413和414)所构成的底部阶层。其中，构成顶部阶层的导电条纹和构成底部阶层的导电条纹与栅介电层(例如，栅介电层655、656、657、658、615、616、617和618)接触。且构成顶部阶层的导电条纹以及构成底部阶层的导电条纹，是沿着垂直X-Z阶层的Y方向设置。
图9是绘示在移除经由第二开口暴露于外的多个牺牲层，藉以在绝缘层(例如，绝缘层415、425、435和445)之间形成多个水平开口(例如，水平开口905)之后的工艺结构剖面示意图。工艺中的此步骤留下黏着于垂直有源条纹(例如，垂直有源条纹761和762)上的绝缘层以及多个水平开口(例如，水平开口905)。其中，水平开口905可用来形成字线(WLs)。牺牲层可通过使用磷酸(H3PO4)作为刻蚀剂的刻蚀工艺移除。磷酸对于使用于牺牲层中的氮化硅材质、使用于绝缘层的氧化物材质，以及使用于顶部导电层和底部导电层的N+掺杂多晶硅材质，具有相当高的选择性。
图10是绘示在水平开口中的垂直有源条纹的侧壁表面上形成存储层(例如，存储层441m、442m、443m和444m)；再经由第二开口(例如开口810)于存储层上沉积导电材质(例如导电材质1001)之后的工艺结构剖面示意图。此一导电材质可以包括氮化钛(TiN)和钨(W)。其中，第二开口的侧壁上可能余留多余的导电材质。
图11是绘示在移除余留在第二开口侧壁上的多余的导电材质之后的工艺结构剖面示意图。其中，可以采用，例如等向性刻蚀，来移除多余的导电材质。经过此一移除步骤，只有位于水平开口中的导电材质会被余留下来。藉以，在这些水平开口中，形成多个由多个导电条纹所构成的阶层。这些阶层包括多个由多个导电条纹(例如，导电条纹421、422、423、424、431、432、433、434、441、442、443和444)所构成的中间阶层(WLs)。而构成这些中间阶层的导电条纹，其侧壁表面会与存储层接触。且构成这些中间阶层的导电条纹，是沿着垂直X-Z平面的Y方向设置。
图12是绘示在第二开口(例如开口810)中，以及在绝缘层(例如，绝缘层455)上，形成绝缘材料(例如，绝缘材料1270)之后的工艺结构剖面示意图。
图13是绘示在刻蚀绝缘材料(例如，绝缘材料1270和455)之后的工艺结构剖面示意图。其中，刻蚀工艺停止于导电条纹(例如451、452、453和454)的顶部阶层和垂直有源条纹(例如，垂直有源条纹761和762)的顶部。此一工艺步骤，形成了多个由多个导电条纹所构成的叠层。每一个导电条纹的叠层，包括导电条纹(例如，导电条纹411、412、413或414)的底部阶层(GSL)、多个导电条纹(例如，导电条纹441、442、443或444)的中间阶层(WLs)以及导电条纹(例如，导电条纹451、452、453或454)的顶部阶层(SSL)。栅介电层(例如，栅介电层615、616、617、618、655、656、657和658)形成于垂直有源条纹与构成顶部阶层的导电条纹及构成底部阶层的导电条纹的侧壁表面之间的交错处的接口区中。
图14是绘示在形成间隙壁(例如间隙壁1481、1483、1485和1487)之后的工艺结构剖面示意图。其中，这些间隙壁是用来隔离垂直有源条纹(例如，垂直有源条纹761和762)和导电条纹(例如，导电条纹451、452、453和454)的顶部阶层。这些间隙壁可以是一种薄层介电衬里，且可包含氧化物材质或氮化硅材质。
图15是绘示在导电条纹(例如，导电条纹451、452、453和454)的顶部阶层上方形成金属硅化物层(例如，金属硅化物层1591，1593，1595和1597)；以及/或在垂直有源条纹(例如，垂直有源条纹761和762)顶部上形成金属硅化物层(例如，金属硅化物层1592和1596)之后的工艺结构剖面示意图。其中，这些金属硅化物层可以包括钛(Ti)、钴(Co)和镍(Ni)。继续工艺步骤以完成三维立体存储器阵列的制备。
图16至图27是根据本发明的另一实施例所绘示，制作存储器元件的一系列工艺结构剖面示意图。图4至图15绘示的工艺所制备的存储器元件包含介电层，设于垂直有源条纹与构成顶部阶层的导电条纹的侧壁表面之间的交错处的接口区中，以及设于垂直有源条纹与构成底部阶层的导电条纹的侧壁表面之间的交错处接口区的中。与其相比，图16至图27绘示的工艺所制备的存储器元件包含介电层，设于垂直有源条纹与仅构成顶部阶层的导电条纹的侧壁表面之间的交错处接口区中。在上述两实施例之中，相同的元件符号代表相同元件。
图16是沿着X-Z平面所绘示的存储器元件半成品的结构剖面示意图。在图16中，存储器元件包括位于集成电路基材上方的，多个用来形成字线(WLs)的牺牲层(例如，牺牲层420、430和440)以及用来形成接地选择线(GSL)的牺牲层(例如，牺牲层410a)。其中，这些牺牲层和导电层彼此被绝缘层(例如，绝缘层405、415、425、435、445和445)所隔离。用来形成字线(WLs)的多个牺牲层和用来形成接地选择线(GSL)的牺牲层可包含氮化硅。而有关硬掩模层(例如，硬掩模层460)以及顶部导电层(例如，导电层450)的详细内容，请参照图4的相关描述。
图17是绘示在刻蚀牺牲层及导电层以形成多个第一开口(例如开口510和520)之后的工艺结构剖面示意图。其中，第一开口穿透顶部导电层(450)、用来形成字线的多个牺牲层(例如，牺牲层420、430和440)以及用来形成接地选择线(GSL)的牺牲层(例如，牺牲层410a)。而这些第一开口，是用来形成多个垂直有源条纹。
图18是绘示在第一开口(例如，开口510和520)中的顶部导电层的侧壁表面上，形成栅介电层(例如，栅介电层655、656、657和658)之后的工艺结构剖面示意图。其中，栅介电层以及制备栅介电层的热氧化工艺，已于图6中具体描述，在此不再赘述。其中，热氧化工艺并不会在用来形成接地选择线(GSL)的牺牲层(例如，牺牲层410a)上形成氧化硅材质层。
图19是绘示在第一开口之中形成多个垂直有源条纹(例如，垂直有源条纹761和762)之后的工艺结构剖面示意图。其中，这些个垂直有源条纹与形成在顶部导电层的侧壁表面上的栅介电层(例如，栅介电层655、656、657和658)接触。硬掩模层(例如，硬掩模层460)则，如图7所绘示，已被平坦化。
图20是绘示在刻蚀牺牲层及导电层，藉以在相邻的垂直有源条纹(例如，垂直有源条纹761和762)之间形成第二开口(例如开口810)之后的工艺结构剖面示意图。其中，用来形成字线的多个牺牲层(例如，牺牲层420、430和440)以及用来形成接地选择线(GSL)的牺牲层(例如，牺牲层410a)经由第二开口暴露于外。并形成由多个导电条纹(例如，导电条纹451、452、453和454)所构成的顶部阶层。其中，构成顶部阶层的导电条纹与栅介电层(例如，栅介电层655、656、657和658)接触。
图21是绘示在移除经由第二开口暴露于外的多个牺牲层，藉以在绝缘层(例如，绝缘层415、425、435和445)之间形成多个水平开口(例如，水平开口905)之后的工艺结构剖面示意图。经过这个工艺步骤，黏着于垂直有源条纹(例如，垂直有源条纹761和762)上的绝缘层被余留下来，藉以形成位于绝缘层之间的多个水平开口(例如，水平开口905和906)。其中，水平开口905是用来形成字线(WLs)；而水平开口906则是用来形成接地选择线(GSL)。
图22是绘示在水平开口中的垂直有源条纹的侧壁表面上，形成用来形成字线(WLs)的存储层(例如，存储层441m、442m、443m和444m)，以及形成用来形成接地选择线(GSL)的存储层(例如，存储层411m、412m、413m和414m)；再经由第二开口(例如开口810)于存储层上沉积导电材质(例如导电材质1001)之后的工艺结构剖面示意图。此一导电材质可以包括氮化钛和钨。第二开口的侧壁上可能余留多余的导电材质。
图23是绘示在移除遗留在第二开口侧壁上的多余导电材质之后的工艺结构剖面示意图。其中，可以采用，例如等向性刻蚀，来移除多余的导电材质。经过此一移除步骤，只有位于水平开口中的导电材质会被余留下来。藉以，在水平开口中，形成多个由多个导电条纹所构成的阶层。这些阶层，包括多个由导电条纹(例如，导电条纹421、422、423、424、431、432、433、434、441、442、443和444)所构成的中间阶层(WLs)，以及一个由导电条纹(例如，导电条纹411a、412a、413a和414a)所构成的底部阶层(GSL)。而构成这些中间阶层的导电条纹和构成底部阶层的导电条纹，其侧壁表面分别与存储层(例如，存储层411m、412m、413m、414m、441m、442m、443m和444m)接触。
图24是绘示在第二开口(例如开口810)中，以及在绝缘层(例如，绝缘层455)上，形成绝缘材料(例如，绝缘材料1270)之后的工艺结构剖面示意图。
图25是绘示在刻蚀绝缘材料(例如，绝缘材料1270和455)之后的工艺结构剖面示意图。其中，刻蚀工艺停止于导电条纹(例如451、452、453和454)的顶部阶层和垂直有源条纹(例如，垂直有源条纹761和762)的顶部。此一工艺步骤形成了多个由多个导电条纹所构成的叠层。每一个叠层，包括一个导电条纹(例如，导电条纹411a、412a、413a或414a)的底部阶层(GSL)、多个导电条纹(例如，导电条纹441、442、443或444)的中间阶层(WLs)以及一个导电条纹(例如，导电条纹451、452、453或454)的底部阶层(GSL)。栅介电层(例如，栅介电层655、656、657和658)，形成于垂直有源条纹与构成顶部阶层的导电条纹的侧壁表面之间的交错处接口区中。包含电荷储存结构的存储层(例如，存储层411m、412m、413m和414m)，则形成于垂直有源条纹与构成底部阶层的导电条纹的侧表面之间的交错处接口区中。
图26是绘示在形成间隙壁(例如间隙壁1481、1483、1485和1487)之后的工艺结构剖面示意图。其中，这些间隙壁是用来隔离垂直有源条纹(例如，垂直有源条纹761和762)与导电条纹(例如，导电条纹451、452、453和454)的顶部阶层。这些间隙壁可以是一种薄层介电衬里，且可包含氧化物材质或氮化硅材质。
图27是绘示在导电条纹(例如，导电条纹451、452、453和454)的顶部阶层上方形成金属硅化物层(例如，金属硅化物层1591，1593，1595，1597)；以及/或在垂直有源条纹(例如，垂直有源条纹761和762)顶部形成金属硅化物层(例如，金属硅化物层1592和1596)之后的工艺结构剖面示意图。其中，这些金属硅化物层可以包括，钛、钴和镍。后续，再继续其他工艺步骤，以完成三维立体存储器阵列的制备。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视随附的权利要求范围所界定的为准。
Claims (15)
1.一种存储器元件，包括一串接存储单元阵列，包括：
由绝缘材质所分离的多个导电条纹的多个叠层，包括至少由多个导电条纹所构成的一底部阶层、由多个导电条纹所构成的多个中间阶层、以及由多个导电条纹所构成的一顶部阶层；
多个垂直有源条纹，位于这些叠层之间；
多个电荷储存结构，位于这些叠层中的这些中间阶层的这些导电条纹的多个侧壁表面，与这些垂直有源条纹之间的多个交错处的接口区中；以及
一栅介电层，具有与这些电荷储存结构相异的材质，且位于该顶部阶层的这些导电条纹和该底部阶层的这些导电条纹二者至少一者的多个侧壁表面，与这些垂直有源条纹之间的多个交错处的接口区中。
2.根据权利要求1所述的存储器元件，包括多个金属硅化物层，位于该顶部阶层的导电条纹上。
3.根据权利要求1所述的存储器元件，包括：
多个间隙壁，用来隔离该顶部阶层的导电条纹和这些垂直有源条纹；以及
多个金属硅化物层，形成在这些垂直有源条纹的顶部上。
4.根据权利要求1所述的存储器元件，其中该栅介电层包括一氧化硅材质层，具有小于这些电荷储存结构的一厚度。
5.根据权利要求1所述的存储器元件，更包括一参考导体层，位于该底部阶层的导电条纹和一集成电路基材之间的一层次中，并且连接至这些垂直有源条纹。
6.根据权利要求5所述的存储器元件，其中该参考导体层包含N+掺杂的半导体材质。
7.一种存储器元件的制作方法，包括：
在一集成电路基材上形成被多个绝缘层所分开的多个牺牲层、以及一顶部导电层和一底部导电层其中至少一个；
刻蚀这些牺牲与导电层以形成多个第一开口；
在这些第一开口中的该顶部导电层和该底部导电层其中该至少一个的多个侧壁表面上形成一栅介电层；
于这些第一开口之中，形成多个垂直有源条纹，并使这些垂直有源条纹与该栅介电层接触；
刻蚀这些牺牲与导电层和该底部导电层，以在相邻的这些垂直有源条纹之间形成多个第二开口，藉此将这些牺牲层暴露于外，且藉此在该顶部导电层和该底部导电层其中该至少一个中，形成由多个导电条纹所构成的一顶部阶层和由多个导电条纹所构成的一底部阶层中至少一个；
移除由这些第二开口暴露于外的这些牺牲层，藉以在这些绝缘层之间形成多个水平开口；
于这些水平开口中的这些垂直有源条纹的多个侧壁表面上形成一存储层；
于这些水平开口中形成由多个导电条纹所构成的多个阶层，使构成这些阶层的这些导电条纹的多个侧壁表面与该存储层接触；其中该栅介电层具有与该存储层相异的材质。
8.根据权利要求7所述的存储器元件的制作方法，更包括于这些第二开口中形成绝缘材料。
9.根据权利要求7所述的存储器元件的制作方法，更包括：
形成多个间隙壁，用来隔离该顶部阶层的导电条纹和这些垂直有源条纹；以及
在这些垂直有源条纹的顶部上形成多个金属硅化物层。
10.根据权利要求7所述的存储器元件的制作方法，更包括，在该顶部阶层的导电条纹上形成多个金属硅化物层。
11.根据权利要求7所述的存储器元件的制作方法，其中构成该顶部阶层的这些导电条纹具有多个侧壁表面与该栅介电层接触。
12.根据权利要求7所述的存储器元件的制作方法，其中构成该底部阶层的这些导电条纹具有多个侧壁表面与该栅介电层接触。
13.根据权利要求7所述的存储器元件的制作方法，其中该栅介电层包括一氧化硅材质层，具有小于该存储层的一厚度。
14.根据权利要求7所述的存储器元件的制作方法，更包括于该牺牲与导电层和该集成电路基材之间的一层次(level)中形成一参考导体层，并使该参考导体层与这些垂直有源条纹连接。
15.根据权利要求14所述的存储器元件的制作方法，其中该参考导体层包含N+掺杂的半导体材质。
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