US7166533B2 - Phase change memory cell defined by a pattern shrink material process - Google Patents
Phase change memory cell defined by a pattern shrink material process Download PDFInfo
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- US7166533B2 US7166533B2 US11/101,974 US10197405A US7166533B2 US 7166533 B2 US7166533 B2 US 7166533B2 US 10197405 A US10197405 A US 10197405A US 7166533 B2 US7166533 B2 US 7166533B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/066—Patterning of the switching material by filling of openings, e.g. damascene method
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/068—Patterning of the switching material by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8413—Electrodes adapted for resistive heating
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors
Definitions
- Phase-change memories include phase-change materials that exhibit at least two different states.
- Phase-change material may be used in a memory cell to store a bit of data.
- the states of phase-change material may be referenced to as amorphous and crystalline states.
- the states may be distinguished because the amorphous state generally exhibits higher resistivity than does the crystalline state.
- the amorphous state involves a more disordered atomic structure, while the crystalline state is an ordered lattice.
- Phase change in the phase-change materials may be induced reversibly.
- the memory may change from the amorphous state to the crystalline state, and vice versa, in response to temperature changes.
- the temperature changes to the phase-change material may be achieved in a variety of ways.
- a laser can be directed to the phase-change material, current may be driven through the phase-change material, or current or voltage can be fed through a resistive heater adjacent the phase change material.
- controllable heating of the phase-change material causes controllable phase change within the phase change-material.
- phase-change memory comprises a memory array having a plurality of memory cells that are made of phase-change material
- the memory may be programmed to store data utilizing the memory states of the phase-change material.
- One way to read and write data in such a phase-change memory device is to control a current and/or voltage pulse that is applied to the phase-change material.
- the level of current and voltage generally corresponds to the temperature induced within the phase-change material in each memory cell.
- the size of the electrical contact for the phase-change material of the memory cell should be minimized.
- the memory cell device includes a first electrode, a phase-change material adjacent the first electrode, and a second electrode adjacent the phase-change material.
- the phase-change material has a sublithographic width defined by a pattern shrink material process.
- FIG. 1 is a block diagram illustrating one embodiment of a memory cell device.
- FIG. 2 illustrates a cross-sectional view through one embodiment of a phase-change memory cell.
- FIG. 3 illustrates a cross-sectional view of one embodiment of a preprocessed wafer.
- FIG. 4 illustrates a cross-sectional view of one embodiment of the preprocessed wafer and an isolation material layer.
- FIG. 5 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, and a mask layer.
- FIG. 6 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, mask layer, and a pattern shrink material layer.
- FIG. 7A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, mask layer, and a SAFIERTM material layer after baking.
- FIG. 7B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, mask layer, a compound material layer, and a RELACSTM material layer after baking.
- FIG. 8A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, and mask layer after removing the SAFIERTM material layer.
- FIG. 8B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, mask layer, and compound material layer after removing the RELACSTM material layer.
- FIG. 9 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, and mask layer after etching the isolation material layer.
- FIG. 10 illustrates a cross-sectional view of one embodiment of the preprocessed wafer and isolation material layer after removing the mask layer.
- FIG. 11 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, and a phase-change material layer.
- FIG. 12 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, and phase-change material layer after planarization.
- FIG. 13 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, phase-change material layer, and a second electrode material layer.
- FIG. 14 illustrates a cross-sectional view through one embodiment of a heater phase-change memory cell.
- FIG. 15 illustrates a cross-sectional view of one embodiment of a preprocessed wafer.
- FIG. 16 illustrates a cross-sectional view of one embodiment of the preprocessed wafer and an isolation material layer.
- FIG. 17 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, and a mask layer.
- FIG. 18 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, mask layer, and a pattern shrink material layer.
- FIG. 19A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, mask layer, and a SAFIERTM material layer after baking.
- FIG. 19B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, mask layer, a compound material layer, and a RELACSTM material layer after baking.
- FIG. 20A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, and mask layer after removing the SAFIERTM material layer.
- FIG. 20B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, mask layer, and compound material layer after removing the RELACSTM material layer.
- FIG. 21 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, and mask layer after etching the isolation material layer.
- FIG. 22 illustrates a cross-sectional view of one embodiment of the preprocessed wafer and isolation material layer after removing the mask layer.
- FIG. 23 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, and a heater material layer.
- FIG. 24 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, and heater material layer after planarization.
- FIG. 25 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, isolation material layer, a phase-change material layer, and a second electrode material layer.
- FIG. 26 is a plot illustrating one embodiment of the correlation between the mask critical dimension and hole pitch to the shrink amount for the SAFIERTM process.
- FIG. 27 is a plot illustrating one embodiment of the correlation between the hole pitch to the critical dimension percentage dose for the SAFIERTM process.
- FIG. 1 is a block diagram illustrating one embodiment of a memory cell device 50 .
- Memory cell device 50 includes write pulse generator 52 , distribution circuit 56 , memory cells 54 a , 54 b , 54 c , and 54 d , and a sense amplifier 58 .
- memory cells 54 a – 54 d are phase-change memory cells that are based on the amorphous to crystalline phase transition of the memory material.
- Phase change memory cells 54 a – 54 d are fabricated using a Shrink Assist Film for Enhanced Resolution (SAFIERTM) material available from Tokyo Ohka Kogyo Co., Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACSTM) material available from AZ Electronic Materials, or other suitable pattern shrink material.
- SAFIERTM Shrink Assist Film for Enhanced Resolution
- RELACSTM Resolution Enhancement Lithography Assisted by Chemical Shrink
- Pattern shrink material as used herein is defined as any suitable material that when coated onto patterned photoresist and then heated reduces the line widths of the patterned photoresist.
- the pattern shrink material provides memory storage locations having a sublithographic width by reducing the width of openings in a patterned photoresist mask used for defining the memory storage locations. Examples of the SAFIERTM process and the RELACSTM process are described in Kim, H. W., “Analytical Study on Small Contact Hole Process for Sub-65 nm Node Generation.” JVSTB 22(6), L38, 2004.
- write pulse generator 52 generates current or voltage pulses that are controllably directed to memory cells 54 a – 54 d via distribution circuit 56 .
- distribution circuit 56 is a plurality of transistors that controllably direct current or voltage pulses to the memory, and in another embodiment, is a plurality of transistors that controllably direct current or voltage pulses to heaters adjacent to the phase-change memory cells.
- memory cells 54 a – 54 d are made of a phase-change material that can be changed from an amorphous state to a crystalline state or from a crystalline state to an amorphous state under influence of temperature change.
- the degree of crystallinity thereby defines at least two memory states for storing data within memory cell device 50 , which can be assigned to the bit values “0” and “1”.
- the bit states of memory cells 54 a – 54 d differ significantly in their electrical resistivity. In the amorphous state, a phase-change material exhibits significantly higher resistivity than in the crystalline state. In this way, sense amplifier 58 reads the cell resistance such that the bit value assigned to a particular memory cell 54 a – 54 d is determined.
- write pulse generator 52 To program a memory cell 54 a – 54 d within memory cell device 50 , write pulse generator 52 generates a current or voltage pulse for heating the phase-change material in the target memory cell. In one embodiment, write pulse generator 52 generates an appropriate current or voltage pulse, which is fed into distribution circuit 56 and distributed to the appropriate target memory cell 54 a – 54 d . The current or voltage pulse amplitude and duration is controlled depending on whether the memory cell is being set or reset. Generally, a “set” operation of a memory cell is heating the phase-change material of the target memory cell above its crystallization temperature (but below its melting temperature) long enough to achieve the crystalline state. Generally, a “reset” operation of a memory cell is quickly heating the phase-change material of the target memory cell above its melting temperature, and then quickly quench cooling the material, thereby achieving the amorphous state.
- FIG. 2 illustrates a cross-sectional view through one embodiment of a phase-change memory cell 100 .
- Phase-change memory cell 100 includes a first electrode 102 , phase-change material 106 , a second electrode 108 , insulator material 104 , and isolation material 110 .
- isolation material 110 comprises insulator material 104 .
- Phase-change material 106 provides a storage location for storing one bit or several bits of data. Phase-change material 106 is laterally completely enclosed by isolation material 110 , which defines the current path and hence the location of the phase-change region in phase-change material 106 .
- phase-change material 106 is a sublithographic width defined by a SAFIERTM material process, RELACSTM material process, or other suitable pattern shrink material process.
- a selection device such as an active device like a transistor or diode, is coupled to first electrode 102 to control the application of current or voltage to first electrode 102 , and thus to phase-change material 106 , to set and reset phase-change material 106 .
- phase-change material 106 reaches its crystalline state during this set operation.
- a reset current and/or voltage pulse is selectively enabled by the selection device and sent through first electrode 102 to phase-change material 106 .
- the reset current or voltage quickly heats phase-change material 106 above its melting temperature, and then phase-change material 106 is quickly quench cooled to achieve its amorphous state.
- isolation material 110 is a good thermal insulator dielectric material such as a porous oxide film having a thermal conductivity between 0.1 and 0.8 W/mK.
- isolation material 110 may be a dielectric material such as Aerogel material with a thermal conductivity of about 0.12–0.18 W/mK, and in another it may be a templated porous oxide dielectric such as Philk with a thermal conductivity of about 0.13–0.17 W/mK.
- Phase-change material 106 may be made up of a variety of materials in accordance with the present invention. Generally, chalcogenide alloys that contain one or more elements from Column IV of the periodic table are useful as such materials.
- phase-change material 106 of memory cell 100 is made up of a chalcogenide compound material, such as GeSbTe or AgInSbTe.
- the phase change material can be chalcogen-free such as GeSb, GaSb or GeGaSb.
- FIGS. 3–13 illustrate embodiments of a process for fabricating phase-change memory cell 100 using a pattern shrink material, such as SAFIERTM material or RELACSTM material.
- a pattern shrink material such as SAFIERTM material or RELACSTM material.
- the figure numbers followed by an “A” illustrate portions of the fabrication process when using SAFIERTM material as the pattern shrink material.
- the figure numbers followed by a “B” illustrate portions of the fabrication process when using RELACSTM material as the pattern shrink material.
- the process can also be performed using other pattern shrink materials similar to SAFIERTM material and RELACSTM material.
- FIG. 3 illustrates a cross-sectional view of one embodiment of a preprocessed wafer 105 .
- Preprocessed wafer 105 includes insulation material 104 , first electrode 102 , optional contact material 112 , and lower wafer layers (not shown). In other embodiments, contact material 112 is excluded.
- First electrode 102 is a tungsten plug, copper plug, or another suitable electrode.
- Insulation material 104 is SiO 2 or other suitable insulating material.
- Contact material 112 comprises Ta, TaN, TiN, or another suitable contact material.
- Optional contact material 112 is provided in one embodiment by etching first electrode 102 to form a recess, filling the recess with contact material 112 , and planarizing to provide preprocessed wafer 105 . In other embodiments, contact material 112 is provided using another suitable process.
- FIG. 4 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 and an insulation material layer 110 a .
- a planar deposition of isolation material such as SiO 2 , a low k material, SiN, or other suitable isolation material, over preprocessed wafer 105 provides isolation material layer 110 a .
- Isolation material layer 110 a is deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), plasma vapor deposition (PVD), jet vapor deposition (JVP), or other suitable deposition technique.
- CVD chemical vapor deposition
- ALD atomic layer deposition
- MOCVD metal organic chemical vapor deposition
- PVD plasma vapor deposition
- JVP jet vapor deposition
- FIG. 5 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 a , and a mask layer 114 a .
- mask layer 114 a is provided by spin coating photoresist onto isolation material layer 110 a and performing optical lithography to define mask layer 114 a having an opening 113 a .
- an anti-reflective coating is spin coated onto isolation material layer 110 a before applying the photoresist. The anti-reflective coating is removed from opening 113 a using a dry etch.
- opening 113 a is a cylindrical opening above a single first electrode 102 .
- opening 113 a is a trench opening that extends across one or an array of first electrodes 102 . Opening 113 a is defined by a lithographic width 115 a . In one embodiment, opening 113 a in mask layer 114 a is positioned approximately above the center of first electrode 102 .
- FIG. 6 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 a , mask layer 114 a , and a pattern shrink material layer 116 a , such as a SAFIERTM or RELACSTM material layer.
- Pattern shrink material layer 116 a is spin coated or applied using another suitable method onto exposed portions of mask layer 114 a and isolation material layer 110 a.
- FIG. 7A illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 a , mask layer 114 b , and a SAFIERTM material layer 116 b after baking.
- preprocessed wafer 105 , isolation material layer 110 a , mask layer 114 a , and SAFIERTM material layer 116 a are baked at approximately 150–165° C. for approximately one minute to provide SAFIERTM material layer 116 b and mask layer 114 b having opening 113 b .
- Opening 113 b is defined by a sublithographic width 115 b .
- the baking shrinks SAFIERTM material layer 116 a and flows the photoresist of mask layer 114 a while maintaining the shape of the sidewalls of opening 113 a .
- the shrink rate and the photoresist profile are a function of the bake temperature.
- the baking reduces width 115 a of opening 113 a in mask layer 114 a to provide mask layer 114 b having opening 113 b with width 115 b .
- the baking is repeated to further reduce the width 115 b of opening 113 b in mask layer 114 b .
- the baking reduces the line edge roughness of the sidewalls of opening 113 b.
- FIG. 7B illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 a , mask layer 114 c , a compound material layer 118 , and a RELACSTM material layer 116 c after baking.
- Preprocessed wafer 105 , isolation material layer 110 a , mask layer 114 a , and RELACSTM material layer 116 a are baked to provide RELACSTM material layer 116 c , a conformal compound material layer 118 and mask layer 114 c having opening 113 c .
- Opening 113 c is defined by a sublithographic width 115 c .
- the baking reduces the width 115 a of opening 113 a in mask layer 114 a to provide mask layer 114 c and conformal compound material layer 118 having opening 113 c with width 115 c .
- Conformal compound material layer 118 is produced by a chemical reaction between RELACSTM material layer 116 a and the photoresist of mask layer 114 a during baking.
- FIG. 8A illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 a , and mask layer 114 b after removing SAFIERTM material layer 116 b .
- SAFIERTM material layer 116 b is removed using a DI water rinse or another suitable method.
- SAFIERTM material is again applied to exposed portions of mask layer 114 b and insulation material layer 110 a , baked, and removed repeatedly until the desired width 115 of opening 113 in mask layer 114 b is obtained.
- FIG. 8B illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 a , mask layer 114 c , and compound material layer 118 after removing RELACSTM material layer 116 c .
- RELACSTM material layer 116 c is removed using a DI water rinse or another suitable method.
- FIG. 9 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 , and mask layer 114 b after etching isolation material layer 110 a .
- FIG. 9 illustrates mask layer 114 b after removing the SAFIERTM material.
- the portion of isolation material layer 110 a that is etched is defined by mask layer 114 c and compound material layer 118 as illustrated in FIG. 8B .
- isolation material layer 110 a is etched using a reactive ion etch (RIE) or other suitable etch to provide isolation material layer 110 and expose first electrode 102 .
- RIE reactive ion etch
- FIG. 10 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 and isolation material layer 110 after removal of mask layer 114 b or mask layer 114 c and compound material layer 118 .
- Mask layer 114 b or mask layer 114 c and compound material layer 118 are removed using a photoresist stripping process.
- FIG. 11 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 , and a phase-change material layer 106 a .
- Phase-change material such as a calcogenic compound material or other suitable phase change material, is deposited over exposed portions of isolation material layer 110 and first electrode 102 to provide phase-change material layer 106 a .
- Phase-change material layer 106 a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
- FIG. 12 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 , and phase-change material layer 106 after planarizing phase-change material layer 106 a .
- phase-change material layer 106 a is planarized using chemical mechanical polishing (CMP) or another suitable planarizing technique to provide phase-change material layer 106 .
- CMP chemical mechanical polishing
- FIG. 13 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 , phase-change material layer 106 , and a second electrode material layer 108 a .
- a planar deposition of electrode material, such as TiN, TaN, or another suitable electrode material, over phase-change material layer 106 and isolation material layer 110 provides second electrode material layer 108 a .
- Second electrode material layer 108 a is etched to provide second electrode 108 and phase-change memory cell 100 as illustrated in FIG. 2 .
- second electrode 108 provides a landing pad for the next level metallization plug.
- FIG. 14 illustrates a cross-sectional view through one embodiment of a heater phase-change memory cell 101 .
- Heater phase-change memory cell 101 includes a first electrode 102 , a heater 120 , phase-change material 106 , a second electrode 108 , insulator material 104 , and isolation material 110 .
- isolation material 110 comprises insulator material 104 .
- Heater 120 is laterally completely enclosed by isolation material 110 , which defines the current path and hence the location of the phase-change region in phase-change material 106 .
- Phase-change material 106 provides a storage location for storing one bit or several bits of data.
- a selection device such as an active device like a transistor or diode, is coupled to first electrode 102 to control the application of current or voltage to first electrode 102 , and thus to heater 120 and phase-change material 106 , to set and reset phase-change material 106 .
- a set current or voltage pulse is selectively enabled to heater 120 thereby heating phase-change material 106 above its crystallization temperature (but below its melting temperature). In this way, phase-change material 106 reaches its crystalline state during this set operation.
- a reset current and/or voltage pulse is selectively enabled by the selection device and sent through first electrode 102 to heater 120 and phase-change material 106 . The reset current or voltage quickly heats phase-change material 106 above its melting temperature, and then phase-change material 106 is quickly quench cooled to achieve its amorphous state.
- FIGS. 15–25 illustrate embodiments of a process for fabricating heater phase-change memory cell 101 using a pattern shrink material, such as SAFIERTM material or RELACSTM material.
- a pattern shrink material such as SAFIERTM material or RELACSTM material.
- the figure numbers followed by an “A” illustrate portions of the fabrication process for using SAFIERTM material as the pattern shrink material.
- the figure numbers followed by a “B” illustrate portions of the fabrication process for using RELACSTM material as the pattern shrink material.
- the process can also be performed using other pattern shrink materials similar to SAFIERTM material and RELACSTM material.
- FIG. 15 illustrates a cross-sectional view of one embodiment of a preprocessed wafer 105 .
- Preprocessed wafer 105 includes insulation material 104 , first electrode 102 , optional contact material 112 , and lower wafer layers (not shown). In other embodiments, contact material 112 is excluded.
- First electrode 102 is a tungsten plug, copper plug, or another suitable electrode.
- Insulation material 104 is SiO 2 or other suitable insulating material.
- Contact material 112 comprises Ta, TaN, TiN, or another suitable contact material.
- Optional contact material 112 is provided in one embodiment by etching first electrode 102 to form a recess, filling the recess with contact material 112 , and planarizing to provide preprocessed wafer 105 . In other embodiments, contact material 112 is provided using another suitable process.
- FIG. 16 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 and an insulation material layer 110 a .
- a planar deposition of isolation material such as SiO 2 , a low k material, SiN, or other suitable isolation material, over preprocessed wafer 105 provides isolation material layer 110 a .
- Isolation material layer 110 a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
- FIG. 17 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 a , and a mask layer 114 a .
- mask layer 114 a is provided by spin coating photoresist onto isolation material layer 110 a and performing optical lithography to define mask layer 114 a having an opening 113 a .
- opening 113 a is a cylindrical opening above a single first electrode 102 .
- opening 113 a is a trench opening that extends across one or an array of first electrodes 102 .
- Opening 113 a is defined by a lithographic width 115 a .
- opening 113 a in mask layer 114 a is positioned approximately above the center of first electrode 102 .
- FIG. 18 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 a , mask layer 114 a , and a pattern shrink material layer 116 a , such as a SAFIERTM or RELACSTM material layer.
- Pattern shrink material layer 116 a is spin coated or applied using another suitable method onto exposed portions of mask layer 114 a and isolation material layer 110 a.
- FIG. 19A illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 a , mask layer 114 b , and a SAFIERTM material layer 116 b after baking.
- preprocessed wafer 105 , isolation material layer 110 a , mask layer 114 a , and SAFIERTM material layer 116 a are baked at approximately 150–165° C. for approximately one minute to provide SAFIERTM material layer 116 b and mask layer 114 b having opening 113 b .
- Opening 113 b is defined by a sublithographic width 115 b .
- the baking shrinks SAFIERTM material layer 116 a and flows the photoresist of mask layer 114 a while maintaining the shape of the sidewalls of opening 113 a .
- the shrink rate and the photoresist profile are a function of the bake temperature.
- the baking reduces width 115 a of opening 113 a in mask layer 114 a to provide mask layer 114 b having opening 113 b with width 115 b .
- the baking is repeated to further reduce the width 115 b of opening 113 b in mask layer 114 b .
- the baking reduces the line edge roughness of the sidewalls of opening 113 b.
- FIG. 19B illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 a , mask layer 114 c , a compound material layer 118 , and a RELACSTM material layer 116 c after baking.
- Preprocessed wafer 105 , isolation material layer 110 a , mask layer 114 a , and RELACSTM material layer 116 a are baked to provide RELACSTM material layer 116 c , a conformal compound material layer 118 and mask layer 114 c having opening 113 c .
- Opening 113 c is defined by a sublithographic width 115 c .
- the baking reduces the width 115 a of opening 113 a in mask layer 114 a to provide mask layer 114 c and conformal compound material layer 118 having opening 113 c with width 115 c .
- Conformal compound material layer 118 is produced by a chemical reaction between RELACSTM material layer 116 a and the photoresist of mask layer 114 a during baking.
- FIG. 20A illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 a , and mask layer 114 b after removing SAFIERTM material layer 116 b .
- SAFIERTM material layer 116 b is removed using a DI water rinse or another suitable method.
- SAFIERTM material is again applied to exposed portions of mask layer 114 b and insulation material layer 110 a , baked, and removed repeatedly until the desired width 115 of opening 113 in mask layer 114 b is obtained.
- FIG. 20B illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 a , mask layer 114 c , and compound material layer 118 after removing RELACSTM material layer 116 c .
- RELACSTM material layer 116 c is removed using a DI water rinse or another suitable method.
- FIG. 21 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 , and mask layer 114 b after etching isolation material layer 110 a .
- FIG. 21 illustrates mask layer 114 b after removing the SAFIERTM material.
- the portion of isolation material layer 110 a that is etched is defined by mask layer 114 c and compound material layer 118 as illustrated in FIG. 20B .
- isolation material layer 110 a is etched using a RIE etch or other suitable etch to provide isolation material layer 110 and expose first electrode 102 .
- FIG. 22 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 and isolation material layer 110 after removal of mask layer 114 b or mask layer 114 c and compound material layer 118 .
- Mask layer 114 b or mask layer 114 c and compound material layer 118 are removed using a photoresist stripping process.
- FIG. 23 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 , and a heater material layer 120 a .
- Heater material such as TiN, TaN, or another suitable heater material is deposited over exposed portions of isolation material layer 110 and first electrode 102 using CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique.
- FIG. 24 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 , and heater material layer 120 after planarizing heater material layer 120 a to expose isolation material layer 110 .
- heater material layer 120 a is planarized using. CMP or other suitable planarization method to provide heater material layer 120 .
- FIG. 25 illustrates a cross-sectional view of one embodiment of preprocessed wafer 105 , isolation material layer 110 , heater material layer 120 , a phase-change material layer 106 a , and a second electrode material layer 108 a .
- a planar deposition of phase-change material such as a calcogenic compound material or another suitable phase-change material, over isolation material layer 110 and heater material layer 120 provides phase-change material layer 106 a .
- phase-change material such as a calcogenic compound material or another suitable phase-change material
- electrode material such as TiN, TaN, or another suitable electrode material
- Phase-change material layer 106 a and second electrode material layer 108 a are deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. Second electrode material layer 108 a and phase-change material layer 106 a are etched to provide second electrode 108 and phase-change material 106 as illustrated in FIG. 14 . In one embodiment, second electrode 108 provides a landing pad for the next level metallization plug.
- FIG. 26 is a plot 200 illustrating one embodiment of the correlation between the mask critical dimension and hole pitch to the shrink amount for the SAFIERTM process.
- the shrink amount increases as the mask critical dimension increases.
- the shrink amount increases based on the increase in the mask critical dimension.
- errors in the mask critical dimension are compensated for using the SAFIERTM process. Therefore, relatively small fluctuations in the critical dimension of the mask are not amplified into relatively large fluctuations after the lithographic process is complete since larger holes shrink more than smaller holes using the SAFIERTM process.
- FIG. 27 is a plot 220 illustrating one embodiment of the correlation between the hole pitch to the critical dimension percentage dose for the SAFIERTM process. As illustrated in plot 220 , the critical dimension percentage dose for the SAFIERTM process is fairly independent of the hole pitch. This characteristic of the SAFIERTM process improves the stability of the process.
- Embodiments of the present invention provide phase-change memory cells having storage locations with sublithographic dimensions by using pattern shrink material processes. By reducing the size of the memory cells, the amount of power that is used in each memory cell can be reduced.
Abstract
Description
Claims (38)
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US11/101,974 US7166533B2 (en) | 2005-04-08 | 2005-04-08 | Phase change memory cell defined by a pattern shrink material process |
PCT/EP2006/003089 WO2006108541A1 (en) | 2005-04-08 | 2006-04-05 | Phase change memory cell defined by a pattern shrink material process |
DE112006000072T DE112006000072T5 (en) | 2005-04-08 | 2006-04-05 | Phase change memory cell defined by a pattern shrinkage material method |
KR1020077006304A KR20070088524A (en) | 2005-04-08 | 2006-04-05 | Phase change memory cell defined by a pattern shrink material process |
US11/502,078 US20060270216A1 (en) | 2005-04-08 | 2006-08-10 | Phase change memory cell defined by a pattern shrink material process |
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US20060228883A1 (en) | 2006-10-12 |
KR20070088524A (en) | 2007-08-29 |
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WO2006108541A1 (en) | 2006-10-19 |
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