US20070235811A1 - Simultaneous conditioning of a plurality of memory cells through series resistors - Google Patents

Simultaneous conditioning of a plurality of memory cells through series resistors Download PDF

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US20070235811A1
US20070235811A1 US11/400,596 US40059606A US2007235811A1 US 20070235811 A1 US20070235811 A1 US 20070235811A1 US 40059606 A US40059606 A US 40059606A US 2007235811 A1 US2007235811 A1 US 2007235811A1
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memory elements
current
electrodes
series resistor
series
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US11/400,596
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Toshijaru Furukawa
Mark Hakey
Steven Holmes
David Horak
Charles Koburger
Chung Lam
Gerhard Meijer
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GlobalFoundries Inc
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International Business Machines Corp
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Publication of US20070235811A1 publication Critical patent/US20070235811A1/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/24Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures

Abstract

Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.

Description

    BACKGROUND
  • 1. Field of the Invention
  • The present invention relates generally to a non-volatile memory device and an associated fabrication method. Particularly, the invention relates to a non-volatile memory device that incorporates a series of memory cells having memory elements comprising a bi-stable layer with programmable electrical resistance sandwiched between two conductive layers. Additionally, the invention relates to a method for manufacturing the non-volatile memory device that incorporates a process for simultaneously conditioning the transition metal oxide layer of each memory cell in a series such that the transition metal oxide layers exhibit a bi-stable electrical resistance.
  • 2. Description of the Related Art
  • Flash erasable programmable read only memory (FEPROM or flash memory) is used in semiconductor devices and provides for rapid block erase operations. Flash memory generally requires only the use of one transistor per memory cell versus the two transistors per memory cell required for conventional electrically erasable programmable read only memory (EEPROM). Thus, flash memory takes up less space on a semiconductor device and is less expensive to produce. However, the need to develop further space saving components and to remain cost efficient in the fabrication of semiconductor devices continues. To that end, the use of materials with programmable electrical resistance for semiconductor device applications has been studied. The electrical resistance of resistance-switching materials, including but not limited to transition metal oxide materials, can be changed significantly by external influences, including temperature, magnetic fields and electric fields. Electrical impulses applied to theses materials can “program” them, such that they exhibit a desired resistive property. Specifically, the following referenced articles, international application and U.S. Patent, all of which are hereby expressly incorporated by reference into the present invention for purposes including, but not limited to, indicating the background of the present invention and illustrating the state of the art, describe materials and classes of materials with programmable electrical resistance and simple electrical resistor devices made from these materials: “Reproducible switching effect in thin oxide films for memory applications” (A. Beck et al., Applied Physics Letters, Vol. 77, No. 1, July 2000); “Current-driven insulator-conductor transition and non-volatile memory in chromium-doped SrTiO3 single crystals” (Y. Watanabe et al., Applied Physics Letters, Vol. 78, No. 23, June 2001); “Electrical current distribution across a metal-insulator-metal structure during bi-stable switching” (C. Rossel et al., Journal of Applied Physics, Vol. 90, No. 6, September 2001); U.S. Pat. No. 6,815,744 issued to Beck et al. on Nov. 9, 2004; and, U.S. Pat. No. 6,204,139 issued to Liu et al. on Mar. 20, 2001.
  • Transition metal oxide materials are one class of materials that can be conditioned such that they exhibit a bi-stable electrical resistance and, therefore, they have a wide range of potential applications. This conditioning process involves subjecting the insulating dielectric material to an appropriate electrical signal for a sufficient period of time in order to generate a confined conductive region in the transition metal oxide that can be reversibly switched between two or more resistance states. However, there is a large variation in the time required for conditioning transition metal oxides. Due to this large time variation, bulk conditioning of multiple memory elements is difficult because once a single memory element is conditioned, current must be limited in order to prevent the conditioned element from burning-out when subjected to additional current as other memory elements continue to undergo conditioning. Consequently, individual conditioning of each memory cell is generally required. This time-consuming process of conditioning each memory cell individually and the large variations in conditioning nominally identical programmable resistors used in the memory cells and in devices formed with such memory cells severely hinders manufacturability and is impractical for production type arrays. Therefore, there is a need in the art for both a semiconductor structure and a method that allow for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells.
  • SUMMARY
  • In view of the foregoing, embodiments of the invention provide both a semiconductor structure and a method that allow for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells.
  • An embodiment of the invention provides a semiconductor structure that allows for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells. The semiconductor structure comprises multiple memory cells each having a memory element. These memory elements comprise a transition metal oxide (i.e., a bi-stable layer with programmable electrical resistance) layered between first electrodes and second electrodes (i.e., each memory element comprises a transition metal oxide layer sandwiched between a first electrode and a second electrode). The semiconductor structure further comprises a temporary series resistor and/or permanent series resistors. These series resistors are configured so that they limit current passing through the memory elements during a simultaneous conditioning process. Thus, damage to the conditioned transition metal oxide in individual memory elements is avoided while other memory elements are still undergoing the conditioning process (i.e., the temporary series resistor and/or permanent series resistors limit the current passing through the memory elements to avoid damaging the transition metal oxide once it is conditioned).
  • Specifically, the semiconductor structure can comprise a blanket temporary series resistor that is electrically connected to exposed second electrodes of the memory elements. The current is then applied simultaneously to the memory elements via the temporary series resistor. This temporary series resistor can take several different forms. For example, the temporary series resistor can comprise a temporary resistive layer-metal layer stack over the memory elements such that a resistive layer of the stack contacts the second electrodes. Alternatively, the temporary series resistor can comprise an electrolyte solution or a plasma, having selected conductive and resistive properties, that is contained over the memory elements such that the electrolyte solution or plasma contacts the second electrode of each of the memory elements. Similarly, the temporary series resistor can comprise mercury that is contained over the memory elements such that the mercury contacts the second electrode of each of the memory elements. Current applied to the temporary series resistor (e.g., to the resistive layer via the metal layer, the electrolyte solution, the plasma, the mercury, etc.) from a power supply is evenly and simultaneously distributed through the temporary series resistor to the memory elements located immediately below and contacting the temporary series resistor. The size of the temporary series resistor (e.g., an area measurement defining the number of memory elements above which the temporary series resistor is positioned) is predetermined based on the output capacity of the power supply used to apply the current and by the probe contact resistance that can be tolerated in order to ensure that the current is applied equally to each of the memory elements below the resistor. Thus, a given device with multiple cells may be configured with multiple temporary series resistors, each having a predetermined size sufficient to contact the second electrodes of a group of memory elements and to ensure that those memory elements will be simultaneously conditioned.
  • In addition to or instead of the temporary series resistor, described above, the semiconductor structure of the invention can comprise permanent series resistors that are each electrically connected to corresponding first electrodes of the memory elements. As with the temporary resistor, the permanent resistors function to limit current passing through the memory elements during a simultaneous conditioning process in order to avoid damaging the transition metal oxide in each of the memory elements once conditioned. Typically, each memory cell comprises a diffusion region with a first conductivity type that contacts a corresponding first electrode of a memory element. Such memory cells also comprise a semiconductor substrate with a second conductivity type below the diffusion region. Permanent series resistors can be created by incorporating a semiconductor well into each of the memory cells. Specifically, a semiconductor well with the second conductivity type that connects the semiconductor substrate in series with the diffusion region can function as a series resistor if this semiconductor well has less of a second conductivity type dopant than the semiconductor substrate.
  • An embodiment of the invention also provides a method of simultaneously conditioning multiple memory elements in devices with multiple memory cells. The method comprises forming multiple memory cells on a semiconductor substrate. Each memory cell is formed by forming a transistor and then forming a memory element on the drain region of the transistor. Memory elements are formed by layering a transition metal oxide (i.e., a bi-stable layer with programmable electrical resistance) between first (lower) electrodes and second (upper) electrodes. The method further comprises forming a temporary series resistor over the memory cells at the wafer surface and/or permanent series resistors within the memory cells. Once the temporary and/or permanent series resistors are formed current can be simultaneously applied to the memory elements so as to condition the transition metal oxide in each of the memory elements. The series resistors are configured so that, during this simultaneous conditioning process, they limit current passing through the memory elements. Thus, damage to conditioned transition metal oxide in individual memory elements is avoided while other memory elements are still undergoing the conditioning process (i.e., the temporary series resistor and/or permanent series resistors limit the current passing through the memory elements to avoid damaging the transition metal oxide once it is conditioned).
  • Specifically, the method can comprise forming a blanket temporary series resistor over the memory elements such that the temporary series resistor contacts the second electrodes of the memory elements. The temporary series resistor can be formed using various techniques. For example, the temporary series resistor can be formed by forming a temporary resistive layer-metal layer stack over the memory elements such that a resistive layer of the stack contacts the second electrodes. Alternatively, the temporary series resistor can be formed by selecting either an electrolyte solution or plasma that has selected conductive and resistive properties and, then, containing the electrolyte solution or plasma over the memory elements such that it contacts the second electrodes. Similarly, the temporary series resistor can be formed by containing mercury over the memory elements such that the mercury contacts the second electrode of each of the memory elements.
  • Current can be simultaneously applied to the memory elements by applying current from a power supply to the temporary series resistor (e.g., to the resistive layer via the metal layer, to the electrolyte solution, to the plasma, or to the mercury). Specifically, current applied to the temporary series resistor is distributed evenly and simultaneously through the temporary series resistor to the memory elements located immediately below. A size of the blanket temporary series resistor (e.g., an area measurement defining the number of memory elements above which the temporary series resistor is positioned) can be predetermined based on the output capacity of the power supply that is used to apply the current and by the probe contact resistance that can be tolerated in order to ensure that the current is applied equally to each of the memory elements that are located below the resistor. Thus, for a given device with multiple cells multiple temporary series resistors can be formed, each having a predetermined size sufficient to contact the second electrodes of a group of memory elements and to ensure that those memory elements will be simultaneously conditioned.
  • In addition to or instead of forming the temporary series resistor, described above, the method of the invention can also comprise forming permanent series resistors that are electrically connected in series to corresponding first electrodes of the memory elements. As with the temporary resistors, these permanent resistors function to limit current passing through the memory elements during a simultaneous conditioning process in order to avoid damaging the transition metal oxide in each of the memory elements once conditioned. Permanent series resistors can be created by incorporating a semiconductor well with a second conductivity type in series between a semiconductor substrate with the same conductivity type and a diffusion region with a first conductivity type. If this semiconductor well is formed so that it has less of a second conductivity type dopant than the semiconductor substrate it will function as a series resistor.
  • These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, in which:
  • FIG. 1 is a schematic drawing illustrating a cross-section of a portion of a nonvolatile memory device with multiple memory cells;
  • FIG. 2 is a schematic drawing illustrating an embodiment of the structure of the invention;
  • FIG. 3 is a schematic drawing illustrating another embodiment of the structure of the invention;
  • FIG. 3 is a schematic drawing illustrating another embodiment of the structure of the invention;
  • FIG. 4 is a schematic drawing illustrating another embodiment of the structure of the invention;
  • FIG. 5 is a schematic drawing illustrating another embodiment of the structure of the invention;
  • FIG. 6 is a schematic drawing illustrating another embodiment of the structure of the invention;
  • FIG. 7 is a schematic drawing illustrating a top view of the structure of FIG. 2;
  • FIG. 8 is a schematic drawing illustrating another embodiment of the structure of the invention; and
  • FIG. 9 is a flow diagram illustrating an embodiment of the method of the invention.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments of the invention. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments of the invention may be practiced and to further enable those of skill in the art to practice the embodiments of the invention. Accordingly, the examples should not be construed as limiting the scope of the embodiments of the invention.
  • FIG. 1 is a cross-sectional diagram illustrating a portion of a nonvolatile memory device 100 with multiple memory cells 1. In this configuration, each memory cell 1 comprises a transistor 10. Each transistor 10 comprises a source region 11 and a drain region 12 formed in a semiconductor substrate 5. Each transistor 10 also comprises a gate electrode 13 formed on a gate dielectric film 14 above the substrate 5 between the source/drain regions 11, 12. A memory element 20 contacts the drain region 12 and comprises a variable resistor 21 (and, optionally, a platinum (Pt) layer 24) sandwiched between a first (lower) electrode 22 and a second (upper) electrode 23. The variable resistor 21 comprises a transition metal oxide (e.g., strontium titanium oxide (SrTiO3), strontium barium titanium oxide ((Sr, Ba)TiO3), praseodymium calcium manganese oxide ((Pr,Ca)MnO3), strontium zirconium oxide (SrZrO3), nickel oxide (NiO), titanium oxide (TiO2), tantalum oxide (Ta2O5), or other transition metal oxides. The transition metal oxides can be doped preferentially with chromium, manganese, or vanadium.) The transistor 10 and the variable resistor 21 of the memory element 20 are electrically connected to each other in series by contact between the drain region 12 and the first electrode 22. Additionally, the second electrode 23 is connected to metal interconnects 31 that serve as bit lines, the gate electrode 13 is connected to word lines, and the source region 11 is connected to other metal interconnects 32 that serve as common lines.
  • As discussed above, the desire resistance value of such transition metal oxides 21 in the memory element 20 can be activated upon voltage/current conditioning. More specifically, transition metal oxides are insulating as-deposited and, thus, need to be conditioned in order to exhibit the bi-stable electrical resistance for utility as memory elements. The conditioning process involves subjecting the transition metal oxide in its insulating dielectric state to an appropriate electrical signal for a sufficient period of time in order to generate a confined conducting region that can be reversibly switched between two or more resistance states. For example, resistance properties of transition metal oxides can be switched, as illustrated in U.S. Pat. No. 6,815,744 to Beck and U.S. Pat. No. 6,204,139 to Liu, cited above and incorporated herein by reference, by applying short electrical pulses to the material. However, there is a large variation in the time required for conditioning transition metal oxides. Due to this large time variation, bulk conditioning of multiple memory elements is difficult because once a single memory element is conditioned current through that conditioned element must be limited in order to prevent the conditioned element from burning-out when subjected to additional current as other memory elements continue to undergo conditioning. Consequently, current practice requires individual conditioning of each memory cell is typically required. This time-consuming process of conditioning each memory cell individually and the large variations in identical programmable resistors used in the memory cells and in devices formed with such memory cells severely hinders manufacturability and is impractical for production-type arrays. Therefore, there is a need in the art for both a semiconductor structure and a method that allow for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells.
  • In view of the foregoing, embodiments of the invention provide both a semiconductor structure and a method that allow for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells.
  • Referring to FIG. 2, embodiments of the invention provide a semiconductor structure 200 that allows for simultaneous conditioning of multiple parallel memory elements 220 in devices with multiple memory cells 201. In this configuration, each memory cell 201 comprises a transistor 210. Each transistor 210 comprises a source region 211 (e.g., an N+ silicon diffusion region) and a drain region 212 (e.g., an N+ silicon diffusion region) formed in a semiconductor substrate 205 (e.g., a P+ silicon substrate). Each transistor 210 also comprises a gate electrode 213 formed on a gate dielectric film 214 (e.g., an oxide film) that is positioned above the substrate 205 between the source/drain regions 211, 212. A memory element 220 contacts the drain region 212 and comprises a variable resistor 221 (and, optionally, a platinum (Pt) layer 224) sandwiched between a first (lower) electrode 222 and a second (upper) electrode 223. The variable resistor 221 comprises a transition metal oxide (e.g., strontium titanium oxide (SrTiO3), strontium barium titanium oxide ((Sr, Ba)TiO3), praseodymium calcium manganese oxide ((Pr,Ca)MnO3), strontium zirconium oxide (SrZrO3), nickel oxide (NiO), titanium oxide (TiO2), tantalum oxide (Ta2O5), or other transition metal oxides. The transition metal oxides can be doped preferentially with chromium, manganese, or vanadium.) The transistor 210 and the variable resistor 221 of the memory element 220 are electrically connected to each other in series by contact between the drain region 212 and the first electrode 222. The source region 211 is connected to metal interconnects 232 that will serve as common lines for the finished memory device. A dielectric material 240 with a planar top surface 241 at which the second electrodes 223 are exposed, isolates the various features.
  • The semiconductor structure 200 further comprises a temporary blanket series resistor 250 at the surface 241 and/or permanent series resistors 260 within the semiconductor substrate 205 (see detailed description below). These series resistors 250, 260 are configured so that they limit current passing through the memory elements 220 during the process of simultaneously conditioning the transition metal oxide 221 and, thus, so that the transition metal oxide will exhibit the desired bi-stable electrical resistance (i.e., conditioning to exhibit the desired resistive properties). Thus, damage (i.e., burn-out) to conditioned transition metal oxide 221 in individual memory elements 220 is avoided while other memory elements 220 are still undergoing the conditioning process (i.e., the temporary series resistor 250 and/or permanent series resistors 260 limit the current passing through the memory elements to avoid damaging the transition metal oxide 221 once it is conditioned).
  • Specifically, the semiconductor structure 200 can comprise a series resistor 250 that is temporarily connected in series to exposed second electrodes 223 of the memory elements 220 (i.e., a blanket resistor is formed on top of the exposed second electrodes of the memory elements and, then, following the transition metal oxide conditioning process (discussed below, the blanket resistor is removed). This blanket resistor can take several different forms (see FIGS. 3-6). For example, referring to FIG. 3, the temporary series resistor can comprise a temporary resistive layer 351-metal layer 352 stack 353 over the memory elements 220 such that a resistive layer 351 of the stack 353 contacts the second electrodes 223. Alternatively, the temporary series resistor can comprise an electrolyte solution (see item 451 of FIG. 4) or plasma (see item 551 of FIG. 5), having selected conductive and resistive properties, that is contained (e.g., in a sealed container (see items 452-453 of FIG. 4 and items 552-553 of FIG. 5) over the memory elements 220 such that the electrolyte solution 451 or plasma 551 contacts the second electrode 223 of each of the memory elements 220. Similarly, referring to FIG. 6, the temporary series resistor can comprise mercury 651 (i.e., a liquid metal at room temperature that exhibits poor conductivity) that is contained (e.g., in a sealed container 652-653) over the memory elements such that the mercury 651 contacts the second electrode 223 of each of the memory elements 220.
  • Referring again to FIG. 2, current applied from a power source 270 to the temporary series resistor 250 (e.g., to the resistive layer 351 via the metal layer 352, which evenly distributes the potential around the resistive layer 351, (see FIG. 3), to the electrolyte solution 451 (see FIG. 4), to the plasma 551 (see FIG. 5), or to the mercury 651 (see FIG. 6)) is evenly and simultaneously distributed through the temporary series resistor 250 to the memory elements 220 located immediately below. Specifically, the current can be applied using suitable known techniques for programming the selected transition metal oxide material, for example, as illustrated in the prior art documents cited above in the “Description of the Related Art” and incorporated herein by reference.
  • Referring to FIG. 7, the size of the temporary series resistor 250 (e.g., an area measurement (i.e., length 757 by width 758) or volume measurement (not shown) that ultimately defines the number of memory elements 220 above which the temporary series resistor 250 is positioned) is predetermined based on the output capacity of the power supply (see item 270 of FIG. 2) used to apply the current and by the probe contact resistance that can be tolerated in order to ensure that the current is applied equally to each of the memory elements 220 below the resistor 250. Thus, a given device with multiple cells may be configured with multiple temporary series resistors 250, each having a predetermined size sufficient to contact the second electrodes of a group of memory elements 220 and to ensure that those memory elements 220 will be simultaneously conditioned.
  • Referring again to FIG. 2, in addition to or instead of the temporary series resistor 250, described above, the semiconductor structure 200 of the invention can also comprise additional resistors 260 that are each permanently connected in series to corresponding first electrodes 222 of the memory elements 220 (i.e., corresponding resistors 260 are electrically connected in series to the first electrodes during the memory cell formation process and these resistors 260 remain incorporated into the memory cells even after the transition metal oxide conditioning process (discussed below). As with the temporary series resistor, these permanent series resistors 260 function to limit current passing through the memory elements 220 during a simultaneous conditioning process in order to avoid damaging the transition metal oxide 221 in each of the memory elements 220 once conditioned. Typically, as discussed above, each memory cell 201 comprises a drain region 212 with a first conductivity type (e.g., an N+ silicon diffusion region) that contacts a corresponding first electrode 222 of a memory element 220. Such memory cells 201 also comprise (i.e., are formed from) a semiconductor substrate 205 with a second conductivity type (e.g., a P+ silicon substrate) below the diffusion region 212. Referring to FIG. 8, permanent series resistors can be created by incorporating a semiconductor well 861 into each of the memory cells 201. Specifically, a semiconductor well 861 with the second conductivity type (e.g., a p-type well) that connects the semiconductor substrate 205 in series with the diffusion region 212 can function as a series resistor, if this semiconductor well 861 has less of a second conductivity type dopant than the semiconductor substrate 205 (i.e., a P-well 861/P+ substrate 205 combination).
  • Additionally, if the semiconductor structure of the invention is formed without a temporary series resistor, as illustrated in FIG. 8, the structure can further comprise a conductor 855 (e.g., a temporary metal plate) over the memory elements 220 such the second electrodes 223 the memory elements 220 are contacted. Then, current applied to this conductor 855 from a power source 270 is distributed evenly and simultaneously to the memory elements 220 located immediately below.
  • Referring to FIG. 9 in combination with FIG. 2, an embodiment of the invention also provides a method of simultaneously conditioning multiple memory elements 220 in devices with multiple memory cells 201. The method comprises first using known techniques to form multiple memory cells 201 for a nonvolatile memory device on a semiconductor substrate 205 (e.g., a P+ silicon substrate) (902). Each memory cell 201 is formed by forming a transistor 210 on the wafer and then, forming a memory element 220 that contacts the drain region 212 of the transistor 210. Specifically, to form multiple memory cells 201, multiple transistors 210 can be formed on the wafer such that each transistor 210 comprises a source region 211 (e.g., an N+ silicon diffusion region), a drain region 212 (e.g., an N+ silicon diffusion region) and a gate (e.g., a gate electrode 213 formed on a gate dielectric film 214 above the substrate 205 between the source/drain regions 211, 212). The memory elements 220 for the memory cells 201 can be formed by forming a first electrode 222 on each drain region 212, by forming a layer of transition metal oxide 221 on the first electrode 222, by optionally forming a layer of platinum 224 on the transition metal oxide 221 and by forming a second electrode 223 on the platinum 224 so that the second electrode is exposed at the top surface 241 of a dielectric 240 (903). The variable resistor 221 can comprises a transition metal oxide (e.g., strontium titanium oxide (SrTiO3), strontium barium titanium oxide ((Sr, Ba)TiO3), praseodymium calcium manganese oxide ((Pr,Ca)MnO3), strontium zirconium oxide (SrZrO3), nickel oxide (NiO), titanium oxide (TiO2), tantalum oxide (Ta2O5), or other transition metal oxides. The transition metal oxides can be doped preferentially with chromium, manganese, or vanadium.)
  • As the memory cells are being formed permanent series resistors 260 can, optionally, be formed within the memory cells (908). Furthermore, in addition to these permanent series 260 resistors or instead of these permanent series resistors 260, a temporary series resistor 250 can be formed on the memory cells (904).
  • Once the temporary 250 and/or permanent series resistors 260 are formed one or within the memory cells, respectively, current can be simultaneously applied to the memory elements 220 so as to condition the transition metal oxide 221 in each of the memory elements 220 (913). The series resistors 250, 260 are configured so that, during this simultaneous conditioning process (913), they limit current passing through the memory elements 220. Thus, damage to conditioned transition metal oxide in individual memory elements is avoided while other memory elements are still undergoing the conditioning process (i.e., the temporary series resistor 250 and/or permanent series resistors 260 limit the current passing through the memory elements to avoid damaging transition metal oxide in any of the memory elements once it is conditioned). Following the conditioning process 913, the temporary series resistor 250 will be removed and the memory device will be completed, for example, by conventional processing techniques (914-915).
  • Specifically, the method can comprise forming a blanket temporary series resistor 250 over the memory elements 220 such that the temporary series resistor 250 contacts the second electrodes 223 of the memory elements 220 (904). The temporary series resistor 250 may be formed using various techniques (905-907; see FIGS. 3-6). For example, the temporary series resistor can be formed by forming a temporary resistive layer 351-metal layer 352 stack 353 over the memory elements 220 such that a resistive layer 351 of the stack 353 contacts the second electrodes 223 (905; see FIG. 3). Alternatively, the temporary series resistor can be formed by selecting either an electrolyte solution (906; see item 451 of FIG. 4) or a plasma (906; see item 551 of FIG. 5) that has selected conductive and resistive properties and, then, containing the electrolyte solution 451 or plasma 551 over the memory elements 220 such that it contacts the second electrodes 223. Similarly, the temporary series resistor can be formed by containing mercury 651 over the memory elements 221 such that the mercury 651 contacts the second electrodes 223 (907; see FIG. 6). The size of the blanket temporary series resistor 250 (e.g., an area measurement that defines the number of memory elements above which the temporary series resistor is positioned) can be predetermined, prior to formation, based on the output capacity of the power supply 270 that is used to apply the current and by the probe contact resistance that can be tolerated in order to ensure that the current is applied equally to each of the memory elements 220 that are located below the resistor 250. Thus, for a given device with multiple cells 201, multiple temporary series resistors 250 can be formed at process 904 and used at process 913 (see FIG. 7). The multiple temporary series resistor 250 can each have a predetermined size sufficient to contact the second electrodes 223 of a group of memory elements so as to ensure that those memory elements will be simultaneously conditioned.
  • After formation of the temporary series resistor (at process 904), current can be simultaneously applied from a power supply 270 to the memory elements 220 (at process 913) by applying current to the temporary series resistor 250 (e.g., to the resistive layer 351 of FIG. 3 via the metal layer 35, which evenly distributes the potential around the entire resistive layer, to the electrolyte solution 451 of FIG. 4, to the plasma 551 of FIG. 5, or to the mercury 651 of FIG. 6). Specifically, the current can be applied using suitable known techniques for programming the selected transition metal oxide, for example, as illustrated in the prior art documents cited above and incorporated herein by reference. The current as applied to the temporary series resistor 250 is evenly and simultaneously distributed through the temporary series resistor to the memory elements 220 located immediately below and contacting the temporary series resistor 250.
  • Those skilled in the art will recognize that by supplying the current to the exposed contacts 223 via the electrolyte solution, plasma or mercury, vice a deposited resistive layer-metal layer stack, memory device manufacturing costs are reduced because less processing is required to remove these types of temporary series resistors from the wafer surface following completion of conditioning (at process 913).
  • In addition to or instead of forming the temporary series resistor 250 on the wafer surface (at process 904), as described above, the method of the invention can also comprise forming permanent series resistors 260 within the wafer substrate (908). Specifically, these series resistors 260 are formed during memory cell formation so that they are electrically connected in series to corresponding first electrodes 222 of the memory elements 220. As with the temporary series resistors, these permanent series resistors function to limit current passing through the memory elements 220 during a simultaneous conditioning process in order to avoid damaging the transition metal oxide 221 in each of the memory elements 220 once they are conditioned. As mentioned above, each memory cell 201 is formed to have a memory element 220 on a drain region 212 above a substrate 205 (902-903). The permanent series resistors 260 can be created by incorporating a semiconductor well 861 into each of the memory cells 201 between this drain region 212 and the substrate 205 (909-912). Specifically, in order to form each memory cell 201 with a series resistor 260, the substrate 205 with a second conductivity type is provided (e.g., a P+ silicon substrate) (909). A semiconductor well 861 with the second conductivity type, but having less of a second conductivity type dopant than the substrate (e.g., a P− silicon well), is then formed in the substrate 205 (910). The diffusion regions 211 and 212, having a first conductivity type (e.g., N+ silicon diffusion regions), are formed in the well 861 (911, see FIG. 8). Thus, the semiconductor well 861 connects the semiconductor substrate 205 with the drain region 212. By forming the semiconductor well 861 with less of a second conductivity type dopant than the semiconductor substrate 205 (during process 910), this well 861 will function as a series resistor.
  • In the event that a temporary series resistor is not formed (at process 904), the method can further comprise forming a conductor (e.g., see temporary metal plate 855 of FIG. 8) over the memory elements 220 such the second electrode 223 of each of the memory elements 220 are contacted. Then, during process 913, current applied to this conductor 855 from a power source 270 can be evenly and simultaneously distributed via the conductor 855 to the memory elements 220 located immediately below.
  • As mentioned above, following the simultaneous conditioning of the transition metal oxide in the multiple memory elements (at process 913) by use of the structure and method, disclosed herein, any temporary series resistors or temporary metal plates are removed from the wafer surface (914) and additional processing will be performed to complete the nonvolatile memory device (e.g., metal interconnects will be formed on the top surface of the dielectric material to serve as bit lines connecting the memory cells to the support circuitry) (915).
  • Therefore, disclosed above are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with individual memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.
  • The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, those skilled in the art will recognize that the embodiments of the invention can be practiced with modification within the spirit and scope of the appended claims.

Claims (20)

1. A semiconductor structure that allows for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells, said semiconductor structure comprising:
multiple parallel memory elements, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes; and,
a series resistor temporarily connected in series to said second electrodes, wherein said series resistor is configured to limit current passing through said memory elements during a simultaneous conditioning process of said transition metal oxide in each of said memory elements.
2. The semiconductor structure of claim 1, wherein a size of said temporary series resistor is predetermined based on the output capacity of the power supply used to apply said current in order to ensure that said current is applied equally to each of said memory elements.
3. The semiconductor structure of claim 1, wherein said temporary series resistor comprises a temporary resistive layer-metal layer stack adjacent to said memory elements such that a resistive layer of said stack contacts said second electrodes.
4. The semiconductor structure of claim 1, wherein said temporary series resistor comprises an electrolyte solution that is contained over said memory elements such that said electrolyte solution contacts said second electrode of each of said memory elements, wherein said electrolyte solution has selected conductive and resistive properties.
5. The semiconductor structure of claim 1, wherein said temporary series resistor comprises mercury that is contained over said memory elements such that said mercury contacts said second electrode of each of said memory elements.
6. The semiconductor structure of claim 1, wherein said temporary series resistor comprises a plasma that is contained over said memory elements such that said plasma contacts said second electrode of each of said memory elements, wherein said plasma has selected conductive and resistive properties.
7. The semiconductor structure of claim 1, further comprising additional series resistors electrically connected to said first electrodes of said memory elements to further limit said current passing through said memory elements.
8. A semiconductor structure that allows for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells, said semiconductor structure comprising:
multiple parallel memory elements, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes; and,
series resistors electrically connected in series to corresponding first electrodes of said memory elements, wherein said series resistors are configured to limit current passing through said memory elements during a simultaneous conditioning process of said transition metal oxide in each of said memory elements.
9. The semiconductor structure of claim 8, wherein each of said memory cells comprises a diffusion region with a first conductivity type that contacts a corresponding first electrode and a semiconductor substrate with a second conductivity type below said diffusion region,
wherein each of said series resistors comprises a semiconductor well with said second conductivity type that connects said semiconductor substrate and said diffusion region, and
wherein said semiconductor well has less of a second conductivity type dopant than said semiconductor substrate and, thereby, functions as a resistor.
10. The semiconductor structure of claim 8, further comprising a temporary series resistor electrically connected to said second electrodes to further limit said current passing through said memory elements.
11. The semiconductor structure of claim 10, wherein a size of said temporary series resistor is predetermined based on the output capacity of the power supply used to apply said current in order to ensure that said current is applied equally to each of said memory elements.
12. A method of simultaneously conditioning multiple memory elements in devices with multiple memory cells, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes, said method comprising:
forming a series resistor over said memory elements such that said series resistor contacts said second electrodes of said memory elements;
simultaneously applying current to said memory elements so as to simultaneously condition said transition metal oxide in each of said memory elements, wherein said series resistor limits said current passing through said memory elements to avoid damaging said transition metal oxide; and
removing said series resistor.
13. The method of claim 12, wherein a size of said series resistor is predetermined based on the output capacity of the power supply used for said applying of said current in order to ensure that said current is applied equally to each of said memory elements.
14. The method of claim 12, wherein said forming of said series resistor comprises forming a resistive layer-metal layer stack over said memory elements such that a resistive layer of said stack contacts said second electrodes, and
wherein said applying of said current comprises supplying said current to said temporary metal layer.
15. The method of claim 12, wherein said forming of said series resistor comprises forming an electrolyte solution, having selected conductive and resistive properties, and containing said electrolyte solution over said memory elements such that said electrolyte solution contacts said second electrodes, and
wherein said applying of said current comprises supplying said current to said electrolyte solution.
16. The method of claim 12, wherein said forming of said series resistor comprises containing mercury over said memory elements such that said mercury contacts said second electrode of each of said memory elements, and
wherein said applying of said current comprises supplying said current to said mercury.
17. The method of claim 12, wherein said forming of said series resistor comprises forming a plasma, having selected conductive and resistive properties, and containing said plasma over said memory elements such that said plasma contacts said second electrodes, and
wherein said applying of said current comprises supplying said current to said plasma.
18. The method of claim 12, further comprising forming additional series resistors within said memory cells such that said additional series resistors contact said first electrodes of said memory elements to further limit said current passing through said memory elements.
19. A method of simultaneously conditioning multiple memory elements in devices with multiple memory cells, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes, said method comprising:
forming series resistors within said memory cells such that said series resistors are electrically connected to said first electrodes of said memory elements; and
simultaneously applying current to said memory elements so as to simultaneously condition said transition metal oxide in each of said memory elements, wherein said series resistors limit said current passing through said memory elements to avoid damaging said transition metal oxide.
20. The method of claim 19, wherein said forming of said series resistors comprises forming each of said memory cells with a semiconductor well connecting a semiconductor substrate and a diffusion region and with a memory element connected to said diffusion region,
wherein said diffusion region is formed with a first conductivity type and said semiconductor well and said semiconductor substrate are formed with a second conductivity type, and
wherein said semiconductor well is formed with less of a second conductivity type dopant than said semiconductor substrate so that for each of said memory elements said semiconductor well functions as a series resistor.
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Cited By (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070117315A1 (en) * 2005-11-22 2007-05-24 Macronix International Co., Ltd. Memory cell device and manufacturing method
US20070128870A1 (en) * 2005-12-02 2007-06-07 Macronix International Co., Ltd. Surface Topology Improvement Method for Plug Surface Areas
US20070298535A1 (en) * 2006-06-27 2007-12-27 Macronix International Co., Ltd. Memory Cell With Memory Material Insulation and Manufacturing Method
US20080246014A1 (en) * 2007-04-03 2008-10-09 Macronix International Co., Ltd. Memory Structure with Reduced-Size Memory Element Between Memory Material Portions
US7595218B2 (en) * 2006-01-09 2009-09-29 Macronix International Co., Ltd. Programmable resistive RAM and manufacturing method
US7646631B2 (en) 2007-12-07 2010-01-12 Macronix International Co., Ltd. Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods
US7688619B2 (en) 2005-11-28 2010-03-30 Macronix International Co., Ltd. Phase change memory cell and manufacturing method
US7701750B2 (en) 2008-05-08 2010-04-20 Macronix International Co., Ltd. Phase change device having two or more substantial amorphous regions in high resistance state
US7719913B2 (en) 2008-09-12 2010-05-18 Macronix International Co., Ltd. Sensing circuit for PCRAM applications
US20100133496A1 (en) * 2008-12-02 2010-06-03 Samsung Electronics Co., Ltd. Resistive random access memory
US7749854B2 (en) 2006-12-06 2010-07-06 Macronix International Co., Ltd. Method for making a self-converged memory material element for memory cell
US7772581B2 (en) 2006-09-11 2010-08-10 Macronix International Co., Ltd. Memory device having wide area phase change element and small electrode contact area
US7777215B2 (en) 2007-07-20 2010-08-17 Macronix International Co., Ltd. Resistive memory structure with buffer layer
US7786460B2 (en) 2005-11-15 2010-08-31 Macronix International Co., Ltd. Phase change memory device and manufacturing method
US7785920B2 (en) 2006-07-12 2010-08-31 Macronix International Co., Ltd. Method for making a pillar-type phase change memory element
US7791057B2 (en) 2008-04-22 2010-09-07 Macronix International Co., Ltd. Memory cell having a buried phase change region and method for fabricating the same
US7825398B2 (en) 2008-04-07 2010-11-02 Macronix International Co., Ltd. Memory cell having improved mechanical stability
US7829876B2 (en) 2005-11-21 2010-11-09 Macronix International Co., Ltd. Vacuum cell thermal isolation for a phase change memory device
US7842536B2 (en) 2005-11-21 2010-11-30 Macronix International Co., Ltd. Vacuum jacket for phase change memory element
US7863655B2 (en) 2006-10-24 2011-01-04 Macronix International Co., Ltd. Phase change memory cells with dual access devices
US7869270B2 (en) 2008-12-29 2011-01-11 Macronix International Co., Ltd. Set algorithm for phase change memory cell
US7867815B2 (en) 2005-11-16 2011-01-11 Macronix International Co., Ltd. Spacer electrode small pin phase change RAM and manufacturing method
US7879645B2 (en) 2008-01-28 2011-02-01 Macronix International Co., Ltd. Fill-in etching free pore device
US7879643B2 (en) 2008-01-18 2011-02-01 Macronix International Co., Ltd. Memory cell with memory element contacting an inverted T-shaped bottom electrode
US7884343B2 (en) 2007-02-14 2011-02-08 Macronix International Co., Ltd. Phase change memory cell with filled sidewall memory element and method for fabricating the same
US7894254B2 (en) 2009-07-15 2011-02-22 Macronix International Co., Ltd. Refresh circuitry for phase change memory
US7897954B2 (en) 2008-10-10 2011-03-01 Macronix International Co., Ltd. Dielectric-sandwiched pillar memory device
US7902538B2 (en) 2005-11-28 2011-03-08 Macronix International Co., Ltd. Phase change memory cell with first and second transition temperature portions
US7903447B2 (en) 2006-12-13 2011-03-08 Macronix International Co., Ltd. Method, apparatus and computer program product for read before programming process on programmable resistive memory cell
US7903457B2 (en) 2008-08-19 2011-03-08 Macronix International Co., Ltd. Multiple phase change materials in an integrated circuit for system on a chip application
US7910906B2 (en) 2006-10-04 2011-03-22 Macronix International Co., Ltd. Memory cell device with circumferentially-extending memory element
US7919766B2 (en) 2007-10-22 2011-04-05 Macronix International Co., Ltd. Method for making self aligning pillar memory cell device
US7923285B2 (en) 2005-12-27 2011-04-12 Macronix International, Co. Ltd. Method for forming self-aligned thermal isolation cell for a variable resistance memory array
US7933139B2 (en) 2009-05-15 2011-04-26 Macronix International Co., Ltd. One-transistor, one-resistor, one-capacitor phase change memory
US7932506B2 (en) 2008-07-22 2011-04-26 Macronix International Co., Ltd. Fully self-aligned pore-type memory cell having diode access device
US7956344B2 (en) 2007-02-27 2011-06-07 Macronix International Co., Ltd. Memory cell with memory element contacting ring-shaped upper end of bottom electrode
US7968876B2 (en) 2009-05-22 2011-06-28 Macronix International Co., Ltd. Phase change memory cell having vertical channel access transistor
US7972895B2 (en) 2007-02-02 2011-07-05 Macronix International Co., Ltd. Memory cell device with coplanar electrode surface and method
US7978509B2 (en) 2007-08-02 2011-07-12 Macronix International Co., Ltd. Phase change memory with dual word lines and source lines and method of operating same
US7993962B2 (en) 2005-11-15 2011-08-09 Macronix International Co., Ltd. I-shaped phase change memory cell
US8030634B2 (en) 2008-03-31 2011-10-04 Macronix International Co., Ltd. Memory array with diode driver and method for fabricating the same
US8030635B2 (en) 2009-01-13 2011-10-04 Macronix International Co., Ltd. Polysilicon plug bipolar transistor for phase change memory
US8036014B2 (en) * 2008-11-06 2011-10-11 Macronix International Co., Ltd. Phase change memory program method without over-reset
US8062833B2 (en) 2005-12-30 2011-11-22 Macronix International Co., Ltd. Chalcogenide layer etching method
US8064248B2 (en) 2009-09-17 2011-11-22 Macronix International Co., Ltd. 2T2R-1T1R mix mode phase change memory array
US8064247B2 (en) 2009-01-14 2011-11-22 Macronix International Co., Ltd. Rewritable memory device based on segregation/re-absorption
US8077505B2 (en) 2008-05-07 2011-12-13 Macronix International Co., Ltd. Bipolar switching of phase change device
US8084842B2 (en) 2008-03-25 2011-12-27 Macronix International Co., Ltd. Thermally stabilized electrode structure
US8084760B2 (en) 2009-04-20 2011-12-27 Macronix International Co., Ltd. Ring-shaped electrode and manufacturing method for same
US8089137B2 (en) 2009-01-07 2012-01-03 Macronix International Co., Ltd. Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method
US8097871B2 (en) 2009-04-30 2012-01-17 Macronix International Co., Ltd. Low operational current phase change memory structures
US8107283B2 (en) 2009-01-12 2012-01-31 Macronix International Co., Ltd. Method for setting PCRAM devices
US8110822B2 (en) 2009-07-15 2012-02-07 Macronix International Co., Ltd. Thermal protect PCRAM structure and methods for making
US8134857B2 (en) 2008-06-27 2012-03-13 Macronix International Co., Ltd. Methods for high speed reading operation of phase change memory and device employing same
US8143612B2 (en) 2007-09-14 2012-03-27 Marconix International Co., Ltd. Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing
US8158963B2 (en) 2006-01-09 2012-04-17 Macronix International Co., Ltd. Programmable resistive RAM and manufacturing method
US8158965B2 (en) 2008-02-05 2012-04-17 Macronix International Co., Ltd. Heating center PCRAM structure and methods for making
US8173987B2 (en) 2009-04-27 2012-05-08 Macronix International Co., Ltd. Integrated circuit 3D phase change memory array and manufacturing method
US8178405B2 (en) 2006-12-28 2012-05-15 Macronix International Co., Ltd. Resistor random access memory cell device
US8178387B2 (en) 2009-10-23 2012-05-15 Macronix International Co., Ltd. Methods for reducing recrystallization time for a phase change material
US8178386B2 (en) 2007-09-14 2012-05-15 Macronix International Co., Ltd. Phase change memory cell array with self-converged bottom electrode and method for manufacturing
US8198619B2 (en) 2009-07-15 2012-06-12 Macronix International Co., Ltd. Phase change memory cell structure
US8238149B2 (en) 2009-06-25 2012-08-07 Macronix International Co., Ltd. Methods and apparatus for reducing defect bits in phase change memory
US8310864B2 (en) 2010-06-15 2012-11-13 Macronix International Co., Ltd. Self-aligned bit line under word line memory array
US8324605B2 (en) 2008-10-02 2012-12-04 Macronix International Co., Ltd. Dielectric mesh isolated phase change structure for phase change memory
US8350316B2 (en) 2009-05-22 2013-01-08 Macronix International Co., Ltd. Phase change memory cells having vertical channel access transistor and memory plane
US8363463B2 (en) 2009-06-25 2013-01-29 Macronix International Co., Ltd. Phase change memory having one or more non-constant doping profiles
US8395935B2 (en) 2010-10-06 2013-03-12 Macronix International Co., Ltd. Cross-point self-aligned reduced cell size phase change memory
US8406033B2 (en) 2009-06-22 2013-03-26 Macronix International Co., Ltd. Memory device and method for sensing and fixing margin cells
US8415651B2 (en) 2008-06-12 2013-04-09 Macronix International Co., Ltd. Phase change memory cell having top and bottom sidewall contacts
US8467238B2 (en) 2010-11-15 2013-06-18 Macronix International Co., Ltd. Dynamic pulse operation for phase change memory
US8497705B2 (en) 2010-11-09 2013-07-30 Macronix International Co., Ltd. Phase change device for interconnection of programmable logic device
US8664689B2 (en) 2008-11-07 2014-03-04 Macronix International Co., Ltd. Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions
US8729521B2 (en) 2010-05-12 2014-05-20 Macronix International Co., Ltd. Self aligned fin-type programmable memory cell
US8809829B2 (en) 2009-06-15 2014-08-19 Macronix International Co., Ltd. Phase change memory having stabilized microstructure and manufacturing method
US8907316B2 (en) 2008-11-07 2014-12-09 Macronix International Co., Ltd. Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions
US8933536B2 (en) 2009-01-22 2015-01-13 Macronix International Co., Ltd. Polysilicon pillar bipolar transistor with self-aligned memory element
US8987700B2 (en) 2011-12-02 2015-03-24 Macronix International Co., Ltd. Thermally confined electrode for programmable resistance memory
US20150214479A1 (en) * 2014-01-24 2015-07-30 Macronix International Co., Ltd. Multiple phase change materials in an integrated circuit for system on a chip application
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
US9672906B2 (en) 2015-06-19 2017-06-06 Macronix International Co., Ltd. Phase change memory with inter-granular switching

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104392746A (en) * 2014-10-20 2015-03-04 中国科学院微电子研究所 Operating method for obtaining multiple transformation modes of resistance transformation memorizer
WO2018004650A1 (en) * 2016-07-01 2018-01-04 Intel Corporation 1t-1r rram cell including group iii-n access transistor

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204139B1 (en) * 1998-08-25 2001-03-20 University Of Houston Method for switching the properties of perovskite materials used in thin film resistors
US20040036109A1 (en) * 2002-06-25 2004-02-26 Sharp Kabushiki Kaisha Memory cell and memory device
US6815744B1 (en) * 1999-02-17 2004-11-09 International Business Machines Corporation Microelectronic device for storing information with switchable ohmic resistance
US20050151277A1 (en) * 2004-01-14 2005-07-14 Sharp Kabushiki Kaisha Nonvolatile semiconductor memory device
US20060002172A1 (en) * 2004-06-30 2006-01-05 Balasubramanian Venkataraman Providing current for phase change memories
US20060187701A1 (en) * 2005-01-28 2006-08-24 Corvin Liaw Integrated semiconductor memory with an arrangement of nonvolatile memory cells, and method
US7256415B2 (en) * 2005-05-31 2007-08-14 International Business Machines Corporation Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells
US7362604B2 (en) * 2005-07-11 2008-04-22 Sandisk 3D Llc Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4192060B2 (en) * 2003-09-12 2008-12-03 シャープ株式会社 Nonvolatile semiconductor memory device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204139B1 (en) * 1998-08-25 2001-03-20 University Of Houston Method for switching the properties of perovskite materials used in thin film resistors
US6815744B1 (en) * 1999-02-17 2004-11-09 International Business Machines Corporation Microelectronic device for storing information with switchable ohmic resistance
US20040036109A1 (en) * 2002-06-25 2004-02-26 Sharp Kabushiki Kaisha Memory cell and memory device
US20050151277A1 (en) * 2004-01-14 2005-07-14 Sharp Kabushiki Kaisha Nonvolatile semiconductor memory device
US20060002172A1 (en) * 2004-06-30 2006-01-05 Balasubramanian Venkataraman Providing current for phase change memories
US20060187701A1 (en) * 2005-01-28 2006-08-24 Corvin Liaw Integrated semiconductor memory with an arrangement of nonvolatile memory cells, and method
US7256415B2 (en) * 2005-05-31 2007-08-14 International Business Machines Corporation Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells
US7362604B2 (en) * 2005-07-11 2008-04-22 Sandisk 3D Llc Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements

Cited By (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7786460B2 (en) 2005-11-15 2010-08-31 Macronix International Co., Ltd. Phase change memory device and manufacturing method
US8008114B2 (en) 2005-11-15 2011-08-30 Macronix International Co., Ltd. Phase change memory device and manufacturing method
US7993962B2 (en) 2005-11-15 2011-08-09 Macronix International Co., Ltd. I-shaped phase change memory cell
US7867815B2 (en) 2005-11-16 2011-01-11 Macronix International Co., Ltd. Spacer electrode small pin phase change RAM and manufacturing method
US8097487B2 (en) 2005-11-21 2012-01-17 Macronix International Co., Ltd. Method for making a phase change memory device with vacuum cell thermal isolation
US8110430B2 (en) 2005-11-21 2012-02-07 Macronix International Co., Ltd. Vacuum jacket for phase change memory element
US7829876B2 (en) 2005-11-21 2010-11-09 Macronix International Co., Ltd. Vacuum cell thermal isolation for a phase change memory device
US7842536B2 (en) 2005-11-21 2010-11-30 Macronix International Co., Ltd. Vacuum jacket for phase change memory element
US20070117315A1 (en) * 2005-11-22 2007-05-24 Macronix International Co., Ltd. Memory cell device and manufacturing method
US7929340B2 (en) 2005-11-28 2011-04-19 Macronix International Co., Ltd. Phase change memory cell and manufacturing method
US7688619B2 (en) 2005-11-28 2010-03-30 Macronix International Co., Ltd. Phase change memory cell and manufacturing method
US7902538B2 (en) 2005-11-28 2011-03-08 Macronix International Co., Ltd. Phase change memory cell with first and second transition temperature portions
US20070128870A1 (en) * 2005-12-02 2007-06-07 Macronix International Co., Ltd. Surface Topology Improvement Method for Plug Surface Areas
US7923285B2 (en) 2005-12-27 2011-04-12 Macronix International, Co. Ltd. Method for forming self-aligned thermal isolation cell for a variable resistance memory array
US8062833B2 (en) 2005-12-30 2011-11-22 Macronix International Co., Ltd. Chalcogenide layer etching method
US8158963B2 (en) 2006-01-09 2012-04-17 Macronix International Co., Ltd. Programmable resistive RAM and manufacturing method
US7595218B2 (en) * 2006-01-09 2009-09-29 Macronix International Co., Ltd. Programmable resistive RAM and manufacturing method
US7696506B2 (en) 2006-06-27 2010-04-13 Macronix International Co., Ltd. Memory cell with memory material insulation and manufacturing method
US20070298535A1 (en) * 2006-06-27 2007-12-27 Macronix International Co., Ltd. Memory Cell With Memory Material Insulation and Manufacturing Method
US7785920B2 (en) 2006-07-12 2010-08-31 Macronix International Co., Ltd. Method for making a pillar-type phase change memory element
US7964437B2 (en) 2006-09-11 2011-06-21 Macronix International Co., Ltd. Memory device having wide area phase change element and small electrode contact area
US7772581B2 (en) 2006-09-11 2010-08-10 Macronix International Co., Ltd. Memory device having wide area phase change element and small electrode contact area
US7910906B2 (en) 2006-10-04 2011-03-22 Macronix International Co., Ltd. Memory cell device with circumferentially-extending memory element
US7863655B2 (en) 2006-10-24 2011-01-04 Macronix International Co., Ltd. Phase change memory cells with dual access devices
US8110456B2 (en) 2006-10-24 2012-02-07 Macronix International Co., Ltd. Method for making a self aligning memory device
US7749854B2 (en) 2006-12-06 2010-07-06 Macronix International Co., Ltd. Method for making a self-converged memory material element for memory cell
US7903447B2 (en) 2006-12-13 2011-03-08 Macronix International Co., Ltd. Method, apparatus and computer program product for read before programming process on programmable resistive memory cell
US8178405B2 (en) 2006-12-28 2012-05-15 Macronix International Co., Ltd. Resistor random access memory cell device
US7972895B2 (en) 2007-02-02 2011-07-05 Macronix International Co., Ltd. Memory cell device with coplanar electrode surface and method
US7884343B2 (en) 2007-02-14 2011-02-08 Macronix International Co., Ltd. Phase change memory cell with filled sidewall memory element and method for fabricating the same
US8263960B2 (en) 2007-02-14 2012-09-11 Macronix International Co., Ltd. Phase change memory cell with filled sidewall memory element and method for fabricating the same
US7956344B2 (en) 2007-02-27 2011-06-07 Macronix International Co., Ltd. Memory cell with memory element contacting ring-shaped upper end of bottom electrode
US20080246014A1 (en) * 2007-04-03 2008-10-09 Macronix International Co., Ltd. Memory Structure with Reduced-Size Memory Element Between Memory Material Portions
US7875493B2 (en) 2007-04-03 2011-01-25 Macronix International Co., Ltd. Memory structure with reduced-size memory element between memory material portions
US7786461B2 (en) 2007-04-03 2010-08-31 Macronix International Co., Ltd. Memory structure with reduced-size memory element between memory material portions
US7943920B2 (en) 2007-07-20 2011-05-17 Macronix International Co., Ltd. Resistive memory structure with buffer layer
US7777215B2 (en) 2007-07-20 2010-08-17 Macronix International Co., Ltd. Resistive memory structure with buffer layer
US7978509B2 (en) 2007-08-02 2011-07-12 Macronix International Co., Ltd. Phase change memory with dual word lines and source lines and method of operating same
US8860111B2 (en) 2007-09-14 2014-10-14 Macronix International Co., Ltd. Phase change memory cell array with self-converged bottom electrode and method for manufacturing
US8178386B2 (en) 2007-09-14 2012-05-15 Macronix International Co., Ltd. Phase change memory cell array with self-converged bottom electrode and method for manufacturing
US8143612B2 (en) 2007-09-14 2012-03-27 Marconix International Co., Ltd. Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing
US7919766B2 (en) 2007-10-22 2011-04-05 Macronix International Co., Ltd. Method for making self aligning pillar memory cell device
US8222071B2 (en) 2007-10-22 2012-07-17 Macronix International Co., Ltd. Method for making self aligning pillar memory cell device
US7646631B2 (en) 2007-12-07 2010-01-12 Macronix International Co., Ltd. Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods
US7893418B2 (en) 2007-12-07 2011-02-22 Macronix International Co., Ltd. Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods
US7879643B2 (en) 2008-01-18 2011-02-01 Macronix International Co., Ltd. Memory cell with memory element contacting an inverted T-shaped bottom electrode
US7879645B2 (en) 2008-01-28 2011-02-01 Macronix International Co., Ltd. Fill-in etching free pore device
US8158965B2 (en) 2008-02-05 2012-04-17 Macronix International Co., Ltd. Heating center PCRAM structure and methods for making
US8084842B2 (en) 2008-03-25 2011-12-27 Macronix International Co., Ltd. Thermally stabilized electrode structure
US8293600B2 (en) 2008-03-25 2012-10-23 Macronix International Co., Ltd. Thermally stabilized electrode structure
US8030634B2 (en) 2008-03-31 2011-10-04 Macronix International Co., Ltd. Memory array with diode driver and method for fabricating the same
US7825398B2 (en) 2008-04-07 2010-11-02 Macronix International Co., Ltd. Memory cell having improved mechanical stability
US7791057B2 (en) 2008-04-22 2010-09-07 Macronix International Co., Ltd. Memory cell having a buried phase change region and method for fabricating the same
US8077505B2 (en) 2008-05-07 2011-12-13 Macronix International Co., Ltd. Bipolar switching of phase change device
US8059449B2 (en) 2008-05-08 2011-11-15 Macronix International Co., Ltd. Phase change device having two or more substantial amorphous regions in high resistance state
US7701750B2 (en) 2008-05-08 2010-04-20 Macronix International Co., Ltd. Phase change device having two or more substantial amorphous regions in high resistance state
US8415651B2 (en) 2008-06-12 2013-04-09 Macronix International Co., Ltd. Phase change memory cell having top and bottom sidewall contacts
US8134857B2 (en) 2008-06-27 2012-03-13 Macronix International Co., Ltd. Methods for high speed reading operation of phase change memory and device employing same
US7932506B2 (en) 2008-07-22 2011-04-26 Macronix International Co., Ltd. Fully self-aligned pore-type memory cell having diode access device
US8315088B2 (en) 2008-08-19 2012-11-20 Macronix International Co., Ltd. Multiple phase change materials in an integrated circuit for system on a chip application
US7903457B2 (en) 2008-08-19 2011-03-08 Macronix International Co., Ltd. Multiple phase change materials in an integrated circuit for system on a chip application
US7719913B2 (en) 2008-09-12 2010-05-18 Macronix International Co., Ltd. Sensing circuit for PCRAM applications
US8324605B2 (en) 2008-10-02 2012-12-04 Macronix International Co., Ltd. Dielectric mesh isolated phase change structure for phase change memory
US7897954B2 (en) 2008-10-10 2011-03-01 Macronix International Co., Ltd. Dielectric-sandwiched pillar memory device
US8036014B2 (en) * 2008-11-06 2011-10-11 Macronix International Co., Ltd. Phase change memory program method without over-reset
US8664689B2 (en) 2008-11-07 2014-03-04 Macronix International Co., Ltd. Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions
US8907316B2 (en) 2008-11-07 2014-12-09 Macronix International Co., Ltd. Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions
US20100133496A1 (en) * 2008-12-02 2010-06-03 Samsung Electronics Co., Ltd. Resistive random access memory
US7869270B2 (en) 2008-12-29 2011-01-11 Macronix International Co., Ltd. Set algorithm for phase change memory cell
US8094488B2 (en) 2008-12-29 2012-01-10 Macronix International Co., Ltd. Set algorithm for phase change memory cell
US8089137B2 (en) 2009-01-07 2012-01-03 Macronix International Co., Ltd. Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method
US8107283B2 (en) 2009-01-12 2012-01-31 Macronix International Co., Ltd. Method for setting PCRAM devices
US8030635B2 (en) 2009-01-13 2011-10-04 Macronix International Co., Ltd. Polysilicon plug bipolar transistor for phase change memory
US8237144B2 (en) 2009-01-13 2012-08-07 Macronix International Co., Ltd. Polysilicon plug bipolar transistor for phase change memory
US8064247B2 (en) 2009-01-14 2011-11-22 Macronix International Co., Ltd. Rewritable memory device based on segregation/re-absorption
US8933536B2 (en) 2009-01-22 2015-01-13 Macronix International Co., Ltd. Polysilicon pillar bipolar transistor with self-aligned memory element
US8084760B2 (en) 2009-04-20 2011-12-27 Macronix International Co., Ltd. Ring-shaped electrode and manufacturing method for same
US8173987B2 (en) 2009-04-27 2012-05-08 Macronix International Co., Ltd. Integrated circuit 3D phase change memory array and manufacturing method
US8097871B2 (en) 2009-04-30 2012-01-17 Macronix International Co., Ltd. Low operational current phase change memory structures
US8916845B2 (en) 2009-04-30 2014-12-23 Macronix International Co., Ltd. Low operational current phase change memory structures
US7933139B2 (en) 2009-05-15 2011-04-26 Macronix International Co., Ltd. One-transistor, one-resistor, one-capacitor phase change memory
US7968876B2 (en) 2009-05-22 2011-06-28 Macronix International Co., Ltd. Phase change memory cell having vertical channel access transistor
US8313979B2 (en) 2009-05-22 2012-11-20 Macronix International Co., Ltd. Phase change memory cell having vertical channel access transistor
US8350316B2 (en) 2009-05-22 2013-01-08 Macronix International Co., Ltd. Phase change memory cells having vertical channel access transistor and memory plane
US8624236B2 (en) 2009-05-22 2014-01-07 Macronix International Co., Ltd. Phase change memory cell having vertical channel access transistor
US8809829B2 (en) 2009-06-15 2014-08-19 Macronix International Co., Ltd. Phase change memory having stabilized microstructure and manufacturing method
US8406033B2 (en) 2009-06-22 2013-03-26 Macronix International Co., Ltd. Memory device and method for sensing and fixing margin cells
US8238149B2 (en) 2009-06-25 2012-08-07 Macronix International Co., Ltd. Methods and apparatus for reducing defect bits in phase change memory
US8363463B2 (en) 2009-06-25 2013-01-29 Macronix International Co., Ltd. Phase change memory having one or more non-constant doping profiles
US8779408B2 (en) 2009-07-15 2014-07-15 Macronix International Co., Ltd. Phase change memory cell structure
US8198619B2 (en) 2009-07-15 2012-06-12 Macronix International Co., Ltd. Phase change memory cell structure
US8228721B2 (en) 2009-07-15 2012-07-24 Macronix International Co., Ltd. Refresh circuitry for phase change memory
US7894254B2 (en) 2009-07-15 2011-02-22 Macronix International Co., Ltd. Refresh circuitry for phase change memory
US8110822B2 (en) 2009-07-15 2012-02-07 Macronix International Co., Ltd. Thermal protect PCRAM structure and methods for making
US8064248B2 (en) 2009-09-17 2011-11-22 Macronix International Co., Ltd. 2T2R-1T1R mix mode phase change memory array
US8178387B2 (en) 2009-10-23 2012-05-15 Macronix International Co., Ltd. Methods for reducing recrystallization time for a phase change material
US8729521B2 (en) 2010-05-12 2014-05-20 Macronix International Co., Ltd. Self aligned fin-type programmable memory cell
US8853047B2 (en) 2010-05-12 2014-10-07 Macronix International Co., Ltd. Self aligned fin-type programmable memory cell
US8310864B2 (en) 2010-06-15 2012-11-13 Macronix International Co., Ltd. Self-aligned bit line under word line memory array
US8395935B2 (en) 2010-10-06 2013-03-12 Macronix International Co., Ltd. Cross-point self-aligned reduced cell size phase change memory
US8497705B2 (en) 2010-11-09 2013-07-30 Macronix International Co., Ltd. Phase change device for interconnection of programmable logic device
US8467238B2 (en) 2010-11-15 2013-06-18 Macronix International Co., Ltd. Dynamic pulse operation for phase change memory
US8987700B2 (en) 2011-12-02 2015-03-24 Macronix International Co., Ltd. Thermally confined electrode for programmable resistance memory
US20150214479A1 (en) * 2014-01-24 2015-07-30 Macronix International Co., Ltd. Multiple phase change materials in an integrated circuit for system on a chip application
US9336879B2 (en) * 2014-01-24 2016-05-10 Macronix International Co., Ltd. Multiple phase change materials in an integrated circuit for system on a chip application
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
US9672906B2 (en) 2015-06-19 2017-06-06 Macronix International Co., Ltd. Phase change memory with inter-granular switching

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