CN101479852A - 无电容器单晶体管浮体动态随机存取存储器单元及其形成方法 - Google Patents

无电容器单晶体管浮体动态随机存取存储器单元及其形成方法 Download PDF

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CN101479852A
CN101479852A CNA2007800239294A CN200780023929A CN101479852A CN 101479852 A CN101479852 A CN 101479852A CN A2007800239294 A CNA2007800239294 A CN A2007800239294A CN 200780023929 A CN200780023929 A CN 200780023929A CN 101479852 A CN101479852 A CN 101479852A
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费尔南多·冈萨雷斯
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Abstract

本发明包括一种无电容器单晶体管DRAM单元，所述单元包括接纳于半导电材料(18)内的一对间隔开的源极/漏极区域(60、62)。电浮体区域(26)设置于所述半导电材料内的源极/漏极区域之间。间隔开的第一栅极(24)与所述源极/漏极区域之间的体区域分开且以电容方式耦合到所述体区域。一对相对的导电互连第二栅极(44、46)与所述第一栅极间隔开且横向接纳于所述第一栅极外部。所述第二栅极与横向位于所述第一栅极外部且在所述对源极/漏极区域之间的体区域间隔开且以电容方式耦合到所述体区域。本发明揭示形成无电容器单晶体管DRAM单元的线路的方法。

Description

无电容器单晶体管浮体动态随机存取存储器单元及其形成方法
技术领域
本发明涉及无电容器单晶体管DRAM单元，涉及包含无电容器单晶体管DRAM单元阵列的集成电路，且涉及形成无电容器单晶体管DRAM单元的线路的方法。
背景技术
半导体存储器(例如，动态随机存取存储器(DRAM))广泛用于计算机系统中以存储数据。DRAM单元通常包括存取场效晶体管(FET)及存储电容器。所述存取FET允许数据电荷在读取及写入操作期间向及从所述存储电容器转移。所述存储电容器上的数据电荷在刷新操作期间周期性地刷新。
也已开发无电容器的单晶体管DRAM单元。一种类型的所述单元使用绝缘体上半导体晶体管的浮体效应，例如如第6,969,662号美国专利中所揭示。所述存储器单元可包含部分耗尽或完全耗尽的绝缘体上硅晶体管(或形成于体衬底材料中的晶体管)，其具有邻近所述体且通过栅极电介质与所述体分离设置的沟道。由于设置于所述晶体管的体区域下方的绝缘或非导电区域，所述体区域电浮动。通过电荷在所述绝缘体上半导体晶体管的体区域内的集中来确定所述存储器单元的状态。
虽然本发明的动机是解决上文所标识的问题，但其绝不受此限制。在不解释性或其它限制性参考本说明书的情况下且根据等效原则，本发明仅受随附权利要求书的字面文字的限制。
发明内容
附图说明
下文参照以下附图说明本发明的优选实施例。
图1是半导体衬底在根据本发明的方面的过程中的概略俯视平面图。
图2是沿图1中的线2-2截取的概略截面图。
图3是图1的衬底在图1所示的步骤之后的处理步骤处的视图。
图4是沿图3中的线4-4截取的概略截面图。
图5是图4的衬底在图4所示的步骤之后的处理步骤处的视图。
图6是图5的衬底在图5所示的步骤之后的处理步骤处的视图。
图7是图6的衬底在图6所示的步骤之后的处理步骤处的视图。
图8是图7的衬底在图7所示的步骤之后的处理步骤处的视图。
图9是图8的衬底的概略透视图。
图10是图8及9的衬底的概略俯视平面图，其中图8沿图10中的线8-8截取。
图11是图8的衬底在图8所示的步骤之后的处理步骤处的视图。
图12是图11的衬底的替代实施例衬底的概略截面图。
具体实施方式
所述论述首先着手论述形成无电容器单晶体管DRAM单元的线路的实例性方法。不管所述制造方法如何，本发明的方面还包括无电容器单晶体管DRAM单元，及包含无电容器单晶体管DRAM单元阵列的集成电路。
参照图1及2，一般使用参考编号10指示衬底(优选地是半导体衬底)。在本文件的上下文中，术语“半导体衬底”或“半导电衬底”经定义以意指包含半导电材料的任何构造，所述半导电材料包括但不限于例如半导电晶片(单独或在于其上包含其它材料的组件中)及半导电材料层(单独或在包含其它材料的组件中)等体半导电材料。术语“衬底”是指任何支撑结构，其包括但不限于上文所说明的半导电衬底。衬底10包含基础衬底12，举例来说体单晶硅。然而，衬底10可包含另一衬底(不管是现有或是尚待开发的衬底)，且举例来说包含绝缘体上半导体衬底。
衬底10经形成以包含间隔开的半导电材料18的岛20的实例性线路14、16。图中显示线路14、16为大致直线线性，但当然也涵盖弯曲、锯齿、成角或其它形状的线路。实例性优选半导电材料18为单晶硅，举例来说由实例性体半导体衬底材料12制作。仅以实例的方式，形成所描绘岛20的实例性方式是通过现有或尚待开发的沟槽及横向在岛20附近形成绝缘材料22的再填充技术。实例性优选材料包括二氧化硅及/或氮化硅中的一者或其组合。举例来说，可通过紧在岛20下方将氧原子离子植入到体衬底材料12中一峰值植入深度且从此形成二氧化硅在岛20下方上升地制作绝缘材料22。另外仅以实例的方式但并非最优选，可沉积绝缘材料22，在其中蚀刻岛开口20，且随后用半导电材料(举例来说，单晶硅及/或多晶硅)填充所述岛开口。再一选择为，当然，可使用一种或一种以上技术，从而将横向相对的沟槽做入半导体衬底12中，后跟岛20下方的横向底切蚀刻，且其中随后用一种或一种以上绝缘材料填充所述底切的体积。无论如何，在一个实例性实施方案中，可认为绝缘材料22被横向接纳于相应岛20附近及下方，且接触所述岛的半导电材料18。为便于说明，所述论述相对于形成无电容器单晶体管DRAM单元的线路(相对于间隔开的半导电材料18的岛20的线路14)的方法而继续。
参照图3及4，形成字线24，其为间隔开的岛20的线路14所共用且在间隔开的岛20的线路14上方延伸。字线24形成在相应间隔开的岛20的浮体区域26上方。字线24(举例来说)通过/借助所描绘的实例性电介质层28与体区域26间隔开且以电容方式耦合到体区域26。所述电介质层可包含任何适合的电介质，其中二氧化硅从优选的硅半导电材料18热生长仅为一个实例。材料28的实例性优选厚度范围是从12埃到100埃。另外仅以实例的方式，材料18的实例性优选深度是从500埃到1,000埃。字线24优选地包含高熔点金属、高熔点金属硅化物及/或经导电掺杂的半导电材料(例如，多晶硅)中的任一者或其组合。在字线24上方接纳绝缘顶盖30，其中氮化硅及/或二氧化硅为实例性材料。出于继续论述的目的，可认为字线24包含实例性图3描绘中的端32。出于继续论述的目的，可认为浮体区域26具有基底34，其中绝缘材料22被接纳抵靠在基底34上。在仅一个实施方案中，绝缘材料22在基底34下方的实例性优选厚度范围是从500埃到3,000埃。
参照图5，在字线/栅极24的侧壁上方形成绝缘材料36。所述绝缘材料可由单种材料或一种或一种以上材料组成，其中(举例来说)所描绘区域36中的每一者包含两个或两个以上不同绝缘材料层。实例性优选材料包括二氧化硅、氮化硅、氧氮化硅、二氧化铪及/或氧化铝。材料36的实例性优选厚度范围是从50埃到150埃。所述材料可通过在字线24的材料的侧壁上方热生长或沉积形成，此作为一个实例。另外仅以实例的方法，所述材料可通过沉积及随后的无掩模各向异性间隔物蚀刻形成。
已在字线24上方并与其间隔开地形成导电层38，举例来说通过绝缘/电介质材料30及36与其间隔开。层38的实例性优选材料包括氮化钛、多晶硅(p型或n型)、铝及硅化钴，其中层38的实例性优选厚度范围是从50埃到500埃。
参照图6，已在导电层38及字线24上方形成遮掩块40。仅以实例的方式，遮掩块40的优选材料包括光致抗蚀剂。出于继续论述的目的，可认为遮掩块40具有至少接近相对于导电层38接纳块40的地方的间隔开的相对横向边缘42。
参照图7，已加热遮掩块40，以在导电层38上方更加远离彼此地有效地横向向外移动相对的横向边缘42。用于进行此步骤的实例性技术包括在150℃下加热经图案化的光致抗蚀剂遮掩块40一到三分钟。在所述实例性优选实施例中，横向向外移动相对的横向边缘42一大致等于材料38在字线24的横向宽度外部的横向厚度的距离，其中先将遮掩块40图案化以与据以图案化字线24及其上的绝缘顶盖材料30的图案的遮掩块大致吻合。
参照图8-10，已使用遮掩块40(未显示)作为掩模蚀刻导电层38以形成一对互连栅极线44、46，其为间隔开的岛20的线路14所共用且沿着并横向邻近字线24的相对侧在间隔开的岛20的线路14上方延伸，其中栅极线44、46对被接纳于相应间隔开的岛20的相应浮体区域26上方。此仅提供一个将导电层38图案化为一对栅极线的实例性优选方法，所述对栅极线为间隔开的岛的线路所共用且沿着并横向邻近所述字线的相对侧在间隔开的岛的线路上方延伸。出于继续论述的目的，可认为栅极线44、46对包含接近字线端32的相应端48、50。在一个实例性实施方案中，层38的图案化致使字线端32不与栅极线端48、50中的任一者纵向共同定位，如所示实例。在一个优选实施方案中，导电层38的图案化致使字线24纵向延伸超出栅极线44、46对的相应端48、50，如所示实例。无论如何，在一个优选实施方案中，所述图案化形成长度比字线24的长度短的栅极线44、46对。
参照图9及10，将第一导电触点52形成到字线24，且将第二导电触点54形成到栅极线44、46对。因此，在最优选的实施例中，不同的第一及第二导电触点与相应的栅极线44、46及字线24相关联，使得可如所属技术领域中的技术人员所认识的那样单独对其进行控制，如下文所说明的实例。在图9及10中仅用虚线圈概略指示触点52及54，因为所述触点可能穿过随后沉积的电介质材料(出于清晰的目的未在图式中显示)形成到实例性所描绘位置。在一个实例性优选实施方案中，将第一导电触点52形成到纵向延伸超出栅极线44、46对的相应端48、50的字线24的某一部分，如所示实例。
参照图11，横向在互连栅极线44、46对外部且在岛20的半导电材料18内形成相应的间隔开的源极/漏极区域60、62对。因此，通常且优选地，在导电层38的图案化之后形成所述源极/漏极区域。无论如何，图11描绘实例性所制作无电容器单晶体管DRAM单元75。
在一个方面中，虽然制作多个所述DRAM单元为优选且为典型，但不管所述制造方法如何且不管是否制作多个所述DRAM单元，本发明均涵盖无电容器单晶体管DRAM单元。所述DRAM单元包含接纳于半导电材料内的一对间隔开的源极/漏极区域。上文所说明的区域60、62及形成于半导电材料18的实例性岛20内仅为实例性构造。在所述半导电材料内的源极/漏极区域之间设置电浮体区域。另外仅以实例的方式，将所述实例性单元描绘为并非完全耗尽式，其中直接在源极/漏极区域60、62下方的半导电材料也包含电浮体区域/材料。
第一栅极与所述源极/漏极区域之间的体区域间隔开且以电容方式耦合到所述体区域。字线24的所述部分被接纳于个别岛20上方仅为一个实例性所述第一栅极。一对相对的导电互连第二栅极与所述第一栅极间隔开且横向接纳于所述第一栅极外部。所述第二栅极与横向位于所述第一栅极外部且在所述对源极/漏极区域之间的体区域间隔开且以电容方式耦合到所述体区域。仅以实例的方式，第二栅极44、46构成一对实例性所述第二栅极。在一个所描绘且优选的实施方案中，第二栅极44、46通过导电材料(即，导电材料区域70)彼此导电互连，所述导电材料在第二栅极44、46对之间的第一栅极24上方上升延伸。第二栅极44、46对可通过另一方式导电互连，举例来说且仅以实例的方式，通过在最初隔离的第二栅极44、46上方形成的单独导电层。在所述实例中，所述导电层可相同于或不同于制成栅极44、46的材料。另外当然，栅极44及46不需要由相同的组合物构成，但优选地由相同化合物构成。
在一个优选实施方案中，无电容器单晶体管DRAM单元包含衬底，所述衬底包含半导电材料岛。在所述岛附近及下方横向接纳绝缘材料且所述绝缘材料接触所述岛的半导电材料。在所述岛半导电材料内接纳一对间隔开的源极/漏极区域。在所述岛半导电材料内的源极/漏极区域之间设置电浮体区域。第一栅极与所述岛的源极/漏极区域之间的岛体区域间隔开且以电容方式耦合到所述岛体区域。一对导电第二栅极与所述第一栅极间隔开且被横向接纳于所述第一栅极外部，其中所述第二栅极与横向位于所述第一栅极外部且在所述对源极/漏极区域之间的体区域间隔开且以电容方式耦合到所述体区域。此可包含于上文所说明方法及结构中的任一者中。
图12描绘替代且对应于图11的实施方案及实施例的实例性额外实施方案及实施例。已在适当地方使用来自首先说明的实施例的相同编号，其中用后缀“a”或用不同的编号指示不同之处。在图12中，优选地在相应岛20附近及下方横向接纳绝缘材料22a且绝缘材料22a接触所述岛的半导电材料18。在绝缘材料22a外部在相应岛20附近及下方横向接纳经导电掺杂的半导电材料80。实例性优选材料80为经导电掺杂p型或n型多晶硅。优选地，绝缘材料22a在岛20下方及在岛20的横向侧壁与经导电掺杂的半导电材料80之间(两者)具有不大于200埃的厚度。材料22a的更优选所述厚度范围是从50埃到150埃。当然，可通过任何现有或尚待开发的方法制作图12的构造。
所属领域的技术人员将了解并开发用于在上文所描绘实例性DRAM单元内且在包含所述DRAM单元阵列的集成电路中写入、读取、刷新及/或保存数据的各种操作电压。仅以实例的方式，以下表格描绘实例性操作电压，其中Vi是第一栅极电压，Vcs(导电间隔物)是所述对第二栅极的电压，Vt是阈值电压，Vs是源极电压，且VD是漏极电压。另外仅以实例的方式，在所述实例中使用图12实施例中导电的包围半导电材料80，优选地将此半导电材料维持在-3V到-10V的某一适合实例性固定电压下不变。使用包围经导电掺杂的半导电材料80的优选非限制性原因是建立并维持晶体管的优选多晶硅的两侧的相同电位，使得电荷通过电介质电容在所述结构的壁处聚集。
其所长                       实例性操作电压
          Vi           Vcs          Vt        VD          Vs
写入      -3V到-10V    -2.5V        高       1.8V/0V     浮动/0V
保存数据  -3V到-10V    0V           高       浮动/浮动   浮动/0V
读取      2.5V         2.5V         0.5V     0.1V/0.1V   0V/0V
重新写入  -3V到-10V    -2.5V        高       1.8V/0V     浮动/0V
保存数据  -3V到-10V    0V           高       浮动/浮动   浮动/0V
仅以实例的方式，在以下专利中揭示用于无电容器单晶体管DRAM单元的操作的实例性技术及构造：第6,969,662号美国专利；发表编号为2005/0017240及2005/0063224的美国专利申请案；郭(Kuo)等人发表于IEDM，IEEE 2002第843-846页的“用于高密度应用的无电容器双栅极DRAM栅极单元设计(A CapacitorlessDouble-Gate DRAM Gate Cell Design For High Density Applications)”；及吉田(Yoshida)等人发表于IEEE电子装置学报第53卷第4号2006年4月第692-697页的“将栅极诱发漏极泄漏(GIDL)电流用于低功率及高速度嵌入式存储器的无电容器1T-DRAM技术(A Capacitorless 1 T-DRAM Technology Using Gate-InducedDrain-Leakage(GIDL)Current For Low-Power And High-Speed Embedded Memory)”。第5,714,786、6,005,273、6,090,693及7,005,710号美国专利的揭示内容以引用的方式并入本文中。

Claims (38)

1、一种无电容器单晶体管DRAM单元，其包含：
一对间隔开的源极/漏极区域，其接纳于半导电材料内；
电浮体区域，其设置于所述半导电材料内的所述源极/漏极区域之间；
第一栅极，其与所述源极/漏极区域之间的所述体区域间隔开且以电容方式耦合到所述体区域；及
一对相对的导电互连第二栅极，其与所述第一栅极间隔开且横向接纳于所述第一栅极外部，所述第二栅极与横向位于所述第一栅极外部且在所述对源极/漏极区域之间的所述体区域间隔开且以电容方式耦合到所述体区域。
2、如权利要求1所述的DRAM单元，其中所述对第二栅极由在所述对第二栅极之间的所述第一栅极上方上升延伸的导电材料导电互连。
3、如权利要求1所述的DRAM单元，其中所述第一栅极由至少两种绝缘材料与所述第二栅极分离。
4、如权利要求1所述的DRAM单元，其中所述浮体区域具有基底，绝缘层被接纳抵靠所述基底，所述绝缘层具有从500埃到3,000埃的厚度。
5、如权利要求1所述的DRAM单元，其中：
所述浮体区域具有基底，绝缘层被接纳抵靠所述基底；且
经导电掺杂的半导电材料接纳抵靠所述基底下方的所述绝缘层。
6、如权利要求5所述的DRAM单元，其中所述绝缘层在所述基底与所述经导电掺杂的半导电材料之间具有不大于200埃的厚度。
7、一种无电容器单晶体管DRAM单元，其包含：
衬底，其包含半导电材料岛；
绝缘材料，其横向接纳于所述岛附近及下方并接触所述岛的半导电材料；
一对间隔开的源极/漏极区域，其接纳于所述岛半导电材料内；
电浮体区域，其设置于所述岛半导电材料内的所述源极/漏极区域之间；
第一栅极，其与所述岛源极/漏极区域之间的所述岛体区域间隔开且以电容方式耦合到所述岛体区域；及
一对导电第二栅极，其与所述第一栅极间隔开且横向接纳于所述第一栅极外部，所述第二栅极与横向位于所述第一栅极外部且在所述对源极/漏极区域之间的所述体区域间隔开且以电容方式耦合到所述体区域。
8、如权利要求7所述的DRAM单元，其包含在所述绝缘材料外部横向接纳于所述岛附近及下方的经导电掺杂的半导电材料。
9、如权利要求8所述的DRAM单元，其中所述绝缘材料在所述岛下方具有不大于200埃的厚度。
10、如权利要求8所述的DRAM单元，其中所述绝缘材料在所述岛的横向侧壁与所述经导电掺杂的半导电材料之间具有不大于200埃的厚度。
11、如权利要求8所述的DRAM单元，其中所述绝缘材料在所述岛下方及在所述岛的横向侧壁与所述经导电掺杂的半导电材料之间具有不大于200埃的厚度。
12、如权利要求8所述的DRAM单元，其中所述绝缘材料在所述岛下方具有从50埃到150埃的厚度。
13、如权利要求8所述的DRAM单元，其中所述绝缘材料在所述岛的横向侧壁与所述经导电掺杂的半导电材料之间具有从50埃到150埃的厚度。
14、一种包含无电容器单晶体管DRAM单元阵列的集成电路，其包含：
间隔开的半导电材料岛的线路，其接纳于衬底内；及
个别无电容器单晶体管DRAM单元，其相对于所述间隔开的岛中的个别岛被接纳，所述个别单元包含：
一对源极/漏极区域，其接纳于所述相应岛的所述半导电材料内；
电浮体区域，其设置于所述相应岛的所述半导电材料内的所述源极/漏极区域之间；
第一栅极，其由字线组成，所述字线为所述相应对源极/漏极区域之间的间隔开的岛的所述线路所共用且在所述间隔开的岛的所述线路上方延伸，所述字线与所述相应对源极/漏极区域之间的所述相应岛的所述相应体区域间隔开且以电容方式耦合到所述相应体区域；及
一对相对的导电互连第二栅极，其与所述第一栅极间隔开且横向接纳于所述第一栅极外部，所述第二栅极与横向位于所述相应第一栅极外部且在所述相应岛的所述相应对源极/漏极区域之间的所述相应体区域间隔开且以电容方式耦合到所述相应体区域，所述对相对的互连第二栅极包含为间隔开的岛的所述线路所共用且沿所述字线上升地并横向地接纳于所述字线上方的导电线。
15、如权利要求14所述的集成电路，其包含连接到所述字线的第一导电触点及连接到所述导电线的不同的第二导电触点。
16、如权利要求14所述的集成电路，其中所述字线在长度上比所述导电线长。
17、如权利要求14所述的集成电路，其中所述导电线具有一端且所述字线具有接近所述导电线端的一端，所述字线端与所述导电线端不纵向共同定位。
18、如权利要求17所述的集成电路，其中所述字线在长度上比所述导电线长。
19、如权利要求17所述的集成电路，其中所述字线端纵向接纳于所述导电线端外部。
20、如权利要求19所述的集成电路，其中所述字线在长度上比所述导电线长。
21、如权利要求14所述的集成电路，其包含横向接纳于所述相应岛附近及下方且接触所述相应岛的半导电材料的绝缘材料；及
在所述绝缘材料外部横向接纳于所述岛附近及下方的经导电掺杂的半导电材料。
22、如权利要求21所述的集成电路，其中所述绝缘材料在所述相应岛下方及在所述相应岛的横向侧壁与所述经导电掺杂的半导电材料之间具有不大于200埃的厚度。
23、一种形成无电容器单晶体管DRAM单元的线路的方法，其包含：
相对于衬底形成间隔开的半导电材料岛的线路；
形成为间隔开的岛的所述线路所共用且在所述间隔开的岛的所述线路上方延伸的字线，所述字线形成在所述相应间隔开的岛的电浮体区域上方；
在所述字线上方且与所述字线间隔开地形成导电层；
将所述导电层图案化为一对栅极线，所述对栅极线为间隔开的岛的所述线路所共用且沿着并横向邻近所述字线的相对侧在所述间隔开的岛的所述线路上方延伸，所述对栅极线接纳于所述相应间隔开的岛的相应浮体区域上方，所述图案化将所述对栅极线形成为在长度上比所述字线的长度短；及
在所述相应岛的所述半导电材料内形成相应对间隔开的源极/漏极区域，所述对间隔开的源极/漏极区域横向接纳于所述对栅极线外部。
24、如权利要求23所述的方法，其中在所述图案化之后形成所述源极/漏极区域。
25、如权利要求23所述的方法，其包含将第一导电触点形成到所述字线及将第二导电触点形成到所述对栅极线。
26、如权利要求23所述的方法，其中所述字线经形成以具有一端且所述图案化形成所述对栅极线的接近所述字线端的相应端，所述图案化致使所述字线端不与所述栅极线端中的任一者纵向共同定位。
27、如权利要求23所述的方法，其中所述图案化包含：
在所述导电层及所述字线上方形成遮掩块，所述遮掩块具有间隔开的相对横向边缘；
在形成所述遮掩块之后，加热所述遮掩块以在所述导电层上方有效地横向向外移动所述相对横向边缘更加远离彼此；及
在所述加热之后，使用所述遮掩块作为掩模来蚀刻所述导电层以形成所述对栅极线。
28、如权利要求27所述的方法，其中所述字线经形成以具有一端且所述图案化形成所述对栅极线的接近所述字线端的相应端，所述图案化致使所述字线端不与所述栅极线端中的任一者纵向共同定位。
29、如权利要求23所述的方法，其包含：
提供横向在所述相应岛附近及下方并接触所述相应岛的半导电材料的绝缘材料；及
提供在所述绝缘材料外部横向在所述岛附近及下方的经导电掺杂的半导电材料。
30、一种形成无电容器单晶体管DRAM单元的线路的方法，其包含：
相对于衬底形成间隔开的半导电材料岛的线路；
形成为间隔开的岛的所述线路所共用且在所述间隔开的岛的所述线路上方延伸的字线，所述字线形成在所述相应间隔开的岛的电浮体区域上方且包含一端；
在所述字线上方且与所述字线间隔开地形成导电层；
将所述导电层图案化为一对栅极线，其为间隔开的岛的所述线路所共用且沿着并横向邻近所述字线的相对侧在所述间隔开的岛的所述线路上方延伸，所述对栅极线接纳于所述相应间隔开的岛的相应浮体区域上方，所述图案化形成所述对栅极线的接近所述字线端的相应端，所述图案化致使所述字线纵向延伸超出所述对栅极线的所述相应端；及
在所述相应岛的所述半导电材料内形成相应对间隔开的源极/漏极区域，所述对间隔开的源极/漏极区域横向接纳于所述对栅极线外部。
31、如权利要求30所述的方法，其中所述图案化包含：
在所述导电层及所述字线上方形成遮掩块，所述遮掩块具有间隔开的相对横向边缘；
在形成所述遮掩块之后，加热所述遮掩块以在所述导电层上方有效地横向向外移动所述相对横向边缘更加远离彼此；及
在所述加热之后，使用所述遮掩块作为掩模来蚀刻所述导电层以形成所述对栅极线。
32、如权利要求30所述的方法，其包含将第一导电触点形成到所述字线及将第二导电触点形成到所述对栅极线。
33、如权利要求32所述的方法，其包含将所述第一导电触点形成到所述字线的纵向延伸超出所述对栅极线的所述相应端的某一部分。
34、如权利要求30所述的方法，其包含：
提供横向在所述相应岛附近及下方并接触所述相应岛的半导电材料的绝缘材料；及
提供在所述绝缘材料外部横向在所述岛附近及下方的经导电掺杂的半导电材料。
35、一种形成无电容器单晶体管DRAM单元的线路的方法，其包含：
相对于衬底形成间隔开的半导电材料岛的线路；
形成为间隔开的岛的所述线路所共用且在所述间隔开的岛的所述线路上方延伸的字线，所述字线形成在所述相应间隔开的岛的电浮体区域上方；
在所述字线上方且与所述字线间隔开地形成导电层；
在所述导电层及所述字线上方形成遮掩块，所述遮掩块具有间隔开的相对横向边缘；
在形成所述遮掩块之后，加热所述遮掩块以在所述导电层上方有效地横向向外移动所述相对横向边缘更加远离彼此；
在所述加热之后，使用所述遮掩块作为掩模蚀刻所述导电层以形成一对互连栅极线，所述对互连栅极线为间隔开的岛的所述线路所共用且沿着并横向邻近所述字线的相对侧在间隔开的岛的所述线路上方延伸，所述对栅极线接纳于所述相应间隔开的岛的相应浮体区域上方；及
在所述相应岛的所述半导电材料内形成相应对间隔开的源极/漏极区域，所述对间隔开的源极/漏极区域横向接纳于所述互连对栅极线外部。
36、如权利要求35所述的方法，其包含形成所述遮掩块以包含光致抗蚀剂。
37、如权利要求35所述的方法，其中在所述图案化之后形成所述源极/漏极区域。
38、如权利要求35所述的方法，其包含将第一导电触点形成到所述字线及将第二导电触点形成到所述对栅极线。
39、如权利要求38所述的方法，其包含将所述第一导电触点形成到所述字线的纵向延伸超出所述对栅极线的所述相应端的某一部分。
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US8551823B2 (en) 2013-10-08
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EP2772942A2 (en) 2014-09-03
KR20090023496A (ko) 2009-03-04
JP5181304B2 (ja) 2013-04-10
US20090239343A1 (en) 2009-09-24
KR101149666B1 (ko) 2012-05-31
CN101479852B (zh) 2012-06-13
US9129847B2 (en) 2015-09-08
EP2041796A2 (en) 2009-04-01

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