JP2009544166A - キャパシタレス1トランジスタdramセル、キャパシタレス1トランジスタdramセルのアレイを含む集積回路、ならびに、キャパシタレス1トランジスタdramセルのラインを形成する方法 - Google Patents
キャパシタレス1トランジスタdramセル、キャパシタレス1トランジスタdramセルのアレイを含む集積回路、ならびに、キャパシタレス1トランジスタdramセルのラインを形成する方法 Download PDFInfo
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Abstract
Description
しいシリコン半導性材料18から熱により成長する二酸化シリコンであってもよい。一種もしくは数種の材料28の例示的な好ましい厚さの範囲は、12オングストロームから100オングストロームである。さらに例示の目的のためだけであるが、材料18の例示的な好ましい深さは、500オングストロームから1000オングストロームである。ワード線24は、耐熱性金属、耐熱性金属ケイ化物、および/または導電性にドープされた多結晶シリコンなどの材料のうち任意の一つ、もしくはそれらの組み合わせを含むことが好ましい。例示的な材料である窒化シリコンおよび/または二酸化シリコンなどの絶縁キャップ30がワード線24を覆って収容される。説明を続けるために、ワード線24は例示図3の図面にある端部32を含むとみなされうる。説明を続けるために、浮遊ボディ領域26は、そこに対して収容される絶縁材料22である底面34を持つとみなされうる。底面34の下の絶縁材料22の例示的な好ましい厚さの範囲は、一つの実施例においてだが、500オングストロームから3000オングストロームである。
ランドのラインに共通しその上に広がる、一組のゲート線にパターンする好ましい方法が得られるが、これは一例である。説明を続けるために、一組のゲート線44、46は、ワード線端部32に近位の各端部48、50を含むとしてみなされうる。一つの例示的な手段においては、層38のパターニングは、例えば示されるように、ワード線端部32は、ゲート線端部48、50のいずれかと縦方向(長手方向)に同位置に配置されないという結果になる。一つの好ましい手段においては、導電層38のパターニングは、例えば示されるように、ワード線24が一組のゲート線44、46の各端部48、50を長手方向に越えて延びるという結果になる。とにかく、一つの好ましい手段においては、パターニングは、一組のゲート線44、46をワード線24の長さより短くなるように形成する。
い。
0017240、2005/0063224、および、Kuo et ai., “A Capacitorless Double-Gate DRAM Cell Design For High Density Applications”, IDEM, IEEE 2002, pp. 843-846、Yoshida
et al., “A Capacitorless 1 T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current For Low-Power And High-Speed Embedded Memory”, IEEE Transaction on Electron Devices, Vol.53, No.4, April 2006, pp. 692-697に 開示される。U.S.Patent No. 5,714,786、6,005,273、6,090,693、および、7,005,710の開示は、参照として本明細書に組み込まれる。
Claims (39)
- 半導性材料内に収容される、間隔のあいたソース/ドレイン領域の組と、
前記半導性材料内の前記ソース/ドレイン領域の間に配置される、電気的浮遊ボディ領域と、
前記ソース/ドレイン領域の間の前記ボディ領域から間隔をあけて配置され、且つ、容量的に結合する、第一のゲートと、
前記第一のゲートから間隔をあけて配置され、且つ、前記第一のゲートの外側に横方向に収容される、相対して導電的に相互接続する第二のゲートの組であって、
前記第二のゲートは、前記第一のゲートの横方向外側で、前記ソース/ドレイン領域の組の間にある前記ボディ領域から間隔があけられ、且つ、容量的に結合されている、第二のゲートと、
を含む、キャパシタレス1トランジスタDRAMセル。 - 前記第二のゲートの組は、前記第二のゲートの組の間の前記第一のゲート上に高さ方向に広がる、導電性材料によって導電的に相互接続される、
請求項1のDRAMセル。 - 前記第一のゲートは、少なくとも二つの絶縁材料によって、前記第二のゲートから分離される、
請求項1のDRAMセル。 - 前記浮遊ボディ領域が、底面と、前記底面に接して収容される絶縁層を有し、前記絶縁層は500オングストロームから3,000オングストロームの厚さを持つことを特徴とする、
請求項1のDRAMセル。 - 前記浮遊ボディ領域が、底面と、前記底面に接して収容される絶縁層を有し、
導電的にドープされた半導性材料が、前記底面の下の前記絶縁層に接して収容される、請求項1のDRAMセル。 - 前記絶縁層は、前記底面と前記導電的にドープされた半導性材料の中間に、200オングストローム以下の厚さを持つ、
請求項5のDRAMセル。 - 半導性材料のアイランドを含む基板と、
前記アイランドの横方向の周囲および下に収容され、前記アイランドの半導性材料に接続している、絶縁材料と、
前記アイランド半導性材料内に収容される、間隔のあいたソース/ドレイン領域の組と、
前記アイランド半導性材料内の前記ソース/ドレイン領域の間に配置される、電気的浮遊ボディ領域と、
前記アイランドソース/ドレイン領域の間の前記アイランドボディ領域から間隔をあけて離され、且つ、容量的に結合する、第一のゲートと、
前記第一のゲートから間隔をあけて離され、且つ、横方向外側に収容される、第二のゲートの組であって、前記第二のゲートは、前記第一のゲートの横方向外側で、前記ソース/ドレイン領域の組の間にある前記ボディ領域から間隔があけられ、且つ、容量的に結合されている、第二のゲートと、
を含む、キャパシタレス1トランジスタDRAMセル。 - 前記絶縁材料の外側のアイランドの、横方向の周囲および下に収容される導電的にドー
プされた半導性材料を含む、
請求項7のDRAMセル。 - 前記絶縁材料は、前記アイランドの下に、200オングストローム以下の厚さを持つ、
請求項8のDRAMセル。 - 前記絶縁材料は、前記アイランドの横方向の側壁と、前記導電的にドープされた半導性材料の中間に、200オングストローム以下の厚さを持つ、
請求項8のDRAMセル。 - 前記絶縁材料は、前記アイランドの下と、前記アイランドの横方向の側壁と、前記導電的にドープされた半導性材料の中間に、200オングストローム以下の厚さを持つ、
請求項8のDRAMセル。 - 前記絶縁材料は、前記アイランドの下に、50オングストロームから150オングストロームの厚さを持つ、
請求項8のDRAMセル。 - 前記絶縁材料は、前記アイランドの横方向の側壁と、前記導電的にドープされた半導性材料の中間に、50オングストロームから150オングストロームの厚さを持つ、
請求項8のDRAMセル。 - キャパシタレス1トランジスタDRAMセルのアレイを含む集積回路であって、
基板内に収容される半導性材料の間隔のあいたアイランドのラインと、
前記間隔のあいたアイランドの個々に関連して収容される、独立したキャパシタレス1トランジスタDRAMセルと、
を含み、前記独立したセルは、
前記アイランドのそれぞれの半導性材料内に収容されるソース/ドレイン領域の組と、
前記アイランドのそれぞれの半導性材料内の前記ソース/ドレイン領域の間に配置される電気的浮遊ボディ領域と、
前記ソース/ドレイン領域の組のそれぞれの間の間隔のあいたアイランドの前記ラインに共通し、その上に延びるワード線からなる第一のゲートであって、前記ワード線は、前記ソース/ドレイン領域の組のそれぞれの間の前記アイランドのそれぞれの前記ボディ領域のそれぞれから間隔があけられ、容量的に結合される、第一のゲートと、
前記第一のゲートから間隔があけられ、前記第一のゲートの横方向外側に収容される、相対して導電的に相互接続する第二のゲートの組であって、前記第二のゲートは、前記第一のゲートのそれぞれの横方向外側、および、前記アイランドのそれぞれの前記ソース/ドレイン領域の組のそれぞれの間の前記ボディ領域のそれぞれから間隔があけられ、且つ容量的に結合され、前記相対して導電的に相互接続する第二のゲートの組は、前記間隔のあいたアイランドのラインに共通し、前記ワード線の高さ方向および横方向を覆って、且つ前記ワード線に沿って収容される導電線を含む、第二のゲートと、
を含む、
集積回路。 - 前記ワード線に接続する第一の導電性コンタクトと、前記導電線に接続する異なる第二の導電性コンタクトを含む、
請求項14の集積回路。 - 前記ワード線は、前記導電線より長いことを特徴とする、
請求項14の集積回路。 - 前記導電線は端部を有し、前記ワード線は前記導電線の端部の近位にある端部を持ち、前記ワード線端部と前記導電線端部は、長手方向に同位置に配置されないことを特徴とする、
請求項14の集積回路。 - 前記ワード線は、前記導電線より長いことを特徴とする、
請求項17の集積回路。 - 前記ワード線端部は、前記導電線端部の長手方向外側に収容される、
請求項17の集積回路。 - 前記ワード線は、前記導電線より長いことを特徴とする、
請求項19の集積回路。 - 前記アイランドのそれぞれの横方向の周囲および下に収容され、前記アイランドのそれぞれの半導性材料と結合する絶縁材料と、
前記絶縁材料の外側のアイランドの横方向の周囲および下に収容される、導電的にドープされた半導性材料と、
を含む、請求項14の集積回路。 - 前記絶縁材料は、前記アイランドのそれぞれの下および、前記アイランドのそれぞれの横方向の側壁と前記導電的にドープされた半導性材料の中間に、200オングストローム以下の厚さを持つ、
請求項21の集積回路。 - 基板に関連して間隔のあいたアイランドのラインを形成するステップと、
前記間隔のあいたアイランドの前記ラインに共通し、その上に延びるワード線を形成するステップであって、前記ワード線は前記間隔のあいたアイランドのそれぞれの電気的浮遊ボディ領域上に形成される、ステップと、
前記ワード線の上に、前記ワード線から間隔をあけて導電層を形成するステップと、
前記ワード線の相対する側面に沿い、横方向に隣接する前記間隔のあいたアイランドの前記ラインに共通し、その上に延びるゲート線の組内に、導電層をパターンするステップであって、前記ゲート線の組は前記間隔のあいたアイランドのそれぞれの浮遊ボディ領域のそれぞれの上に収容され、前記パターンするステップは前記ゲート線の組を前記ワード線より短く形成する、ステップと、
前記アイランドのそれぞれの前記半導性材料内に間隔のあいたソース/ドレイン領域の組をそれぞれ形成するステップであって、前記間隔のあいたソース/ドレイン領域の組は前記ゲート線の組の横方向外側に収容される、ステップと、
を含む、キャパシタレス1トランジスタDRAMセルを形成する方法。 - 前記ソース/ドレイン領域は、前記パターンするステップの後に形成される、請求項23の方法。
- 第一の導電性コンタクトを前記ワード線に形成し、第二の導電性コンタクトを前記ゲート線の組に形成するステップを含む、請求項23の方法。
- 前記ワード線は端部を持つように形成され、前記パターンするステップは、前記ワード線端部の近位にある前記ゲート線の組のそれぞれの端部を形成し、前記パターンするステ
ップは前記ワード線端部が前記ゲート線端部のいずれとも長手方向に同位置に配置されない結果となる、ことを特徴とする、
請求項23の方法。 - 前記パターンするステップは、
前記導電層と前記ワード線を覆ってマスキングブロックを形成するステップであって、前記マスキングブロックは間隔のあいた、相対する横方向の端部を有する、ステップと、
前記マスキングブロックを形成するステップの後、前記導電層の上で互いにさらに間隔のあいた横方向の外側に、前記相対する横方向の端部を動かすのに効果的に、マスキングブロックを熱するステップと、
前記熱するステップの後、前記ゲート線の組を形成するためのマスクとして前記マスキングブロックを用いて、前記導電層をエッチングするステップと、
を含む、請求項23の方法。 - 前記ワード線は端部を持つように形成され、前記パターンするステップは、前記ワード線端部の近位にある前記ゲート線の組のそれぞれの端部を形成し、前記パターンするステップは前記ワード線端部が前記ゲート線端部のいずれとも長手方向に同位置に配置されない結果となる、ことを特徴とする、
請求項27の方法。 - 絶縁材料を、前記アイランドのそれぞれと、それに接続している前記アイランドの半導性材料に対して横方向の周囲および下に提供するステップと、
導電的にドープされた半導性材料を、前記絶縁材料の外側の前記アイランドに対して横方向の周囲および下に提供するステップと、
を含む、請求項23の方法。 - 基板に関連して半導性材料の間隔のあいたアイランドのラインを形成するステップと、
前記間隔のあいたアイランドのラインに共通し、その上に延びるワード線を形成するステップであって、前記ワード線は、前記間隔のあいたアイランドのそれぞれの電気的浮遊ボディ領域上に形成され、前記ワード線は端部を含む、ステップと、
前記ワード線の上に、前記ワード線から間隔をあけて導電層を形成するステップと、
前記ワード線の相対する側面に沿い、横方向に隣接する前記間隔のあいたアイランドの前記ラインに共通し、その上に延びるゲート線の組内に、導電層をパターンするステップであって、前記ゲート線の組は前記間隔のあいたアイランドのそれぞれの浮遊ボディ領域のそれぞれの上に収容され、前記パターンするステップは、前記ワード線端部の近位の前記ゲート線の組のそれぞれの端部を形成し、前記パターンするステップは、前記ゲート線の組の前記それぞれの端部を長手方向に越えて延びるワード線になることを特徴とする、ステップと、
前記アイランドのそれぞれの前記半導性材料内に間隔のあいたソース/ドレイン領域の組をそれぞれ形成するステップであって、前記間隔のあいたソース/ドレイン領域の組は前記ゲート線の組の横方向外側に収容される、ステップと、
を含む、キャパシタレス1トランジスタDRAMセルを形成する方法。 - 前記パターンするステップが、
前記導電層と前記ワード線の上にマスキングブロックを形成するステップであって、前記マスキングブロックは、間隔のあいた、相対する横方向の端部を有するステップと、
前記マスキングブロックを形成するステップの後で、相対する横方向の端部を、前記導電層の上に互いに横方向外側に離して動かすように、効果的に前記マスキングブロックを熱するステップと、
前記熱するステップの後で、前記ゲート線の組を形成するためのマスクとして前記マスキングブロックを用いて導電層をエッチングするステップと、
を含む、請求項30の方法。 - 第一の導電性コンタクトを前記ワード線に形成し、第二の導電性コンタクトを前記ゲート線の組に形成するステップ
を含む、請求項30の方法。 - 前記第一の導電性コンタクトを、前記ゲート線の組の前記それぞれの端部を長手方向に越えて延びる前記ワード線のいくつかの部分に形成するステップ
を含む、請求項32の方法。 - 絶縁材料を、前記アイランドのそれぞれと、前記アイランドのそれぞれの接触する半導性材料に対して横方向の周囲および下に提供するステップと、
導電的にドープされた半導性材料を、前記絶縁材料の外側の前記アイランドに対して横方向および下に提供するステップと、
を含む、請求項30の方法。 - 基板に関連して半導性材料の間隔のあいたアイランドのラインを形成するステップと、
前記間隔のあいたアイランドのラインに共通し、その上に延びるワード線を形成するステップであって、前記ワード線は前記間隔のあいたアイランドのそれぞれの電気的浮遊領域上に形成されるステップと、
前記ワード線の上に、前記ワード線から間隔をあけて導電層を形成するステップと、
マスキングブロックを前記導電層と前記ワード線上に形成するステップであって、前記マスキングブロックは間隔のあいた、相対する横方向の端部を有するステップと、
前記マスキングブロックを形成するステップの後で、相対する横方向の端部を、前記導電層を覆って互いに横方向外側に離して動かすように、効果的に前記マスキングブロックを熱するステップと、
前記熱するステップの後で、前記ワード線の相対する側面に沿い、横方向に隣接する前記間隔のあいたアイランドのラインに共通し、その上に延びる相互接続するゲート線の組を形成するためのマスクとして前記マスキングブロックを用いて導電層をエッチングするステップであって、前記ゲート線の組は前記間隔のあいたアイランドのそれぞれの浮遊ボディ領域のそれぞれの上に収容されるステップと、
前記アイランドのそれぞれの前記半導性材料内に間隔のあいたソース/ドレイン領域の組をそれぞれ形成するステップであって、前記間隔のあいたソース/ドレイン領域の組は前記相互接続するゲート線の組の横方向外側に収容される、
キャパシタレス1トランジスタDRAMセルのラインを形成する方法。 - フォトレジストを含むように前記マスキングブロックを形成するステップを含む、
請求項35の方法。 - 前記ソース/ドレイン領域は前記パターニングの後で形成される、
請求項35の方法。 - 第一の導電性コンタクトを前記ワード線に形成し、第二の導電性コンタクトを前記ゲート線の組に形成するステップを含む、
請求項35の方法。 - 前記第一の導電性コンタクトを、前記ゲート線の組の前記それぞれの端部を長手方向に越えて延びる前記ワード線のいくつかの部分に形成するステップを含む、
請求項38の方法。
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EP2772942A3 (en) | 2014-12-31 |
US20140021550A1 (en) | 2014-01-23 |
KR101149666B1 (ko) | 2012-05-31 |
US20090239343A1 (en) | 2009-09-24 |
WO2008010891A2 (en) | 2008-01-24 |
US7602001B2 (en) | 2009-10-13 |
SG173381A1 (en) | 2011-08-29 |
CN101479852B (zh) | 2012-06-13 |
KR20090023496A (ko) | 2009-03-04 |
US9129847B2 (en) | 2015-09-08 |
WO2008010891A3 (en) | 2008-07-24 |
US20080012056A1 (en) | 2008-01-17 |
CN101479852A (zh) | 2009-07-08 |
EP2772942A2 (en) | 2014-09-03 |
TW200818406A (en) | 2008-04-16 |
JP5181304B2 (ja) | 2013-04-10 |
US8551823B2 (en) | 2013-10-08 |
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