TWI356471B - Capacitorless one transistor dram cell, integrated - Google Patents

Capacitorless one transistor dram cell, integrated Download PDF

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TWI356471B
TWI356471B TW96125888A TW96125888A TWI356471B TW I356471 B TWI356471 B TW I356471B TW 96125888 A TW96125888 A TW 96125888A TW 96125888 A TW96125888 A TW 96125888A TW I356471 B TWI356471 B TW I356471B
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TW200818406A (en
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Fernando Gonzalez
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Micron Technology Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment

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Description

1356471 九、發明說明： 【發明所屬之技術領域】 此發明係關於無電容一電晶體動態隨機存取記憶體單 元、包含無電容一電晶體動態隨機存取記憶體單元陣列之 積體電路、及無電容一電晶體動態隨機存取記憶體單元之 線路形成方法。 【先前技術】 在電腦系統中廣泛使用半導體記憶體（例如，動態隨機 存取記憶體（DRAM))來儲存資料。動態隨機存取記憶體單 元通常包括一存取場效電晶體（FET)與一儲存電容器。在 讀取與寫入操作期間，存取FET允許將資料電荷傳輸至儲 存電容器及傳輸來自儲存電容器之資料電荷。在更新操作 期間週期性更新儲存電容器上之資料電荷。 也開發了無電容一
決定記憶體單元之狀態。
而提出’不過其決不侷 範圍之字面意思限制， 122181.doc 1356471 且係依據等效者之原 無解釋性或其他限制性參考說明書 理。 【發明内容】 基於促進美國專利法"促進科學與有用技術之發展"（第！ ， 條，第8款）之立法目的提出本發明之此揭示内容。 • 。。論述首先以範例性無電容-電晶體動態隨機存取記憶體 早7G之線路形成方法開始進行。本發明之若干方面亦包括 • 無電容一電晶體動態隨機存取記憶體單元，及包含無電容 一電晶體動態隨機存取記憶體單元陣列之積體電路，其係 獨立於製造方法。 【實施方式】 參考圖1與2, 一般採用參考數字10指示基板（較佳為半 導體基板）。在此文件之上下文中，將術語"半導體基板"或 "半導電基板"定義為表示包含半導電材料之任何構造，其 包括但不受限於主體半導電材料（例如半導電晶圓）（單獨或 Φ 在其上包含其他材料之裝配件内），及半導電材料層（單獨 或在包含其他材料之裝配件内）。術語"基板"指任何支擇結 構，其包括但不受限於上述半導電基板。基板1〇包含一底 為 部基板12，例如主體單晶矽。不過，基板丨〇可包含另一基 板（現有或有待開發），且（例如）包含一絕緣物上半導體基 板。 形成基板10以包含半導電材料18之間隔島狀件20之範例 性線14、16。將線14、16顯示為本質上筆直線性，不過毫 無疑問涵蓋彎曲、雜齒狀、傾斜或其他形狀之線。一範例 122I81.doc 1356471 , 性較佳半導電材料18係（例如）由範例性主體半導體基板材 料12製成之單晶矽。僅以範例方式’一形成所述島狀件2〇 之範例性方法係藉由在島狀件20周圍橫向形成絕緣材料22 的現有或有待開發溝渠與再填充技術。一範例性較佳材料 包括一或二氧化矽及/或氮化矽之組合。可（例如）藉由將氧 原子離子植入主體基板材料12中直至一直接位於島狀件2〇 下方之峰值植入深度’並自此形成二氧化矽來製造從島狀 籲 件20下方升尚之絕緣材料22。或者，僅以範例方式（不過 欠佳），可沈積絕緣材料22，於其中蝕刻島狀件開口 2〇， 隨後以一半導電材料（例如，單晶及/或多晶矽）填充島狀件 開口20。當然，可另外以替代方式使用一或多個技術藉 以將橫向對置溝渠製造於半導體基板12中，之後在島狀件 . 20下方進行橫向底切蝕刻，且其中隨後以一或多個絕緣材 料填充底切體積。無論如何，在一範例性實施方案中’可 將絕緣材料22視為在個別島狀件2〇周圍及下方橫向加以接 • 收，且與此類島狀件之半導電材料18接觸。該論述基於方 便說明起見相對於一無電容一電晶體動態隨機存取記憶體 • 單元之線路形成方法（其係相對於半導電材料18之間隔島 狀件20之線14)繼續。 • #考圖3與4，形成-字元線24,其為間隔島狀件2〇之線 Η所共用，且在線14上方延伸。字元線24係、形成於個別間 隔島狀件20之-浮動主體區26上方。字元線24係（例如）藉 由/透過範例性所述介電層28而與主體區26間隔開且電^ 耦合至主體區26。此類介電層可能包含任何合適介電質， 122181.doc 1356471 , 自較佳矽半導電材料18熱生長之二氧化矽僅為一範例。材 料18之範例性較佳厚度範圍係自12埃至1〇〇埃。此外僅 以範例方式，材料18之範例性較佳深度係自5〇〇埃至1〇〇〇 埃。字兀線24較佳包含耐火金屬、耐火金屬矽化物、及/ 或導電摻雜半導電材料（例如多晶矽）中的任一者或組合。 在字元線24上接收一絕緣罩30，氮化矽及/或二氧化矽係 範例性材料。基於繼續論述目的，在範例性圖3之繪圖 中，可將字元線24視為包含一端32。基於繼續論述目的， 可將浮動主體區26視為具有一基底34，相對於該基底34接 收絕緣材料22。在僅僅一實施方案中，基底34下方之絕緣 材料22之範例性較佳厚度範圍係自5〇〇埃至3,〇〇〇埃。 參考圖5，在字元線/閘極24之側壁上形成絕緣材料托。 此類絕緣材料可包含一單一材料，或一或多個材料例 如，所述區域36各包含兩或更多不同絕緣材料層。範例性 較佳材料包括二氧化梦、氮切、氮氧切、二氧化給、 及/或氧化铭。材料36之範例性較佳厚度範圍係自5〇埃至 15〇埃m例，此類材料可藉由字元線24之材料之 侧壁上之熱生長或沈積而形成。或者，僅以範例方式，此 類材料可藉由沈積及-隨後無遮蔽各向異性間隔物蝕刻而 形成。 在字元線24上形成-導電層38且其與字元線糊隔開， 例如藉由絕緣/介電材料30與36而與之間隔開。層刊之範 例性較佳材料包括氣化鈦、多晶矽化型或nS)、鋁及矽 化鈷，層38之範例性較佳厚度範圍係自5〇埃至5〇〇埃。 122181.doc 1356471 參考圖6’在導電層38與字元線24上方形成一遮蔽塊 40。僅以範例方式，遮蔽塊40之較佳材料包括光阻。基於 繼續論述之目的’可將遮蔽塊40視為具有至少最靠近相對 於導電層38接收塊40之位置的間隔對置橫向邊緣42。
參考圖7，已有效加熱遮蔽塊4〇以使對置橫向邊緣42在 導電層38上以橫向向外彼此進一步遠離之方式移動。一用 於如此做的範例性技術包括在15〇。(：下加熱已圖案化光阻 遮蔽塊40持續一至三分鐘。在範例性較佳具體實施例中， 使對置橫向邊緣42橫向向外移動一距離，該距離實質上等 於材料38之自子元線24之橫向範圍向外的橫向厚度，其中 首先圖案化遮蔽塊40以與圖案化字元線及其上之絕緣罩式 材料3〇所依據之圖案實質上一致。
參考圖8至1〇 ’將遮蔽塊40(未顯示)用作-光罩來蝕刻 導電層38以形成一對互連閘極線4[46，其為間隔島狀件 20之線14所共用並在間隔島狀件2()之線14上方沿著且橫向 鄰接字元線24之對置側而延伸，在個別間隔島狀件2〇之個 別浮動主體區26上接收閘極線對44、46。此僅提供將導電 層38圖案化為一對閘極線(其為間隔島狀件之線所共用且 在間隔島狀件之線上沿著且橫、 绅接子70線之對置側而延 伸）的一範例性較佳方法。基於繼續論述目的，可將門極 線對44、46視為包含最靠折宝_… Γ將間極 匕3竑靠近子凡線端32之個別端48、5〇。 在一範例性實施方牵φ s WO 圖案化導致字元線端32並 不與閘極線j^48、50巾# 一 所千卢一私 者縱向共同疋位，例如，如圖 …較佳實施方案中’導電層38之圖案化導致字元 122181.doc 1356471 線24縱向超出閘極線對44、46之個別端48、50而延伸 如，如圖所示。無論如何，在一較佳實施方案令圖案化 形成長度比字元線24之長度短的閘極線對44、46。
參考圖9與1G，料字元線24形成-第—導電接點52, 且針對閘極線對44、46形成一第二導電接點54。因此，在 -最佳具體實施例令，+同的第一與第二導電接點係與個 别閘極線44、46及字7〇線24相關聯，因此可以熟習此項技 術者所熟知且(例如)如下所述方式對此加以獨立控制。㈣ 與10中僅以虛線圓概略指示接點52與54，因為亦可透過隨 後沈積之介電材料（圖式中基於清晰起見未顯示）在範例性 所述位置處形成此類接點。在一範例性較佳實施方案中， 針對字元線24之縱向超出閘極線對44、46之個別端48、5〇 而延伸的某一部分形成第-導電接點52，例如，如圖所 示0 參考圖11，在島狀件20之半導電材料18内自互連閉極線 對44、46橫向向外形成個別間隔源極/汲極區對6〇、62。 因此’通常且較佳地，導電層38之圖案化之後形成此類源 極；及極區無_如何，圖11描述一範例性經製造的無電 容一電晶體動態隨槪存取記憶體單元75 ^ 一方面，本發明涵蓋一種無電容一電晶體動態隨機存取 記憶體單元’其係獨立於製造方法且與是否製造複數個此 類動態隨機存取記憶體無關，不過製造複數個此類動態隨 機存取記憶體為佳且係典型者。此一動態隨機存取記憶體 單元包含在半導電材料内加以接收的一對間隔源極/汲極 122181.doc 1356471 區。上述形成於半導電材料18之範例性島狀件2〇内的區域 6〇、62僅為範例性構造。一電浮動主體區係佈置於該半導 電材料内之該等源極/汲極區之間。此外，僅以範例方 式，將該範例性單元描述為並非完全空乏，直接位於源極/ 區60 62下方之半導電材料亦包含電浮動主體區/材 料。 第閘極係與該等源極/汲極區之間之該主體區間隔 φ 竭且電令耦合至該主體區。字元線24之在個別島狀件2〇上 加ス接收之部分僅為一範例性此類第一閘極。一對對置導 電互連第二閘極係與該第一閘極間隔開且係自該第一閘極 向向外加以接收。該等第二閘極係與自該第一閘極橫向 向外且位於該源極/汲極區對之間的該主體區間隔開且電 • 容耦合至該主體區。僅以範例方式，第二閘極44、46構成 一範例性此類第二閘極對。在一所述且較佳實施方案中， 第二閘極44、46係藉由第一閘極24上方第二閘極對料、46 # 之間向上延伸之導電材料（即，導電材料區70)而彼此導電 =連。第二閘極對44、46可以另一方式（舉例而言且僅以 犯例方式，藉由形成於最初隔離第二閘極44、46上之一獨 導電層）導電互連。在此類實例中，此類導電層可與製 • 造問極44、46所採用之材料的導電層相同或不同。此外’ 毫…、疑問，閘極44與46無須具有相同成分，不過具有相同 成分之閘極44與46較佳。 在—較佳實施方案中，無電容一電晶體動態隨機存取記 憶體單元包含一含半導電材料之島狀件的基板。在島狀件 122181.doc -12· 周圍及下方橫向接收絕緣材料且其與島狀件之半 接觸。在島狀件半導電材料内接收一對間隔源極/沒極 區。-電浮動主體區係佈置於該島狀件半導電材料内之該 等源極/沒極區之間。一第一閉極係與該等島狀件源極/汲 極區之間之島狀件主體區間隔開且電容耦合至該島狀件主 體區。-對導電第二閘極係與該第一閘極間隔開且係自該 第-閘極橫向向外加以接收，該等第二閘極係與自該第一 閘極橫向向外且位於該源極/汲極區對之間的該主體區間 隔開且電容耦合至該主體區。此可包含於上述方法及結構 中的任一者中。 圖12描述為圖丨丨之具體實施例之替代者且與之相對應的 一範例性額外實施方案與具體實施例。必要時使用與首先 說明之具體實施例相同的數字，以尾綴"a"或不同數字指 示區別。在圖12中，較佳在個別島狀件2〇周圍及下方橫向 接收絕緣材料22a且其與此類島狀件之半導電材料丨8接 觸°在個別島狀件20周圍及下方自絕緣材料22a向外橫向 接收導電摻雜半導電材料80。範例性較佳材料80係導電摻 雜P型或η型多晶矽。較佳地，位於島狀件2〇下方以及島狀 件20與導電摻雜半導電材料8〇之橫向側壁中間的絕緣材料 22a均具有不大於2〇〇埃之厚度。材料22a之更佳此類厚度 範圍係自50埃至150埃。當然，圖12之構造可以任何現有 或有待開發方法進行製造。 熟習此項技術者應明白且可開發用於在上述範例性動態 隨機存取記憶體單元内，及包含此類動態隨機存取記憶體 122181.doc 13 早元陣列之積體電路中寫入、讀取、更新、及/或保存資 料的各種操作電壓。僅以範例方式，以下圖表描述範例性 作電壓，jMl ψ Λ/ A4 ”甲Vl係第一閘極電壓，vcs(導電間隔物）係 第一閘極對之電壓，Vt係臨限電壓U源極電壓，而 電壓《此外’僅以範例方式在使用圖12之具體實 施例中之導電壤繞半導電材料8Q之情況下，較佳使此類材 料維持丨亙疋（在-3 v至-1 〇 v間之某一合適範例性固定電壓 下）°使用環繞導電摻雜半導電材料8〇之一較佳非限制性 原因係建立及維持電晶體之較佳聚乙烯之兩側的相同電 位，以便藉由介電電容在結構之壁處收集電荷。 範例性操作電壓
Vcs vt VD Vs 寫入 -3 V至-10 V -2.5 V 高 1.8 V/0 V 浮動/ον 保存資料 -3 V至-10 V 0V 浮動/浮動 浮動/ον 讀取 2.5 V 2.5 V 0.5 V 0.1 V/0.1 V 0 V/0V 重寫 -3 V至-10V -2.5 V 高 1.8 V/0 V 浮動/ον 保存資料 -3 V至-10V ον 兩 浮動/浮動 浮動/ον 舉例而言，在美國專利第6,969,662號；美國專利申請公 告案第 2005/0017240 與 2005/0063224 號；Kuo 等人之"A Capacitorless Double-Gate DRAM Gate Cell Design For High Density Applications"(IEDM，IEEE 2002，第 843 至 846頁）；及Yoshida 等人之"A Capacitorless 1 T-DRAM， Technology Using Gate-Induced Drain-Leakage (GIDL) 122181.doc -14- 1356471 .
Current For Low-Power And High-Speed Embedded Mem〇ry"_E電子裂置彙刊，第53卷，第4號，2006年4 Θ帛692至697頁）中揭示用於無電容一電晶體動態隨機 存取記憶體單元之操作的範例性技術與構造。將美國專利 ^ 5,714,786 ； 6,005,273 ； 6,090,693 ； ^ 7,005,71 〇 ^ ^ ^ 示内容以引用方式併入本文中。 已遵循法規，以一定程度上為結構與方法特徵特有之語 • ^說明本發明。不過，應明白’本發明不受限於所顯示及 說明之特疋特徵，因為本文揭示之方法包含實施本發明之 較佳形式。因此，本發明係以隨附申請專利範圍之正確範 疇内依據等效者之原理加以恰當解釋的其任何形式或修改 進行申請。 • 【圖式簡單說明】 上面已參考以下附圖說明本發明之較佳具體實施例。 圖1係依據本發明之一方面的一處於製程中之半導體基 籲 板的概略俯視平面圖。 圖2係穿過圖丨之線2至2所獲取的概略斷面圖。 圖3係圖1之基板處於一在圖1所示處理步驟之後之處理 步驟中的圖式。 • 圖4係穿過圖3之線4至4所獲取的概略斷面圖。 圖5係圖4之基板處於一在圖4所示處理步驟之後之處理 步驟中的圖式。 圓6係圖5之基板處於一在圖5所示處理步驟之後之處理 步驟中的圖式。 122181.doc 1356471 圖7係圖6之基板處於一在圖6所示處理步驟之後之處理 步驟中的圖式。 圖8係圖7之基板處於一在圖7所示處理步驟之後之處理 步驟中的圖式。 圖9係圖8之基板之概略透視圖。 圖10係圖8與9之基板之概略俯視平面圖，圖8係穿過圖 10之線8至8所獲取之圖式。
圖11係圖8之基板處於一在圖8所示處理步驟之後之處理 步驟中的圖式。 圖12係圖11之基板之替代具體實施例基板的概略斷面 圖。 【主要元件符號說明】 10 基板 12 底部基板/主體半導體基板材料 14 、 16 線
18 半導電材料 20 島狀件/島狀件開口 22 ' 22a 絕緣材料 24 字元線/第一閘極 26 浮動主體區 28 介電層 30 絕緣罩/絕緣/介電材料 32 字元線端 34 基底 122181.doc ^ 1356471 36 絕緣材料/區域 38 導電層/材料 40 遮蔽塊 42 對置橫向邊緣 44、46 閘極線/第二閘極 48 ' 50 閘極線端 52 第一導電接點 54 第二導電接點 60 ' 62 間隔源極/汲極區 70 導電材料區 75 無電容一電晶體動態隨機存取記憶體單元 80 導電摻雜半導電材料 122181.doc -17·

Claims (1)

1356471 . 第096125888號專利申請案 • 中文申清專利範圍替換本(1〇〇年3月） 十、申請專利範圍： 一種無電容一電晶體動態隨機存取記憶體單元，其包 含： 一對間隔源極/汲極區，其係在半導電材料内加以接 收； 電浮動主體區，其係佈置於該半導電材料内之該等 源極/汲極區之間；該浮動主體區具有一基底，相對於該 基底接收一絕緣層，相對於該基底下方之該絕緣層接收 # 導電摻雜半導電材料； 第閘極’其係與該等源極/及極區之間之該主體區 間隔開且電容耦合至該主體區；及 對對置導電互連第一閘極，其係與該第一閘極間隔 • 開及與該第一閘極電性絕緣且係自該第一閘極橫向向外 加以接收，該等第二閘極係與在該第一閘極橫向向外的 該主體區間隔開且電容耦合，並且該第二閘極在該源極/ 沒極區對之間電容耦合至該主體區。 _ 2.如請求項丨之動態隨機存取記憶體單元，其中該第二閘 極對係藉由在該第一閘極上方該第二閘極對之間向上延 伸之導電材料而導電互連。 3. 如請求項1之動態隨機存取記憶體單元，其中該第一問 極係藉由至少兩絕緣材料而與該等第二閘極分離。 4. 如請求項1之動態隨機存取記憶體單元，其中該浮動主 體區具有一基底，相對於該基底接收—絕緣層，該絕緣 層具有一自500埃至3，000埃之厚度。 122181-1000324.doc 1356471 5·如請求項1之動態隨機存取記憶體單元，其中該基底與 該導電摻雜半導電材料中間的該絕緣層具有一不大於; 200埃之厚度。 6. 一種無電容一電晶體動態隨機存取記憶體單元，其包 含： 、 一基板’其包含一半導電材料之島狀件； 絕緣材料，其係在該島狀件周圍及下方加以接收且與 該島狀件之半導電材料接觸； 一對間隔源極/汲極區，其係在該島狀件半導電材料内 加以接收； 一電浮動主體區，其係佈置於該島狀件半導電材料 内； 一第—閘極，其係至少部分與該等島狀件源極/汲極區 之間之該島狀件浮動主體區間隔開且電容耦合至該島狀 件主體區；及 對導電第一閘極，其係與該第一閘極間隔開且係自 該第一閘極橫向向外加以接收，該等第二閘極係與自該 第一閘極橫向向外且至少部分位於該源極/汲極區對之間 的該島狀件浮動主體區間隔開且電容耦合至該島狀件浮 動主體區。 7. 如請求項6之動態隨機存取記憶體單元，其包含在該島 狀件周圍及下方自該絕緣材料向外加以接收之導電摻雜 半導電材料。 8·如請求項7之動態隨機存取記憶體單元，其中位於該島 122181-1000324.doc 9. 10. π. 12. 13. 狀件下方之該絕缘材料具有一不大於2〇〇埃之厚度。 ::求項7之動態隨機存取記憶體單元，其中該島狀件 i古 何枓之榼向側壁中間的該絕緣材料 具有—不大於200埃之厚度。 刊付 之動態隨機存;記憶體單元，其中位於該島 方以及该島狀件與該導電摻雜半導電材料 側壁中間的該絕緣材料具有一不大於200埃之厚度。、 如明求項7之動態隨機存取記憶體單元，其中位於該島 狀件下方之該絕緣材料具有—自5〇埃至15〇埃之厚度7 如請求項7之動態隨機存取記憶體單元，其中該：狀件 與該導電掺雜半導電材料之橫向側壁中間的該絕緣材料 具有一自50埃至150埃之厚度。 一種包含無電容一電晶體動態隨機存取記憶體單元之一 陣列之積體電路，其包含： 一半導電材料之間隔島狀件之串列，其係在一基板内 加以接收；及 個別無電容一電晶體動態隨機存取記憶體單元，其係 相對於該等間隔島狀件中的個別間隔島狀件加以接收， 每一該等個別單元包含： 一對源極/汲極區，其係在該個別島狀件之該半導電 材料内加以接收； 一電浮動主體區，其係佈置於該個別島狀件之該半 導電材料内； 第一閘極，其包含一字元線，該字元線係為該間 12218M000324.doc 1356471 隔島狀件之串列所共用且在至少部分該間隔島狀件之串 列上方該等個別源極/及極區對之間延伸，該字元線具有 數個橫向側且係與該等個別島狀件之該等個別主體區間 隔開且電容輕合至該等個別主體區；及 一對對置導電互連第二閘極，其係與該第一閘極間 隔開且自該第一閘極橫向向外加以接收，該等第二閘極 係與自該等個別第一閘極橫向向外且在該等個別島狀件 之至少部分5玄等個別源極/汲極區對之間的該等個別主體 區間隔開且電容耦合至該等個別主體區，該對置互連第 二閘極對包含一導電線，其係為該間隔島狀件之串列所 共用且延伸於在該字元線之該等橫向側上並且延伸至該 字元線之該等橫向側。 14. 如請求項13之積體電路，其包含一連接至該字元線之第 一導電接點及一連接至該導電線的不同的第二導電接 點。 15. 如請求項13之積體電路，其中該字元線之長度比該導電 線之長度長。 16. 如請求項13之積體電路，其中該導電線具有一端且該字 元線具有一最靠近該導電線端的端，該字元線端與該導 電線端並不縱向共同定位。 17. 如請求項16之積體電路，其中該字元線之長度比該導電 線之長度長。 18. 如請求項16之積體電路，其中自該導電線端縱向向外接 收該字元線端。 122181-1000324.doc 19·如請求項18之積體電路’其中該字元線之長度比該導電 線之長度長。 20.如請求項13之積體電路，其包含：絕緣材料，其係在該 等個別島狀件周圍及下方加以接收且與該等個別島狀件 之半導電材料接觸；及 ▲導電摻雜半導電材料，其係在該島狀件周圍及下方自 該絕緣材料向外加以接收。 h.如請求項20之積體電路，其中位於該等個別島狀件下方 以及該等個別島狀件與該導電掺雜半導電材料之橫向側 土中間的该絕緣材料均具有一不大於2〇〇埃之厚度。 22·種形成無電容一電晶體動態隨機存取記憶體單元之一 串列之方法，其包含： 相對於-基板形成一半導電材料之間隔島狀件之举 形成一字元線，其係為該間隔島狀件之串列所丑用且 =㈣隔、島狀件之串列上方延伸，在該等個別間隔島狀 之電浮動主體區上方形成該字元線； 在該字元線上方且與該字元線間隔開形成-導電層； =導電層圖案化為一對閑極線，其係為該間隔島狀 件之線所共用且在該間隔島狀件之串列上方該字元線之 對：側上至少部分延伸，在該等個別間隔島狀件之個別 ::主體區上方接收該間極線對，該圖案化形成長度比 μ子7C線之長度短的該閘極線對，·及 在該等個別島狀件之該半導電材料内形成個別間隔源 I22I8M 000324.doc 極/汲極區對，該等間隔源極/汲極區對包括於該閘極線 對橫向向外形成的部分。 23 24 25 26 27. 28. •如請求項22之方法’其中該圖案化之後形成該等源極/汲 極區。 .如請求項22之方法，其包含針對該字元線形成一第一導 電接點及針對該閘極線對形成一第二導電接點。 .如請求項22之方法，其中形成該字元線以具有一端且該 圖案化形成該閘極線對之一最靠近該字元線端之個別 端’該圖案化導致該字元線端並不與該等閘極線端中任 —者縱向共同定位。 •如請求項22之方法’其中該圖案化包含： 在該導電層及該字元線上方形成一遮蔽塊，該遮蔽塊 具有間隔對置橫向邊緣； 形成該遮蔽塊之後，有效加熱該遮蔽塊以使該等對置 榀向邊緣在該導電層上以橫向向外彼此進一步遠離之方 式移動；及 該加熱之後，將該遮蔽塊用作一光罩蝕刻該導電層以 形成該閘極線對， 曰 如請求項26之方法，其中形成該字元線以具有一端且該 圖案化形成該閘極線對之一最靠近該字元線端之個別 端’該圖案化導致該字元線端並不與該等閘極線端 一者縱向共同定位。 如請求項22之方法，其包含： 在該等個別島狀件周圍及下方橫向且與該等個別島狀 122181-1000324.doc 1356471 牛之半導電材料接觸來提供絕緣材料；及 在該島狀件周圍及下方自該絕科 摻雜坐请杂向外橫向提供 電摻雜半導電材料 29·—種形成無電容一電 導 晶體動態隨機存取記 ，列之方法，其包含： …憶體單元之相對於一基板形成一半導電材料之 列； 間隔島狀件之串 在該間隔I: 係為該間隔島狀件之串列所共用且 件：一雷件之串列上方延伸’在該等個別間隔島狀 2 一電浮動主體區上方形成該字元線且其包含-端’· 字70線上方且與該字元線間隔開形成-導電層； 將該導電層圖案化為-對閉極線，其料該間隔島狀 牛之線所共用且在該間隔島狀件之串列上方該字元線之 對置側上至少部分延伸，在該等個別間隔島狀件之個別 汙動主體區上方接收該閘極線對，該圖案化形成該閘極 線對之最靠近該字元線端之個別端，該圖案化導致該字 元線縱向超出該閘極線對之該等個別端而延伸；及 在該等個別島狀件之該半導電材料内形成個別間隔源 極/汲極區對，該等間隔源極/汲極區對包括於該閘極線 對橫向向外形成的部分。 30.如請求項29之方法，其中該圖案化包含： 在該導電層及該字元線上方形成一遮蔽塊，該遮蔽塊 具有間隔對置橫向邊緣； 形成該遮蔽塊之後，有效加熱該遮蔽塊以使該等對置 122181-1000324.doc 1356471 橫向邊緣在該導電層上以橫向向外彼此進一步遠離之方 式移動；及 該加熱之後’將該遮蔽塊用作—光罩蝕刻該導電層以 形成該閘極線對。 31 32 33 34. •如請求項29之方法，其包含針對該字元線形成一第一導 電接點及針對該閘極線對形成一第二導電接點。 ’如凊求項3 1之方法，其包含針對該字元線之縱向超出該 閘極線對之該等個別端而延伸的某一部分形成該第一導 電接點。 •如請求項29之方法，其包含： 在該等個別島狀件周圍及下方橫向且與該等個別島狀 件之半導電材料接觸來提供絕緣材料；及 在〆島狀件周圍及下方自該絕緣材料向外橫向提供導 電摻雜半導電材料。 一種形成無電容—電晶體動態隨機存取記憶體單元之-_列之方法，其包含： 相對於-基板形成一半導電材料之間隔島狀件之串 ，'為〇間隔島狀件之串列所共用 件之- Γ、島狀件之串列上方延伸，在該等個別間隔島 :電洋動主體區上方形成該字元線； =:凡線上方且與該字元線間隔開形成一導電層: ;;導電層及該字元線上方形成一遮蔽塊，該遮蔽 具有間搞對置橫向邊緣； 122181-1000324.doc 1356471 形成該遮蔽塊之後，加熱該遮蔽塊以使該等對置橫向 邊緣在該導電層上以橫向向外彼此進一步遠離之方式移 動； 該加熱之後，將該遮蔽塊用作一光罩蝕刻該導電層以 形成一對互連閘極線，其係為該間隔島狀件之串列所共 用且在該間隔島狀件之線上方該字元線之對置側上至少 部分延伸，在該等個別間隔島狀件之個別浮動主體區上 方接收該閘極線對；及 在該等個別島狀件之該半導電材料内形成個別間隔源 極/及極區對’該等間隔源極/汲極區對包括於該閘極線 對橫向向外形成的部分。 3 5.如吻求項34之方法，其包含形成該遮蔽塊以包含光阻。 36.如凊求項34之方法，其中該圖案化之後形成該等源極/汲 37. 38.
如請求項34之方法，其包含針對該字元線形成-第一 電接點及針對該閘極線對形成—第：導電接點。 如請求項37之方法 閘極線對之該等個 電接點。 ，其包含針對該字元線之縱向超出該 別端而延伸的某一部分形成該第一導 39. 一種形成無電容—電晶 串列之方法，其包含： 體動態隨機存取記憶體單元之 相對於一基板形成—半 列； 導電材料之間隔島狀件之$ 形成一字元線 其係為該間隔島狀件之串列所共用且 12218I-1000324.doc 丄妁6471 在該間隔島狀件之串列上方延伸，該字 別間隔島狀件之一電浮動主體 ’、’ ’、^等個 谷一 體區上方形成且電容性耦合 至該電浮動主體區； 成導電互連之1極線對，其至少部分延伸於該字 :、:之對置側上之間隔島狀件之該串列上，並且其與該 子凡線電性絕緣’該閘極線對被接收於該個別間隔島狀 件之個別浮動主龍上且與該個別間隔島狀件之個別浮 動主體區電容耦合；及 在該等個別島狀件之該半導電材料内形成個別間隔源 極/汲極區對，該等間隔源極/汲極區對包括於該閘極線 對橫向向外形成的部分。 40. 41. 42. 43. 如明求項39之方法，其中該等源極/汲極區形成於形成互 連之該閑極線對之後。 如請求項39之方法，其包含形成一第一導電接觸至該字 元線且一第二導電接觸至該閘極線對。 如凊求項39之方法’其中該字元線經形成以具有一端及 形成該閘極線對之一個別端，其接近該字元線端，該字 兀線端並未縱向地與該等閘極線端之任一端放在一起。 如請求項40之方法’其中形成該導電互連閘極線包含： 在该導電層及該字元線上方形成一遮蔽塊，該遮蔽塊 具有間隔對置橫向邊緣； 形成該遮蔽塊之後，加熱該遮蔽塊以使該等對置橫向 邊緣在該導電層上以橫向向外彼此進一步遠離之方式移 動； 12218M000324.doc •10· 1356471 該加熱之後，將該遮蔽塊用作一光罩钮刻該導電層以 形成該閘極線對。 44.如請求項43之方法，其中該字元線經形成以具有—端及 形成該導電互連閘極線形成該閘極線對之一個別端，其 接近該字元線端，料元線端並未縱向地與料問極線 端之任一端放在一起。 ' 45·如5青求項39之方法，其包含：
在該等個別島狀件周圍及下方橫向且與該等個別島狀 件之半導電材料接觸來提供絕緣材料；及 在該島狀件周圍及下方自該絕緣材料向外橫向提供導 電摻雜半導電材料。 46. —種形成無電容一電晶體動態隨機存取記憶體單元之一 串列之方法，其包含： 相對於一基板形成一半導電材料之間隔島狀件之串 列； 形成一字元線，其係為該間隔島狀件之串列所共用且 在該間隔島狀件之串列上方延伸，在該等個別間隔島狀 件之一電浮動主體區上方形成該字元線及包含一端； 升y成導電互連之一閘極線對，其至少部分延伸於該字 兀線之對置側上之間隔島狀件之該串列上，並且其與該 字元線電性絕緣，該閘極線對被接收於該個別間隔島狀 件之個別浮動主體區上且與該個別間隔島狀件之個別浮 動主體區電容耦合，該閘極線對之個別端接近該字元線 端，該字元線十之該圖案化結果向超出該閘極線對之該 122181-1000324.doc 丄乃0471 等個別端縱向延伸。 .如叫求項46之方法，其包含形成一第一導電接觸至該字 几線且一第二導電接觸至該閘極線對。 8·如叫求項47之方法，其包含形成一第一導電接觸至向超 出該閘極線之個別端上之該字元線之某些部分縱向延 伸。 49·如請求項46之方法，其包含： 在該等個別島狀件周圍及下方橫向且與該等個別島狀 件之半導電材料接觸來提供絕緣材料；及 $ 在該島狀件周圍及下方自該絕緣材料向外橫向提供導 電摻雜半導電材料。 5〇.—種形成無電容一電晶體動態隨機存取記憶體單元之一 串列之方法，其包含： 相對於一基板形成一包含石夕之半導電材料之間隔島狀 件之串列； 形成一字元線，其係為該間隔島狀件之串列所共用且 在該間隔島狀件之串列上方延伸，在該等個別間隔島狀鲁 件之一電浮動主體區上方形成該字元線； 在该字元線上方且與該字元線間隔開形成一導電層； 在該導電層及該字元線上方形成一遮蔽塊，該遮蔽塊 具有間隔對置橫向邊緣； 形成該遮蔽塊之後，加熱該遮蔽塊以使該等對置橫向 邊緣在該導電層上以橫向向外彼此進一步遠離之方式移 動； 122181-1000324.doc 12 1356471 · .該加熱之後，將該遮蔽塊用作一光罩蝕刻該導電層以 形成一對互連閘極線，其係為該間隔島狀件之串=所共 用且在該間隔島狀件之串列上方該字元線之對置側上延 伸’在該等個別間隔島狀件之個別浮動主體區上方接收 該閘極線對；及 在該等個別島狀件之該半導電材料内形成個別間隔源 極/汲極區對，該等間隔源極/汲極區對包括於該閘極線 對橫向向外形成的部分。 參 51. 一種圖案化一基板之方法，其包含： 相對於一基板形成一凸起特徵，該凸起特徵包含一頂 部及對置侧牆； 形成一層以被圖案化.於該凸起特徵之該頂部及對置側 牆上； 形成一遮蔽塊於該層上，該遮蔽塊具有間隔對置橫向 邊緣； ' 齡形成该遮蔽塊之後，加熱該遮蔽塊以使該等對置橫向 邊緣在該層上以橫向向外彼此進一步遠離之方式移動； 及 ， 該加熱之後’將該遮蔽塊用作一光罩蝕刻該層以分離 被接收於該頂部之上之該層及該凸起特徵之對置側牆。 52. 如請求項51之方法，其中該遮蔽塊包含光阻劑。 53. 如請求項52之方法，其中該加熱大約至15〇β(：。 54. 如請求項53之方法，其中該加熱大約為一到三分鐘。 55. 如請求項51之方法，其中㈣蔽塊高於相對於該基板凸 122181-1000324.doc 丄乃()471 起之該特徵。 56. 57. 58. 59. 60. 61. 如凊求項51之方法，其中該對置橫向邊緣之每一橫向向 外：動實質上等於該層之厚度之一距離。 月长項51之方法，其中該遮蔽塊包含光阻劑，並且該 對置橫向邊緣之每—橫向向外移動實質上等於該層之厚 度之一距離。 一種形成兩個導電線之方法，包含： 形成一凸起第一導電線於一基板上； 絕緣該凸起導電線之一頂部及側牆； 形成導電材料於該凸起第一導電線之絕緣的該頂部 上； 形成遮蔽塊於該導電材料上，該遮蔽塊具有間隔對 置橫向邊緣； 形成該遮蔽塊之後，加熱該遮蔽塊以使該等對置橫向 邊緣在該導電材料上以橫向向外彼此進一步遠離之方式 移動；及 。亥加熱之後，將該遮蔽塊用作一光罩來餘刻該導電材 料以形成一第二導電線於該第一導電線上並且與該第一 導電材料電性絕緣。 如請求項58之方法，其中該第二導電線係橫向接收於該 第一導電線之該等侧牆上。 如請求項58之方法，其中該遮蔽塊包含光阻劑。 如請求項58之方法，其中該遮蔽塊高於相對於該基板凸 起之該第一導電線。 122181-1000324.doc • 14· 1356471 . A如請求項58之方法，其中該等對置 向外移動實質上等於該層之厚度之—距離母一棱向 63. —種圖案化一基板之方法，其包含： 相對於一基板形成一凸起特徵. 形成一層以被圖案化於該凸起特徵上； 形成一遮蔽塊於該層上，該逆益 成避敗塊具有間隔對置橫向 邊緣； 形成該遮蔽塊之後，加熱該遮蔽塊以使該等對置橫向 邊緣在該層上以橫向向外彼此進—步遠離之方式移動， 該等對置橫向邊緣之每一橫向向外移動之一距離實質上 等於該層之厚度；及 該加熱之後’將該遮蔽塊用作—光罩來姓刻該層以使 該層被接收於該凸起特徵上。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547945B2 (en) * 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7384849B2 (en) * 2005-03-25 2008-06-10 Micron Technology, Inc. Methods of forming recessed access devices associated with semiconductor constructions
US7282401B2 (en) * 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) * 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US7700441B2 (en) * 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7602001B2 (en) 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7772632B2 (en) * 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7589995B2 (en) * 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
KR101324196B1 (ko) * 2007-06-05 2013-11-06 삼성전자주식회사 커패시터리스 디램 및 그의 제조방법
US8889559B2 (en) 2012-12-12 2014-11-18 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8889558B2 (en) 2012-12-12 2014-11-18 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8999852B2 (en) 2012-12-12 2015-04-07 Micron Technology, Inc. Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate
US8937018B2 (en) * 2013-03-06 2015-01-20 Micron Technology, Inc. Methods of forming a pattern on a substrate
US10068918B2 (en) 2015-09-21 2018-09-04 Globalfoundries Inc. Contacting SOI subsrates
US9859388B1 (en) 2016-06-17 2018-01-02 International Business Machines Corporation Uniform vertical field effect transistor spacers
US9812443B1 (en) 2017-01-13 2017-11-07 International Business Machines Corporation Forming vertical transistors and metal-insulator-metal capacitors on the same chip

Family Cites Families (311)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147280A (en) * 1975-06-13 1976-12-17 Hitachi Ltd Semiconductor device
JPS5681974A (en) 1979-12-07 1981-07-04 Toshiba Corp Manufacture of mos type semiconductor device
JPS58220464A (ja) * 1982-06-17 1983-12-22 Fujitsu Ltd 半導体記憶装置
KR920010461B1 (ko) 1983-09-28 1992-11-28 가부시끼가이샤 히다찌세이사꾸쇼 반도체 메모리와 그 제조 방법
JPS60256747A (ja) 1984-06-01 1985-12-18 Nippon Denso Co Ltd 空調装置の吹き出し口
DE3570557D1 (en) 1984-11-27 1989-06-29 American Telephone & Telegraph Trench transistor
GB2190789B (en) * 1986-04-17 1990-05-09 Plessey Co Plc System for optically coupling components of integrated circuits
US4722910A (en) * 1986-05-27 1988-02-02 Analog Devices, Inc. Partially self-aligned metal contact process
US4835741A (en) 1986-06-02 1989-05-30 Texas Instruments Incorporated Frasable electrically programmable read only memory cell using a three dimensional trench floating gate
US5160491A (en) 1986-10-21 1992-11-03 Texas Instruments Incorporated Method of making a vertical MOS transistor
JPS63183691A (ja) 1987-01-26 1988-07-29 Mitsubishi Electric Corp 半導体記憶装置
FR2625044B1 (fr) 1987-12-18 1990-08-31 Commissariat Energie Atomique Transistor mos a extremite d'interface dielectrique de grille/substrat relevee et procede de fabrication de ce transistor
US4979004A (en) 1988-01-29 1990-12-18 Texas Instruments Incorporated Floating gate memory cell and device
US4931409A (en) 1988-01-30 1990-06-05 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device having trench isolation
US5014110A (en) 1988-06-03 1991-05-07 Mitsubishi Denki Kabushiki Kaisha Wiring structures for semiconductor memory device
JPH0294477A (ja) 1988-09-30 1990-04-05 Toshiba Corp 半導体装置及びその製造方法
JPH0778977B2 (ja) 1989-03-02 1995-08-23 松下電器産業株式会社 磁気ディスクカートリッジ
US5108938A (en) 1989-03-21 1992-04-28 Grumman Aerospace Corporation Method of making a trench gate complimentary metal oxide semiconductor transistor
US5021355A (en) 1989-05-22 1991-06-04 International Business Machines Corporation Method of fabricating cross-point lightly-doped drain-source trench transistor
JPH03219677A (ja) 1990-01-24 1991-09-27 Fujitsu Ltd 半導体装置
US5107459A (en) 1990-04-20 1992-04-21 International Business Machines Corporation Stacked bit-line architecture for high density cross-point memory cell array
JPH0834302B2 (ja) 1990-04-21 1996-03-29 株式会社東芝 半導体記憶装置
US5013680A (en) 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5244824A (en) 1990-09-05 1993-09-14 Motorola, Inc. Trench capacitor and transistor structure and method for making the same
US5047117A (en) 1990-09-26 1991-09-10 Micron Technology, Inc. Method of forming a narrow self-aligned, annular opening in a masking layer
US5289030A (en) 1991-03-06 1994-02-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with oxide layer
US5122848A (en) 1991-04-08 1992-06-16 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
JPH07106435B2 (ja) 1991-04-15 1995-11-15 新日本製鐵株式会社 双ロール式連続鋳造装置
KR940006679B1 (ko) 1991-09-26 1994-07-25 현대전자산업 주식회사 수직형 트랜지스터를 갖는 dram셀 및 그 제조방법
US5467305A (en) 1992-03-12 1995-11-14 International Business Machines Corporation Three-dimensional direct-write EEPROM arrays and fabrication methods
US5254218A (en) 1992-04-22 1993-10-19 Micron Technology, Inc. Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer
US5573837A (en) 1992-04-22 1996-11-12 Micron Technology, Inc. Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer
JP2748072B2 (ja) 1992-07-03 1998-05-06 三菱電機株式会社 半導体装置およびその製造方法
US5281548A (en) 1992-07-28 1994-01-25 Micron Technology, Inc. Plug-based floating gate memory
JP2889061B2 (ja) 1992-09-25 1999-05-10 ローム株式会社 半導体記憶装置およびその製法
JP3311070B2 (ja) 1993-03-15 2002-08-05 株式会社東芝 半導体装置
US5358879A (en) * 1993-04-30 1994-10-25 Loral Federal Systems Company Method of making gate overlapped lightly doped drain for buried channel devices
WO1994027325A1 (en) 1993-05-07 1994-11-24 Vlsi Technology, Inc. Integrated circuit structure and method
KR0141218B1 (ko) 1993-11-24 1998-07-15 윤종용 고집적 반도체장치의 제조방법
US5514604A (en) 1993-12-08 1996-05-07 General Electric Company Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making
US5532089A (en) 1993-12-23 1996-07-02 International Business Machines Corporation Simplified fabrication methods for rim phase-shift masks
KR100362751B1 (ko) 1994-01-19 2003-02-11 소니 가부시끼 가이샤 반도체소자의콘택트홀및그형성방법
US5964750A (en) 1994-03-15 1999-10-12 Medolas Gesellschaft Fuer Medizintechnik Gmbh Laser catheter for bypass surgery
JP2658870B2 (ja) 1994-04-22 1997-09-30 日本電気株式会社 半導体記憶装置およびその製造方法
US5413949A (en) 1994-04-26 1995-05-09 United Microelectronics Corporation Method of making self-aligned MOSFET
US5446299A (en) * 1994-04-29 1995-08-29 International Business Machines Corporation Semiconductor random access memory cell on silicon-on-insulator with dual control gates
US5841611A (en) 1994-05-02 1998-11-24 Matsushita Electric Industrial Co., Ltd. Magnetoresistance effect device and magnetoresistance effect type head, memory device, and amplifying device using the same
KR0151195B1 (ko) * 1994-09-13 1998-10-01 문정환 박막 트랜지스터의 구조 및 제조방법
US5753947A (en) * 1995-01-20 1998-05-19 Micron Technology, Inc. Very high-density DRAM cell structure and method for fabricating it
US5574621A (en) 1995-03-27 1996-11-12 Motorola, Inc. Integrated circuit capacitor having a conductive trench
US5567634A (en) 1995-05-01 1996-10-22 National Semiconductor Corporation Method of fabricating self-aligned contact trench DMOS transistors
DE19519160C1 (de) 1995-05-24 1996-09-12 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
JPH0982918A (ja) 1995-09-19 1997-03-28 Toshiba Corp 半導体記憶装置およびその製造方法
KR0179175B1 (ko) * 1995-10-05 1999-03-20 문정환 반도체 메모리 장치 및 제조방법
US5854501A (en) 1995-11-20 1998-12-29 Micron Technology, Inc. Floating gate semiconductor device having a portion formed with a recess
US6420786B1 (en) * 1996-02-02 2002-07-16 Micron Technology, Inc. Conductive spacer in a via
JP2751909B2 (ja) 1996-02-26 1998-05-18 日本電気株式会社 半導体装置の製造方法
US6090700A (en) 1996-03-15 2000-07-18 Vanguard International Semiconductor Corporation Metallization method for forming interconnects in an integrated circuit
JP3219677B2 (ja) 1996-03-28 2001-10-15 三洋電機株式会社 ロッド選別システム
US5869539A (en) 1996-04-17 1999-02-09 Board Of Regents, The University Of Texas System Emulsions of perfluoro compounds as solvents for nitric oxide (NO)
UA41477C2 (uk) 1996-05-21 2001-09-17 Сіменс Акцієнгезельшафт Багатошаровий конденсатор тонкошарової конструкції і спосіб його виготовлення
DE19620625C1 (de) 1996-05-22 1997-10-23 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
JPH1022476A (ja) 1996-07-02 1998-01-23 Sony Corp 容量素子
US5792687A (en) 1996-08-01 1998-08-11 Vanguard International Semiconductor Corporation Method for fabricating high density integrated circuits using oxide and polysilicon spacers
TW308727B (en) 1996-08-16 1997-06-21 United Microelectronics Corp Semiconductor memory device with capacitor (4)
TW304290B (en) 1996-08-16 1997-05-01 United Microelectronics Corp The manufacturing method for semiconductor memory device with capacitor
US5739066A (en) 1996-09-17 1998-04-14 Micron Technology, Inc. Semiconductor processing methods of forming a conductive gate and line
US5714786A (en) * 1996-10-31 1998-02-03 Micron Technology, Inc. Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors
US5998256A (en) 1996-11-01 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
JP4056588B2 (ja) 1996-11-06 2008-03-05 富士通株式会社 半導体装置及びその製造方法
US5714412A (en) 1996-12-02 1998-02-03 Taiwan Semiconductor Manufacturing Company, Ltd Multi-level, split-gate, flash memory cell and method of manufacture thereof
KR19980064176A (ko) 1996-12-17 1998-10-07 윌리엄비.켐플러 집적 회로 유전체
JP4053647B2 (ja) 1997-02-27 2008-02-27 株式会社東芝 半導体記憶装置及びその製造方法
US5792690A (en) 1997-05-15 1998-08-11 Vanguard International Semiconductor Corporation Method of fabricating a DRAM cell with an area equal to four times the used minimum feature
US6337497B1 (en) 1997-05-16 2002-01-08 International Business Machines Corporation Common source transistor capacitor stack
US6054355A (en) 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
US6072209A (en) 1997-07-08 2000-06-06 Micro Technology, Inc. Four F2 folded bit line DRAM cell structure having buried bit and word lines
US6191470B1 (en) 1997-07-08 2001-02-20 Micron Technology, Inc. Semiconductor-on-insulator memory cell with buried word and body lines
US6150687A (en) 1997-07-08 2000-11-21 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
US5909618A (en) 1997-07-08 1999-06-01 Micron Technology, Inc. Method of making memory cell with vertical transistor and buried word and body lines
US5869359A (en) 1997-08-20 1999-02-09 Prabhakar; Venkatraman Process for forming silicon on insulator devices having elevated source and drain regions
US6380026B2 (en) 1997-08-22 2002-04-30 Micron Technology, Inc. Processing methods of forming integrated circuitry memory devices, methods of forming DRAM arrays, and related semiconductor masks
JP3502531B2 (ja) 1997-08-28 2004-03-02 株式会社ルネサステクノロジ 半導体装置の製造方法
DE19801095B4 (de) 1998-01-14 2007-12-13 Infineon Technologies Ag Leistungs-MOSFET
US5998835A (en) 1998-02-17 1999-12-07 International Business Machines Corporation High performance MOSFET device with raised source and drain
US5963469A (en) 1998-02-24 1999-10-05 Micron Technology, Inc. Vertical bipolar read access for low voltage memory cell
US6246083B1 (en) 1998-02-24 2001-06-12 Micron Technology, Inc. Vertical gain cell and array for a dynamic random access memory
US6097065A (en) 1998-03-30 2000-08-01 Micron Technology, Inc. Circuits and methods for dual-gated transistors
US6259142B1 (en) 1998-04-07 2001-07-10 Advanced Micro Devices, Inc. Multiple split gate semiconductor device and fabrication method
US6696746B1 (en) 1998-04-29 2004-02-24 Micron Technology, Inc. Buried conductors
US5972754A (en) 1998-06-10 1999-10-26 Mosel Vitelic, Inc. Method for fabricating MOSFET having increased effective gate length
US6767789B1 (en) 1998-06-26 2004-07-27 International Business Machines Corporation Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby
US6458925B1 (en) 1998-08-03 2002-10-01 University Of Maryland, Baltimore Peptide antagonists of zonulin and methods for use of the same
KR100304717B1 (ko) 1998-08-18 2001-11-15 김덕중 트렌치형게이트를갖는반도체장치및그제조방법
US6362506B1 (en) 1998-08-26 2002-03-26 Texas Instruments Incorporated Minimization-feasible word line structure for DRAM cell
JP3239109B2 (ja) 1998-08-28 2001-12-17 株式会社半導体理工学研究センター 強誘電体不揮発性メモリとその読み出し方法
JP4322330B2 (ja) 1998-09-04 2009-08-26 エルピーダメモリ株式会社 半導体集積回路装置の製造方法
US6225669B1 (en) 1998-09-30 2001-05-01 Advanced Micro Devices, Inc. Non-uniform gate/dielectric field effect transistor
DE19845003C1 (de) 1998-09-30 2000-02-10 Siemens Ag Vertikaler Feldeffekttransistor mit innenliegendem ringförmigen Gate und Herstellverfahren
US6120952A (en) 1998-10-01 2000-09-19 Micron Technology, Inc. Methods of reducing proximity effects in lithographic processes
US6114205A (en) 1998-10-30 2000-09-05 Sony Corporation Epitaxial channel vertical MOS transistor
EP1003219B1 (en) 1998-11-19 2011-12-28 Qimonda AG DRAM with stacked capacitor and buried word line
US5977579A (en) 1998-12-03 1999-11-02 Micron Technology, Inc. Trench dram cell with vertical device and buried word lines
JP2000208762A (ja) 1999-01-13 2000-07-28 Sony Corp 絶縁ゲ―ト電界効果トランジスタおよびその製造方法
US6383861B1 (en) 1999-02-18 2002-05-07 Micron Technology, Inc. Method of fabricating a dual gate dielectric
JP3973819B2 (ja) 1999-03-08 2007-09-12 株式会社東芝 半導体記憶装置およびその製造方法
US6180494B1 (en) 1999-03-11 2001-01-30 Micron Technology, Inc. Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines
KR100282452B1 (ko) 1999-03-18 2001-02-15 김영환 반도체 소자 및 그의 제조 방법
JP2001024161A (ja) * 1999-04-30 2001-01-26 Sony Corp 半導体メモリセル
US6297106B1 (en) 1999-05-07 2001-10-02 Chartered Semiconductor Manufacturing Ltd. Transistors with low overlap capacitance
US6306755B1 (en) 1999-05-14 2001-10-23 Koninklijke Philips Electronics N.V. (Kpenv) Method for endpoint detection during dry etch of submicron features in a semiconductor device
WO2000070622A1 (fr) 1999-05-14 2000-11-23 Hitachi, Ltd. Circuit de memorisation
DE19928781C1 (de) 1999-06-23 2000-07-06 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
US6392271B1 (en) 1999-06-28 2002-05-21 Intel Corporation Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
US6187643B1 (en) 1999-06-29 2001-02-13 Varian Semiconductor Equipment Associates, Inc. Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI)
US6114735A (en) 1999-07-02 2000-09-05 Micron Technology, Inc. Field effect transistors and method of forming field effect transistors
US6214670B1 (en) 1999-07-22 2001-04-10 Taiwan Semiconductor Manufacturing Company Method for manufacturing short-channel, metal-gate CMOS devices with superior hot carrier performance
US6630712B2 (en) 1999-08-11 2003-10-07 Advanced Micro Devices, Inc. Transistor with dynamic source/drain extensions
US6033963A (en) 1999-08-30 2000-03-07 Taiwan Semiconductor Manufacturing Company Method of forming a metal gate for CMOS devices using a replacement gate process
US6461915B1 (en) 1999-09-01 2002-10-08 Micron Technology, Inc. Method and structure for an improved floating gate memory cell
US6403442B1 (en) 1999-09-02 2002-06-11 Micron Technology, Inc. Methods of forming capacitors and resultant capacitor structures
DE19943760C1 (de) 1999-09-13 2001-02-01 Infineon Technologies Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
JP3450758B2 (ja) 1999-09-29 2003-09-29 株式会社東芝 電界効果トランジスタの製造方法
US6303518B1 (en) 1999-09-30 2001-10-16 Novellus Systems, Inc. Methods to improve chemical vapor deposited fluorosilicate glass (FSG) film adhesion to metal barrier or etch stop/diffusion barrier layers
US6255165B1 (en) 1999-10-18 2001-07-03 Advanced Micro Devices, Inc. Nitride plug to reduce gate edge lifting
TW432546B (en) 1999-11-25 2001-05-01 Taiwan Semiconductor Mfg Manufacturing method of copper damascene
US6383879B1 (en) 1999-12-03 2002-05-07 Agere Systems Guardian Corp. Semiconductor device having a metal gate with a work function compatible with a semiconductor device
US6323506B1 (en) 1999-12-21 2001-11-27 Philips Electronics North America Corporation Self-aligned silicon carbide LMOSFET
JP4860022B2 (ja) 2000-01-25 2012-01-25 エルピーダメモリ株式会社 半導体集積回路装置の製造方法
JP4363736B2 (ja) 2000-03-01 2009-11-11 新電元工業株式会社 トランジスタ及びその製造方法
US6686616B1 (en) 2000-05-10 2004-02-03 Cree, Inc. Silicon carbide metal-semiconductor field effect transistors
US6399490B1 (en) 2000-06-29 2002-06-04 International Business Machines Corporation Highly conformal titanium nitride deposition process for high aspect ratio structures
US6348387B1 (en) * 2000-07-10 2002-02-19 Advanced Micro Devices, Inc. Field effect transistor with electrically induced drain and source extensions
DE10036725C2 (de) 2000-07-27 2002-11-28 Infineon Technologies Ag Verfahren zur Herstellung einer porösen Isolierschicht mit niedriger Dielektrizitätskonstante auf einem Halbleitersubstrat
DE10038728A1 (de) 2000-07-31 2002-02-21 Infineon Technologies Ag Halbleiterspeicher-Zellenanordnung und Verfahren zu deren Herstellung
AU2001286895A1 (en) * 2000-08-29 2002-03-13 Boise State University Damascene double gated transistors and related manufacturing methods
US6495474B1 (en) 2000-09-11 2002-12-17 Agere Systems Inc. Method of fabricating a dielectric layer
US6391720B1 (en) 2000-09-27 2002-05-21 Chartered Semiconductor Manufacturing Ltd. Process flow for a performance enhanced MOSFET with self-aligned, recessed channel
US6340614B1 (en) 2000-10-03 2002-01-22 Vanguard International Semiconductor Corporation Method of forming a DRAM cell
JP2002151654A (ja) * 2000-11-10 2002-05-24 Sharp Corp 誘電体キャパシタ素子及びその製造方法
US6552401B1 (en) 2000-11-27 2003-04-22 Micron Technology Use of gate electrode workfunction to improve DRAM refresh
US6348385B1 (en) 2000-11-30 2002-02-19 Chartered Semiconductor Manufacturing Ltd. Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant
GB0029315D0 (en) * 2000-12-01 2001-01-17 Koninkl Philips Electronics Nv Method of increasing the conductivity of a transparent conductive layer
US6621112B2 (en) 2000-12-06 2003-09-16 Infineon Technologies Ag DRAM with vertical transistor and trench capacitor memory cells and methods of fabrication
JP4635333B2 (ja) 2000-12-14 2011-02-23 ソニー株式会社 半導体装置の製造方法
US6864536B2 (en) 2000-12-20 2005-03-08 Winbond Electronics Corporation Electrostatic discharge protection circuit
KR100360414B1 (ko) 2001-01-05 2002-11-13 삼성전자 주식회사 트윈 비트 결함을 방지하는 실린더형 커패시터의 하부전극형성방법
US6300177B1 (en) 2001-01-25 2001-10-09 Chartered Semiconductor Manufacturing Inc. Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials
JP3944367B2 (ja) 2001-02-06 2007-07-11 松下電器産業株式会社 絶縁膜の形成方法及び半導体装置の製造方法
KR100388682B1 (ko) 2001-03-03 2003-06-25 삼성전자주식회사 반도체 메모리 장치의 스토리지 전극층 및 그 형성방법
US6759707B2 (en) 2001-03-08 2004-07-06 Micron Technology, Inc. 2F2 memory device system
DE10111755C1 (de) 2001-03-12 2002-05-16 Infineon Technologies Ag Verfahren zur Herstellung einer Speicherzelle eines Halbleiterspeichers
CA2340985A1 (en) 2001-03-14 2002-09-14 Atmos Corporation Interleaved wordline architecture
US6734510B2 (en) * 2001-03-15 2004-05-11 Micron Technology, Ing. Technique to mitigate short channel effects with vertical gate transistor with different gate materials
JP4895430B2 (ja) 2001-03-22 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP3671854B2 (ja) 2001-04-05 2005-07-13 松下電器産業株式会社 シリコン系基板の表面処理方法
JP2002314072A (ja) 2001-04-19 2002-10-25 Nec Corp 高誘電体薄膜を備えた半導体装置及びその製造方法並びに誘電体膜の成膜装置
EP1253634A3 (en) * 2001-04-26 2005-08-31 Kabushiki Kaisha Toshiba Semiconductor device
US6498062B2 (en) 2001-04-27 2002-12-24 Micron Technology, Inc. DRAM access transistor
US6509612B2 (en) 2001-05-04 2003-01-21 International Business Machines Corporation High dielectric constant materials as gate dielectrics (insulators)
US6624486B2 (en) 2001-05-23 2003-09-23 International Business Machines Corporation Method for low topography semiconductor device formation
DE10125967C1 (de) 2001-05-29 2002-07-11 Infineon Technologies Ag DRAM-Zellanordnung mit vertikalen MOS-Transistoren und Verfahren zu deren Herstellung
JP2002353445A (ja) 2001-05-30 2002-12-06 Sony Corp 溝ゲート型電界効果トランジスタの製造方法
US6888198B1 (en) * 2001-06-04 2005-05-03 Advanced Micro Devices, Inc. Straddled gate FDSOI device
TWI230392B (en) * 2001-06-18 2005-04-01 Innovative Silicon Sa Semiconductor device
JP4246929B2 (ja) 2001-06-29 2009-04-02 株式会社東芝 半導体記憶装置およびその製造方法
JP2003023150A (ja) 2001-07-10 2003-01-24 Sony Corp トレンチゲート型半導体装置及びその作製方法
KR100398955B1 (ko) 2001-08-02 2003-09-19 삼성전자주식회사 이이피롬 메모리 셀 및 형성 방법
DE10139827A1 (de) 2001-08-14 2003-03-13 Infineon Technologies Ag Speicherzelle mit Grabenkondensator und vertikalem Auswahltransistor und einem zwischen diesen geformten ringförmigen Kontaktierungsbereich
US6800899B2 (en) 2001-08-30 2004-10-05 Micron Technology, Inc. Vertical transistors, electrical devices containing a vertical transistor, and computer systems containing a vertical transistor
KR100431656B1 (ko) 2001-09-11 2004-05-17 삼성전자주식회사 반도체 장치의 제조 방법
JP2003092367A (ja) 2001-09-19 2003-03-28 Oki Electric Ind Co Ltd 半導体素子の製造方法
US6825093B2 (en) 2001-09-28 2004-11-30 Infineon Technologies Ag Process window enhancement for deep trench spacer conservation
KR100400323B1 (ko) 2001-11-01 2003-10-01 주식회사 하이닉스반도체 반도체 소자의 시모스(ｃｍｏｓ) 및 그의 제조 방법
KR100436287B1 (ko) * 2001-11-17 2004-06-16 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 및 그 제조 방법
US6724028B2 (en) 2001-12-10 2004-04-20 Hans Gude Gudesen Matrix-addressable array of integrated transistor/memory structures
US6630720B1 (en) 2001-12-26 2003-10-07 Advanced Micro Devices, Inc. Asymmetric semiconductor device having dual work function gate and method of fabrication
US6563183B1 (en) 2001-12-31 2003-05-13 Advanced Micro Devices, Inc. Gate array with multiple dielectric properties and method for forming same
US6858500B2 (en) 2002-01-16 2005-02-22 Fuji Electric Co., Ltd. Semiconductor device and its manufacturing method
US6656748B2 (en) 2002-01-31 2003-12-02 Texas Instruments Incorporated FeRAM capacitor post stack etch clean/repair
DE10208249B4 (de) 2002-02-26 2006-09-14 Infineon Technologies Ag Halbleiterspeicher mit vertikalem Auswahltransistor
US6515325B1 (en) 2002-03-06 2003-02-04 Micron Technology, Inc. Nanotube semiconductor devices and methods for making the same
US6661042B2 (en) * 2002-03-11 2003-12-09 Monolithic System Technology, Inc. One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
US6586808B1 (en) 2002-06-06 2003-07-01 Advanced Micro Devices, Inc. Semiconductor device having multi-work function gate electrode and multi-segment gate dielectric
US6946371B2 (en) 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
DE10226583B4 (de) 2002-06-14 2010-07-08 Qimonda Ag DRAM-Speicherzelle für schnellen Schreib-/Lesezugriff und Speicherzellenfeld
US6756625B2 (en) 2002-06-21 2004-06-29 Micron Technology, Inc. Memory cell and method for forming the same
US7221596B2 (en) 2002-07-05 2007-05-22 Impinj, Inc. pFET nonvolatile memory
JP3934507B2 (ja) 2002-08-08 2007-06-20 株式会社東芝 半導体記憶装置および半導体記憶装置の製造方法
US6914289B2 (en) 2002-08-15 2005-07-05 Intel Corporation Hourglass ram
US7071043B2 (en) 2002-08-15 2006-07-04 Micron Technology, Inc. Methods of forming a field effect transistor having source/drain material over insulative material
US20040034587A1 (en) 2002-08-19 2004-02-19 Amberson Matthew Gilbert System and method for calculating intra-period volatility
US6838723B2 (en) 2002-08-29 2005-01-04 Micron Technology, Inc. Merged MOS-bipolar capacitor memory cell
US6818947B2 (en) 2002-09-19 2004-11-16 Fairchild Semiconductor Corporation Buried gate-field termination structure
US6645869B1 (en) 2002-09-26 2003-11-11 Vanguard International Semiconductor Corporation Etching back process to improve topographic planarization of a polysilicon layer
US7033891B2 (en) 2002-10-03 2006-04-25 Fairchild Semiconductor Corporation Trench gate laterally diffused MOSFET devices and methods for making such devices
US6753228B2 (en) 2002-10-15 2004-06-22 Semiconductor Components Industries, L.L.C. Method of forming a low resistance semiconductor device and structure therefor
TW588413B (en) 2002-11-07 2004-05-21 Winbond Electronics Corp Manufacturing method and device of memory with different depths of isolation trench
US6861689B2 (en) * 2002-11-08 2005-03-01 Freescale Semiconductor, Inc. One transistor DRAM cell structure and method for forming
KR100481867B1 (ko) 2002-11-11 2005-04-11 삼성전자주식회사 강유전체 커패시터 및 그 제조 방법
US6645818B1 (en) 2002-11-13 2003-11-11 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dual-metal gate for N- and P-FETs
US7250650B2 (en) 2002-11-21 2007-07-31 Infineon Technologies Ag Field-effect transistor structure and associated semiconductor memory cell
US7030436B2 (en) * 2002-12-04 2006-04-18 Micron Technology, Inc. Embedded DRAM gain memory cell having MOS transistor body provided with a bi-polar transistor charge injecting means
KR100521369B1 (ko) 2002-12-18 2005-10-12 삼성전자주식회사 고속도 및 저전력 소모 반도체 소자 및 그 제조 방법
TW574746B (en) 2002-12-19 2004-02-01 Taiwan Semiconductor Mfg Method for manufacturing MOSFET with recessed channel
TWI231042B (en) 2002-12-27 2005-04-11 Wintek Corp Method and device to promote the yield rate and uniformity of AMOLED panel
KR20040061967A (ko) 2002-12-31 2004-07-07 동부전자 주식회사 반도체 소자의 제조방법
TW578274B (en) 2003-01-17 2004-03-01 Nanya Technology Corp Vertical flash memory cell with tip-shape floating gate and method therefor
JP4502173B2 (ja) 2003-02-03 2010-07-14 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2004247656A (ja) 2003-02-17 2004-09-02 Renesas Technology Corp 半導体装置及びその製造方法
US6956256B2 (en) 2003-03-04 2005-10-18 Micron Technology Inc. Vertical gain cell
JP2004281736A (ja) 2003-03-17 2004-10-07 Nec Electronics Corp 半導体記憶装置
TW578328B (en) 2003-03-28 2004-03-01 Gemtek Technology Co Ltd Dual-frequency inverted-F antenna
KR100480645B1 (ko) * 2003-04-01 2005-03-31 삼성전자주식회사 역자기 정합 방식을 이용한 트윈―ｏｎｏ 형태의ｓｏｎｏｓ 메모리 소자 제조 방법
US6720232B1 (en) 2003-04-10 2004-04-13 Taiwan Semiconductor Manufacturing Company Method of fabricating an embedded DRAM for metal-insulator-metal (MIM) capacitor structure
US6967143B2 (en) * 2003-04-30 2005-11-22 Freescale Semiconductor, Inc. Semiconductor fabrication process with asymmetrical conductive spacers
TW587338B (en) 2003-05-06 2004-05-11 Mosel Vitelic Inc Stop structure of trench type DMOS device and its formation method
JP2004335031A (ja) * 2003-05-09 2004-11-25 Toshiba Corp 半導体記憶装置
JP3913709B2 (ja) * 2003-05-09 2007-05-09 株式会社東芝 半導体記憶装置
KR100568854B1 (ko) 2003-06-17 2006-04-10 삼성전자주식회사 반도체 메모리에서의 리세스 채널을 갖는 트랜지스터 형성방법
US7105406B2 (en) 2003-06-20 2006-09-12 Sandisk Corporation Self aligned non-volatile memory cell and process for fabrication
US6818515B1 (en) 2003-06-23 2004-11-16 Promos Technologies Inc. Method for fabricating semiconductor device with loop line pattern structure
KR100521381B1 (ko) 2003-06-25 2005-10-12 삼성전자주식회사 모오스 전계 효과 트랜지스터의 제조 방법
KR100511045B1 (ko) 2003-07-14 2005-08-30 삼성전자주식회사 리세스된 게이트 전극을 갖는 반도체 소자의 집적방법
US7335934B2 (en) * 2003-07-22 2008-02-26 Innovative Silicon S.A. Integrated circuit device, and method of fabricating same
US7326619B2 (en) 2003-08-20 2008-02-05 Samsung Electronics Co., Ltd. Method of manufacturing integrated circuit device including recessed channel transistor
US6784069B1 (en) 2003-08-29 2004-08-31 Micron Technology, Inc. Permeable capacitor electrode
US7125781B2 (en) 2003-09-04 2006-10-24 Micron Technology, Inc. Methods of forming capacitor devices
US7067385B2 (en) 2003-09-04 2006-06-27 Micron Technology, Inc. Support for vertically oriented capacitors during the formation of a semiconductor device
KR100546378B1 (ko) 2003-09-09 2006-01-26 삼성전자주식회사 리세스 채널을 가지는 트랜지스터 제조 방법
US6844591B1 (en) 2003-09-17 2005-01-18 Micron Technology, Inc. Method of forming DRAM access transistors
JP2005093808A (ja) 2003-09-18 2005-04-07 Fujio Masuoka メモリセルユニット、それを備えてなる不揮発性半導体記憶装置及びメモリセルアレイの駆動方法
US7184298B2 (en) * 2003-09-24 2007-02-27 Innovative Silicon S.A. Low power programming technique for a floating body memory transistor, memory cell, and memory array
US7468311B2 (en) 2003-09-30 2008-12-23 Tokyo Electron Limited Deposition of silicon-containing films from hexachlorodisilane
JP2005142203A (ja) 2003-11-04 2005-06-02 Elpida Memory Inc 半導体装置およびその製造方法
US20050104156A1 (en) 2003-11-13 2005-05-19 Texas Instruments Incorporated Forming a semiconductor structure in manufacturing a semiconductor device using one or more epitaxial growth processes
KR100521383B1 (ko) 2003-11-17 2005-10-12 삼성전자주식회사 소자분리막 상에 형성된 소오스/드레인을 갖는 반도체소자 및 그 제조방법
JP2005175090A (ja) 2003-12-09 2005-06-30 Toshiba Corp 半導体メモリ装置及びその製造方法
KR100518606B1 (ko) 2003-12-19 2005-10-04 삼성전자주식회사 실리콘 기판과 식각 선택비가 큰 마스크층을 이용한리세스 채널 어레이 트랜지스터의 제조 방법
JP4342970B2 (ja) * 2004-02-02 2009-10-14 株式会社東芝 半導体メモリ装置及びその製造方法
US6974743B2 (en) 2004-02-02 2005-12-13 Infineon Technologies Ag Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates
KR100540371B1 (ko) 2004-03-02 2006-01-11 이태복 고 내압용 반도체 소자 및 그 제조방법
US7262089B2 (en) 2004-03-11 2007-08-28 Micron Technology, Inc. Methods of forming semiconductor structures
KR100614240B1 (ko) 2004-06-10 2006-08-18 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 형성방법
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7160788B2 (en) 2004-08-23 2007-01-09 Micron Technology, Inc. Methods of forming integrated circuits
US7122425B2 (en) 2004-08-24 2006-10-17 Micron Technology, Inc. Methods of forming semiconductor constructions
US7202127B2 (en) 2004-08-27 2007-04-10 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7151040B2 (en) 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7547945B2 (en) 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7442976B2 (en) 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7285812B2 (en) 2004-09-02 2007-10-23 Micron Technology, Inc. Vertical transistors
US7115525B2 (en) 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
JP4083160B2 (ja) * 2004-10-04 2008-04-30 株式会社東芝 半導体記憶装置およびｆｂｃメモリセルの駆動方法
US20060108667A1 (en) 2004-11-22 2006-05-25 Macronix International Co., Ltd. Method for manufacturing a small pin on integrated circuits or other devices
US20060113588A1 (en) 2004-11-29 2006-06-01 Sillicon-Based Technology Corp. Self-aligned trench-type DMOS transistor structure and its manufacturing methods
KR100640616B1 (ko) 2004-12-21 2006-11-01 삼성전자주식회사 매몰 게이트 패턴을 포함하는 전계 효과 트랜지스터구조물 및 그것을 포함하는 반도체 소자의 제조방법
JP2006234780A (ja) 2005-01-25 2006-09-07 Fujitsu Component Ltd 評価基板及びケーブルアッセンブリ評価方法
US20060167741A1 (en) 2005-01-25 2006-07-27 Cisco Technology, Inc. System and method for designing a supply chain
DE102005008478B3 (de) 2005-02-24 2006-10-26 Infineon Technologies Ag Verfahren zur Herstellung von sublithographischen Strukturen
JP2006237455A (ja) * 2005-02-28 2006-09-07 Toshiba Corp 半導体装置とその製造方法
US7244659B2 (en) 2005-03-10 2007-07-17 Micron Technology, Inc. Integrated circuits and methods of forming a field effect transistor
US7390746B2 (en) 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7253118B2 (en) 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7384849B2 (en) 2005-03-25 2008-06-10 Micron Technology, Inc. Methods of forming recessed access devices associated with semiconductor constructions
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
JP4541220B2 (ja) 2005-04-13 2010-09-08 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
US7214621B2 (en) 2005-05-18 2007-05-08 Micron Technology, Inc. Methods of forming devices associated with semiconductor constructions
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7176084B2 (en) * 2005-06-09 2007-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory
US7396781B2 (en) 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
JP2006352005A (ja) 2005-06-20 2006-12-28 Toshiba Corp 強誘電体記憶装置およびその製造方法
US7517741B2 (en) * 2005-06-30 2009-04-14 Freescale Semiconductor, Inc. Single transistor memory cell with reduced recombination rates
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7413981B2 (en) 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US7199005B2 (en) 2005-08-02 2007-04-03 Micron Technology, Inc. Methods of forming pluralities of capacitors
DE102005040133A1 (de) 2005-08-03 2007-02-08 Amazonen-Werke H. Dreyer Gmbh & Co. Kg Grubber
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7687342B2 (en) 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7867845B2 (en) 2005-09-01 2011-01-11 Micron Technology, Inc. Transistor gate forming methods and transistor structures
JP4773182B2 (ja) 2005-10-28 2011-09-14 エルピーダメモリ株式会社 半導体装置の製造方法
US7350441B2 (en) 2005-11-15 2008-04-01 3M Innovative Properties Company Cutting tool having variable movement at two simultaneously independent speeds in an x-direction into a work piece for making microstructures
KR100843139B1 (ko) 2005-12-15 2008-07-02 삼성전자주식회사 오픈 비트 라인 구조를 갖는 멀티레벨 동적 메모리 장치 및그 구동 방법
US7495294B2 (en) 2005-12-21 2009-02-24 Sandisk Corporation Flash devices with shared word lines
TWI293207B (en) * 2006-01-11 2008-02-01 Promos Technologies Inc Dynamic random access memory structure and method for preparing the smae
US7700441B2 (en) 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7495946B2 (en) 2006-03-02 2009-02-24 Infineon Technologies Ag Phase change memory fabricated using self-aligned processing
US7476933B2 (en) 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7349232B2 (en) 2006-03-15 2008-03-25 Micron Technology, Inc. 6F2 DRAM cell design with 3F-pitch folded digitline sense amplifier
US7351666B2 (en) 2006-03-17 2008-04-01 International Business Machines Corporation Layout and process to contact sub-lithographic structures
US7902074B2 (en) 2006-04-07 2011-03-08 Micron Technology, Inc. Simplified pitch doubling process flow
US8003310B2 (en) 2006-04-24 2011-08-23 Micron Technology, Inc. Masking techniques and templates for dense semiconductor fabrication
US7488685B2 (en) 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
JP2008004738A (ja) 2006-06-22 2008-01-10 Elpida Memory Inc 半導体装置及びその製造方法
US7602001B2 (en) 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7755132B2 (en) 2006-08-16 2010-07-13 Sandisk Corporation Nonvolatile memories with shaped floating gates
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7589995B2 (en) 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
US7494870B2 (en) 2007-01-12 2009-02-24 Sandisk Corporation Methods of forming NAND memory with virtual channel
US7732275B2 (en) 2007-03-29 2010-06-08 Sandisk Corporation Methods of forming NAND flash memory with fixed charge
US7619311B2 (en) 2007-02-02 2009-11-17 Macronix International Co., Ltd. Memory cell device with coplanar electrode surface and method
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8563229B2 (en) 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US7684245B2 (en) 2007-10-30 2010-03-23 Atmel Corporation Non-volatile memory array architecture with joined word lines
KR101374323B1 (ko) 2008-01-07 2014-03-17 삼성전자주식회사 반도체 소자 및 그 제조방법
US7759193B2 (en) 2008-07-09 2010-07-20 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8859367B2 (en) 2010-07-09 2014-10-14 Micron Technology, Inc. Gate constructions of recessed access devices and methods of forming gate constructions of recessed access devices

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