TW201633457A - 用於熱傳導的接合孔陣列 - Google Patents
用於熱傳導的接合孔陣列 Download PDFInfo
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Abstract
於微電子裝置,基板具有第一上和下表面。積體電路晶粒具有第二上和下表面。互連將基板的第一上表面耦合於積體電路晶粒的第二下表面以在其間做電通訊。孔陣列具有其接線的近端,其耦合於第二上表面以將熱傳導離開積體電路晶粒。模製材料配置於孔陣列中,而孔陣列之接線的遠端至少延伸到模製材料的較高表面。
Description
以下敘述關於微電子裝置。更特別而言,以下敘述有關用於將熱傳導離開微電子裝置之積體電路晶粒的孔陣列。
某些積體電路晶粒當操作時可以具有熱點,以及/或者當操作時可以比其他積體電路晶粒丟出更多的熱。對於某些微電子組件而言,由於放置在晶粒堆疊旁邊和/或能夠鎖定熱點而將熱由此傳導離開,或者由於晶粒放置在一般而言是不良熱導體的包封模製化合物裡,故將熱傳導離開此種積體電路晶粒可以是有問題的。
據此,提供用於積體電路晶粒的熱傳導而緩和或克服一或更多個上述限制則會是想要的和有用的。
設備一般而言關於微電子裝置。於此種設備,基板具有第一上表面和第一下表面。積體電路晶粒具有第二上表面和第二下表面。互連將基板的第一上表面耦合於積體電路晶粒的第二下表面以在其間做電通訊。孔陣列具有其接線的近端,其耦合於第二上表面以將熱傳導離開積體電路晶粒。模製材料配置於孔陣列中,而孔陣列之接線的遠端至少延伸到模製材料的較高表面。
設備一般而言關於另一微電子裝置。於此種設備,封裝基板具有第一上表面和第一下表面。插置物基板具有第二上表面和第二下表面。第一互連將第二下表面和第一上表面彼此耦合。積體電路晶粒具有第三上表面和第三下表面。第二互連將第二上表面和第三下表面彼此耦合。晶粒堆疊耦合於插置物基板,其中晶粒堆疊具有高於第三上表面的第四上表面。孔陣列具有其接線的近端,其耦合於第三上表面以將熱傳導離開積體電路晶粒。模製材料配置於孔陣列中,而孔陣列之接線的遠端至少延伸到模製材料的較高表面並且高於晶粒堆疊的第四上表面。
方法一般而言關於微電子裝置的形成。於此種方法,獲得基板,其具有第一上表面和第一下表面。獲得積體電路晶粒,其具有第二上表面和第二下表面。基板的第一上表面藉由互連而互連到積體電路晶粒的第二下表面以在其間做電傳導。形成孔陣列,其具有其接線的近端而耦合於第二上表面,以將熱傳導離開積體電路晶粒。模製材料沉積於孔陣列中,而孔陣列之接線的遠端至少延伸到模製材料的較高表面。
10、10-1~10-4‧‧‧積體電路(IC)
18‧‧‧孔結構
40‧‧‧插置物、插置晶粒、插置基板
41‧‧‧封裝基板
42‧‧‧導熱材料
43‧‧‧散熱器
44‧‧‧陣列互連
47‧‧‧接線
50‧‧‧三維(3D)IC封裝構件
52‧‧‧微凸塊
53‧‧‧凸塊或焊球
54‧‧‧底填物
100‧‧‧微電子裝置
101‧‧‧第一下表面
102‧‧‧第一上表面
110‧‧‧模製材料
111‧‧‧第二下表面
112‧‧‧第二上表面
120、121、122‧‧‧孔陣列
123、124‧‧‧接線
125‧‧‧打線接合
127‧‧‧近端
128‧‧‧遠端
132‧‧‧鈍化層
133‧‧‧金屬化層
141‧‧‧較上或較高的表面
142‧‧‧下表面
320‧‧‧襯墊
321‧‧‧接線或打線接合
322‧‧‧整個金屬層
401‧‧‧熱點區域
501‧‧‧晶粒堆疊
511‧‧‧第二下表面
512‧‧‧第二上表面
521‧‧‧第四上表面
522‧‧‧第四下表面
550‧‧‧孔陣列
600‧‧‧形成微電子裝置的過程
601~612‧‧‧形成微電子裝置的過程步驟
伴隨的(多個)圖式顯示依據(多個)範例性設備或方法之一或更多個方面的(多個)範例性具體態樣。然而,伴隨圖式不應拿來限制請求項的範圍,而祇是用來解釋和了解。
圖1是顯示具有孔結構之範例性三維積體電路(three-dimensional integrated circuit,3D IC)封裝構件的截面方塊圖。
圖2是顯示具有孔結構之另一範例性3D IC封裝構件的截面方塊圖。
圖3-1是顯示範例性微電子裝置的截面方塊圖。
圖3-2是顯示另一範例性微電子裝置的截面方塊圖。
圖4是圖3-1之孔陣列的俯視圖。
圖5是顯示另一範例性微電子裝置的截面方塊圖,其在此範例是3D IC封裝構件。
圖6是顯示形成例如圖3-1、3-2或5的微電子裝置之範例性過程的流程圖。
圖7是顯示另一範例性微電子裝置的截面方塊圖,其在此範例是3D IC封裝構件,而具有配置在晶粒堆疊上之可選用的孔陣列。
於以下敘述,列出了許多特定的細節以提供對在此所述之特定範例的更徹底敘述。然而,熟於此技藝者應該明白可以在沒有底下所給的所有特定細節下來實施一或更多個其他範例或這些範例的變化。於其他例子,並未詳細描述熟知的特色,如此以免模糊了在此範例的敘述。為了容易示範,相同的數字標記用於不同的圖中以指稱相同的項目;然而,在替代性範例中,項目可以有所不同。
微電子組件一般而言包括一或更多個IC,舉例而言例如一或更多個封裝晶粒(晶片)或一或更多個晶粒。一或更多個此種IC可以安裝在電路平臺上,例如晶圓(例如在晶圓層級封裝(wafer-level-packaging,WLP))、印刷板(printed board,PB)、印刷接線板(printed wiring board,PWB)、印刷電路板(printed circuit board,PCB)、印刷接線組件(printed wiring assembly,PWA)、印刷電路組件(printed circuit assembly,PCA)、封裝基板、
插置物或晶片載體。附帶而言,一IC可以安裝在另一IC上。
基板可以包括上表面和下表面,其在側向上延伸並且在此種基板的厚度上彼此大致平行。使用例如「上」(upper)和「下」(lower)或其他方向性詞彙乃相對於圖形的參考框架,並且不是意謂對於可能的替代性指向(例如在進一步的組件中或如用於多樣的系統中)加以限制。
基板可以具有鈍化層級。焊料凸塊或打線接合可以習用而言耦合於透過此種鈍化層級所暴露的接合襯墊。鈍化層可以是聚合物層。舉例而言,鈍化層可以是苯并環丁烯(BCB)層或氮化矽層和BCB層的組合。於某些應用,鈍化層可以稱為晶粒間層。
金屬層(例如銅、銅合金或其他金屬)可以形成在鈍化層上和在下端接觸表面上。球可以分別形成在接合襯墊上,其中此種襯墊可以形成在此種金屬層上或作為其一部分。球可以由接合材料所形成,例如焊料或其他接合材料。球可以是微凸塊、C4凸塊、球柵陣列(ball grid array,BGA)球或某種其他的晶粒互連結構。於某些應用,金屬層可以稱為著地襯墊。
近來而言,已經形成了三維(3D)IC或「3D IC」。一般而言,將晶粒附接到另一晶粒可以在接合襯墊層級或晶片上的電接線層級下進行。IC可以從晶圓切成單一晶粒。此種單一晶粒可以彼此接合或接合到電路平臺。為了清楚而藉由舉例但非限制,將假設插置物用於此種電路平臺。
以上述銘記在心而言,圖1是顯示具有孔結構18之範例性3D IC封裝構件50的截面方塊圖。雖然堆疊晶粒或堆疊封裝晶粒可以包括穿矽通孔(TSV)互連,不過為了清楚和藉由舉例而描述孔結構18以用於3D IC封裝構件50。於3D IC封裝構件50的這範例,有三個IC 10,亦即IC 10-1、
10-2、10-3,其堆疊在彼此上。於其他實施例,堆疊中可以有少於或多於三個IC 10。IC 10可以使用微凸塊52或覆晶焊料凸塊而彼此接合。可選用而言,可以使用從晶粒背面延伸的Cu柱。某些微凸塊52可以互連到孔結構18。舉例而言,可以使用Cu/Sn微凸塊瞬間液相(transient liquid phase,TLP)接合科技來將IC彼此接合。因此,互連層可以是在3D堆疊之IC 10的上側上、下側上或上和下側二者上。
此種3D堆疊IC的下方IC 10-3可選用而言可以耦合於插置物或插置晶粒40。插置物40可以是主動晶粒或被動晶粒。為了清楚而無限制,將假設插置物40是被動晶粒。IC 10-3可以藉由微凸塊52而耦合於插置物40。插置物40可以耦合於封裝基板41。封裝基板41可以由稱為層合物或層合基板的薄層所形成。層合物可以是有機或無機的。用於「堅硬」封裝基板的材料範例包括基於環氧樹脂的層合物(例如FR4)、基於樹脂的層合物(例如雙馬來醯亞胺三肼(BT))、陶瓷基板、玻璃基板或其他形式的封裝基板。用於覆晶附接的底填物54可以包封用於耦合插置物40和封裝基板41的C4凸塊或其他焊球53。
分散器/散熱器(heat sink)43可以附接到封裝基板41,並且此種散熱器43和封裝基板41組合起來可以包住此種3D堆疊的IC 10和插置物40。熱膏、熱介面材料(thermal interface material,TIM)或其他導熱材料42可以將此種3D堆疊頂部上之IC 10-1的上表面耦合於此種散熱器43的內部上表面。球柵陣列(BGA)球或其他陣列互連44可以用於將封裝基板41耦合於電路平臺(舉例而言例如PCB)。
圖2是顯示具有孔結構18之另一範例性3D IC封裝構件50
的截面方塊圖。圖1和2的3D IC封裝構件50是相同的,例外之處在於以下差異;於圖2,另一IC 10-4經由微凸塊52而分開耦合於插置物40,其中IC 10-4沒有耦合於IC 10-1、10-2、10-3的堆疊。再者,插置物40包括金屬和孔層以提供接線47來將IC 10-3和10-4互連。再者,插置物40包括孔結構18,其經由微凸塊52而耦合於IC 10-4。
3D晶圓層級封裝(3D-WLP)可以用於將二或更多個IC互連、將一或更多個IC互連到插置物、或其任何組合,其中該等互連可以使用孔結構18。可選用而言,IC可以是晶粒對晶粒(die-to-die,D2D)、堆疊封裝(package-on-package,PoP)或晶片對晶片(chip-to-chip,C2C)的互連,其中該等互連可以使用孔結構18。此外,可選用而言,IC可以是晶粒對晶圓(die-to-wafer,D2W)或晶片對晶圓(chip-to-wafer,C2W)的互連,其中該等互連可以使用孔結構18。據此,可以使用各式各樣任何的晶粒堆疊或晶片堆疊做法來提供3D堆疊IC(3D-SIC或3D-IC)。一或更多個晶粒可以用於提供單封裝系統(system-in-a-package,SiP)。
圖3-1是顯示範例性微電子裝置100的截面方塊圖。微電子裝置100包括基板,例如封裝基板41,其具有第一上表面102和第一下表面101。微電子裝置100包括積體電路晶粒10,其具有第二上表面112和第二下表面111。於此組態,積體電路晶粒10可以具有面朝下的指向。
微電子裝置100包括互連,例如微凸塊52或焊球53,其將封裝基板41的第一上表面102耦合於積體電路晶粒10的第二下表面111以供電傳導。在使用模製材料110之前,可以使用底填物54以在表面102和111之間包封微凸塊52或焊球53。
在沉積模製材料110之前,可以先形成孔陣列120。孔陣列120可以是Bond Via ArrayTM或其他陣列而具有隔開的接線123和124。接線123和124的近端127可以耦合於第二上表面112,以將熱傳導離開積體電路晶粒10。於積體電路晶粒10是面朝上而非如本範例面朝下的組態,可選用而言,接線123和124可以耦合於此種面朝上的正面。然而,更可能的是打算在背面上具有用於耦合接線123和124而因此用於熱逸散的空間。據此,在此描述的是面朝下的正面指向。以近端127來說,此種末端相較於此種接線123和124的遠端128而言乃靠近積體電路晶粒10。接線123和124的近端127可以軟焊或另外接合到上表面112,而接合或軟焊材料則形成打線接合125。舉例而言,可以使用電子焰斷(electronic flame-off,EFO)所誘發的球接合過程。
於此範例,可選用的鈍化層132可以沉積或另外配置在積體電路晶粒10的第二上表面112上。金屬化層133可以沉積在積體電路晶粒10的第二上表面112上方(包括在上面)。對於具有可選用之鈍化層132的組態來說,金屬化層133可以沉積或另外配置在鈍化層132上。金屬化層133可以用於打線接合125以將孔陣列120之接線123和124的近端127耦合於第二上表面112,而將熱傳導離開積體電路晶粒10。據此,積體電路晶粒10的第二上表面112可以是背面而用於面朝下的積體電路晶粒10。
圖3-2是顯示另一範例性微電子裝置100的截面方塊圖。圖3-2的微電子裝置100可以相同於圖3-1的微電子裝置100,而具有接線或打線接合321以及具有或沒有微凸塊52或焊球53,如先前所述。於沒有如先前所述之微凸塊52或焊球53的組態,積體電路晶粒10可以具有面朝上的
指向。然而,隨著積體電路晶粒10的電路變得更緻密,更加強調輸入/輸出接觸,所以積體電路10之例如用於微凸塊52或焊球53的面朝下指向可以提供此種輸入/輸出接觸。沿著那些線,打線接合321可以用於額外傳導熱離開積體電路晶粒10。打線接合321可以分別耦合於襯墊320,而在打線接合的第一末端可以形成為金屬化層133的一部分。打線接合321的第二末端可以耦合於整個金屬層322,其形成於基板41中而延伸到或暴露於第一上表面102,以供打線接合321的此種第二末端對它連接以供額外熱傳導。此種整個金屬層322可以額外使用作為接地平面。
為了清楚而藉由舉例但非限制,在此進一步描述圖3-1的微電子裝置100;然而,以下敘述可以類似應用於圖3-2的微電子裝置100。
在形成孔陣列120之後,模製材料110可以沉積或另外配置於孔陣列120中,而孔陣列120之接線123和124的遠端128至少延伸到模製材料110之較上或較高的表面141(包括與之等高和/或在其上方)。熱膏、TIM或其他導熱黏著劑(熱膏)42可以沉積或另外配置在上表面141上以接觸接線123和124的遠端128。散熱器43的下表面142可以放置成接觸熱膏42。此外,可選用而言,部分的遠端128可以放置成接觸散熱器43的下表面142以熱耦合接線124(可選用而言以及接線123)的遠端128和散熱器43。換言之,熱膏42可以用於將接線123和124耦合於散熱器43以供熱傳導。散熱器43可以配置在接線123和124的遠端128上方,並且此種散熱器43可以在組裝期間往下推以形成對此種遠端128的接觸,因為外面有角度的接線124是可彎曲的。
沿著上述的線,圖4是圖3-1之孔陣列121和122的俯視圖。
同時參考圖3-1和4來進一步描述微電子裝置100。
孔陣列120之接線123和124的近端127可以是分別用於分開的孔陣列121和122。沿著那些線,接線123的近端127可以是孔陣列121的,並且接線124的近端127可以是孔陣列122的。孔陣列121可以是在孔陣列122的內部。據此,孔陣列121和122之接線123和124的近端127可以分別耦合於第二上表面112,以在不同的速率下將熱傳導離開積體電路晶粒10。沿著那些線,孔陣列121可以比孔陣列122還密,亦即區域裡有更多的接線123。孔陣列121可以比孔陣列122還密,因為孔陣列121可以配置在熱點上,其大致指示成積體電路晶粒10的區域401。
孔陣列122之接線124的遠端128可以比孔陣列121之接線123的遠端128分散得更寬廣。接線123的遠端128可以不直接接觸下表面142,而接線124的遠端128可以直接接觸散熱器43的下表面142。
圖5是顯示另一範例性微電子裝置100的截面方塊圖,其在此範例是3D IC封裝構件。微電子裝置100包括封裝基板41、插置基板40、用於互連的焊球53、積體電路晶粒10、排除積體電路晶粒10的積體電路晶粒堆疊(晶粒堆疊)501、作為其他互連的微凸塊52、孔陣列120、模製材料110、散熱器43、熱膏42。
封裝基板41具有第一上表面102和第一下表面101。插置基板40具有第二上表面512和第二下表面511。焊球53可以將第二下表面511和第一上表面102彼此耦合。積體電路晶粒10具有第三上表面112和第三下表面111。微凸塊52可以將第二上表面512和第三下表面111彼此耦合。
晶粒堆疊501可以實際上具有第四上表面521和第四下表面
522。微凸塊52可以將第二上表面512和第四下表面522彼此耦合。第四上表面521可以實質高於積體電路晶粒10的第三上表面112,雖然沒有在它的正上方。
可選用而言,接線123的孔陣列550可以形成在上表面521上,如圖7示例所示,該圖是顯示圖5之範例性微電子裝置100的截面方塊圖,雖然添加了孔陣列550。孔陣列550可以如先前參考孔陣列121所述的來形成。此外,可選用而言,對於低熱逸散應用來說,可以省略散熱器43和熱膏42,並且孔陣列550和120的接線可以有效提供散熱器的鰭。
然而,孔陣列120的接線123可以具有遠端128,其延伸成在第四上表面521上或高於它。孔陣列120可以進一步具有其接線123的近端127,其耦合於第三上表面112以將熱傳導離開積體電路晶粒10。接線123的近端127可以軟焊或另外接合到第三上表面112,而接合或軟焊材料則形成打線接合125。
模製材料110可以配置於孔陣列120中,而孔陣列120之接線123的遠端128延伸在模製材料110上方。模製材料110可以包封晶粒堆疊501以及積體電路晶粒10。底填物54可以配置在表面511和102之間。
熱膏42(或更特別而言是一層熱膏42)可以配置成接觸接線123的遠端128和接觸散熱器43的下表面142以熱耦合接線123的遠端128和散熱器43。熱膏42可以沉積或另外配置在模製材料110的上表面141上,其是在晶粒堆疊501正上方以便接觸接線123的遠端128。再次而言,散熱器43可以位在或配置在(包括而不限於接觸)接線123的遠端128上方。然而,如示例所示,接線123的遠端128可以(雖然不須)直接接觸散熱器43
的下表面142。有效而言,熱膏42可以從接線123導熱到散熱器43,並且接線123可以從積體電路晶粒10導熱到熱膏42。
可選用而言,模製材料110不須配置在晶粒堆疊501的上表面521上方。於此種實施例,熱膏42可以直接接觸晶粒堆疊501的上表面521以將熱由此傳導離開到散熱器43。再者,如在此所述的散熱器43可以是任何散熱器,其習用而言是導熱的金屬或金屬合金,並且可以具有或可以沒有與之關聯的風扇、流體循環系統和/或其他熱移除系統。
可選用的鈍化層和金屬化層可以用於積體電路晶粒10,如先前所述,但為了清楚而不重複。附帶而言,孔陣列120可以包括多於一個孔陣列,例如孔陣列121和122,如先前所述,但為了清楚而不重複。
圖6是顯示形成例如先前所述的微電子裝置100之範例性過程600的流程圖。在601,可以獲得基板,其中此種基板具有第一上表面和第一下表面。此種基板可以是插置物40或封裝基板41。
在602,獲得積體電路晶粒10,其具有第二上表面和第二下表面。在603,此種基板的此種第一上表面以例如焊球53或微凸塊52而互連到此種積體電路晶粒10的此種第二下表面以在其間做電傳導。在604,可以形成孔陣列120,其具有其接線的近端而耦合於此種第二上表面,以將熱傳導離開此種積體電路晶粒10。
可選用而言,在形成孔陣列120之前,在611,鈍化層可以形成在此種積體電路晶粒的此種第二上表面上。在612,金屬化層可以鍍覆在此種鈍化層上,以供打線接合而將此種孔陣列之此種接線的此種近端耦合於此種第二上表面以供此種熱傳導。
在604形成孔陣列120之後,在605,模製材料110可以沉積於此種孔陣列120中,而此種孔陣列之此種接線的遠端至少延伸到此種沉積之模製材料110的較高表面。在606,可以施加熱膏42以接觸此種接線的此種遠端,而熱耦合此種接線的此種遠端與散熱器43。在607,此種散熱器的下表面可以放置到此種熱膏上。此種散熱器43的此種下表面可以位在此種接線的此種遠端上方以接觸此種散熱器43的下表面。
雖然前面描述了依據本發明之一或更多個方面的(多個)範例性具體態樣,不過可以設計出依據本發明之一或更多個方面的(多個)其他和進一步具體態樣,而不偏離本發明由接下來的請求項及其等同者所決定的範圍。列出步驟的(多個)申請專利範圍不暗示任何的步驟次序。商標是其個別擁有者的資產。
10-1~10-3‧‧‧積體電路(IC)
18‧‧‧孔結構
40‧‧‧插置物
41‧‧‧封裝基板
42‧‧‧導熱材料
43‧‧‧散熱器
44‧‧‧陣列互連
50‧‧‧三維(3D)IC封裝構件
52‧‧‧微凸塊
53‧‧‧凸塊或焊球
54‧‧‧底填物
Claims (20)
- 一種微電子裝置,其包括:基板,其具有第一上表面和第一下表面;積體電路晶粒,其具有第二上表面和第二下表面;互連,其將該基板的該第一上表面耦合於該積體電路晶粒的該第二下表面以在其間做電通訊;孔陣列,其具有其接線的近端而耦合於該第二上表面,以將熱傳導離開該積體電路晶粒;以及模製材料,其配置於該孔陣列中,而該孔陣列之該等接線的遠端至少延伸到該模製材料的較高表面。
- 根據申請專利範圍第1項的微電子裝置,其進一步包括:金屬化層,其配置在該積體電路晶粒的該第二上表面上,以將該孔陣列之該等接線的該等近端耦合於該第二上表面以供該傳導;散熱器,其配置在該等接線的該等遠端上方;以及導熱材料,其配置成接觸該等接線的該等遠端和該散熱器的下表面,以耦合該等接線的該等遠端和該散熱器以供熱傳導。
- 根據申請專利範圍第2項的微電子裝置,其中該等接線是第一接線,該微電子裝置進一步包括第二接線,其將該第二上表面耦合於該基板的該第一上表面以供該傳導。
- 根據申請專利範圍第1項的微電子裝置,其中:該孔陣列之該等接線的該等近端分別是第一孔陣列之第一接線的第一近端;以及 該微電子裝置進一步包括第二孔陣列,其具有其第二接線的第二近端而耦合於該第二上表面,以將該熱傳導離開該積體電路晶粒。
- 根據申請專利範圍第4項的微電子裝置,其中該第一孔陣列比該第二孔陣列還密。
- 根據申請專利範圍第5項的微電子裝置,其中該第一孔陣列配置在該積體電路晶粒的熱點上。
- 根據申請專利範圍第6項的微電子裝置,其中:該第一孔陣列之該等第一接線的該等遠端分別是第一孔陣列之第一接線的第一遠端;以及該第二孔陣列之該等第二接線的第二遠端比該第一孔陣列之該等第一接線的該等第一遠端分散得更寬廣。
- 根據申請專利範圍第7項的微電子裝置,其中該第一孔陣列之該等第一接線的該第一遠端和該第二孔陣列之該等第二接線的該第二遠端不接觸該散熱器的該下表面。
- 根據申請專利範圍第1項的微電子裝置,其中該基板是封裝基板。
- 一種微電子裝置,其包括:封裝基板,其具有第一上表面和第一下表面;插置物基板,其具有第二上表面和第二下表面;第一互連,其將該第二下表面和該第一上表面彼此耦合;積體電路晶粒,其具有第三上表面和第三下表面;第二互連,其將該第二上表面和該第三下表面彼此耦合;晶粒堆疊,其耦合於該插置物基板;其中該晶粒堆疊具有高於該第三 上表面的第四上表面;孔陣列,其具有其接線的近端而耦合於該第三上表面,以將熱傳導離開該積體電路晶粒;以及模製材料,其配置於該孔陣列中,而該孔陣列之該等接線的遠端至少延伸到該模製材料的較高表面並且高於該晶粒堆疊的該第四上表面。
- 根據申請專利範圍第10項的微電子裝置,其進一步包括:金屬化層,其配置在該積體電路晶粒的該第二上表面上,以供打線接合而將該孔陣列之該等接線的該等近端耦合於該第三上表面以供該傳導;散熱器,其配置在該等接線的該等遠端上方;以及導熱材料,其配置成接觸該等接線的該等遠端和該散熱器的下表面,以耦合該等接線的該等遠端與該散熱器以供熱傳導。
- 根據申請專利範圍第11項的微電子裝置,其進一步包括鈍化層,其配置在該積體電路晶粒的該第二上表面上,其中該金屬化層配置在該鈍化層上。
- 根據申請專利範圍第10項的微電子裝置,其中:該孔陣列之該等接線的該等近端分別是第一孔陣列之第一接線的第一近端;以及該微電子裝置進一步包括第二孔陣列,其具有其第二接線的第二近端而耦合於該第三上表面,以將該熱傳導離開該積體電路晶粒。
- 根據申請專利範圍第13項的微電子裝置,其中該第一孔陣列比該第二孔陣列還密。
- 根據申請專利範圍第14項的微電子裝置,其中該第一孔陣列配置在 該積體電路晶粒的熱點上。
- 根據申請專利範圍第13項的微電子裝置,其中:該第一孔陣列之該等第一接線的該等遠端分別是第一孔陣列之第一接線的第一遠端;以及該第二孔陣列之該等第二接線的第二遠端比該第一孔陣列之該等第一接線的該等第一遠端分散得更寬廣。
- 根據申請專利範圍第16項的微電子裝置,其中該第一孔陣列之該等第一接線的該等第一遠端和該第二孔陣列之該等第二接線的該等第二遠端不接觸該散熱器的該下表面。
- 一種形成微電子裝置的方法,其包括:獲得基板,其具有第一上表面和第一下表面;獲得積體電路晶粒,其具有第二上表面和第二下表面;藉由互連而將該基板的該第一上表面互連到該積體電路晶粒的該第二下表面以在其間做電傳導;形成孔陣列,其具有其接線的近端而耦合於該第二上表面,以將熱傳導離開該積體電路晶粒;以及沉積模製材料於該孔陣列中,而該孔陣列之該等接線的遠端至少延伸到該模製材料的較高表面。
- 根據申請專利範圍第18項的方法,其進一步包括:在該積體電路晶粒的該第二上表面上形成鈍化層;在該鈍化層上鍍覆金屬化層,以供打線接合而將該孔陣列之該等接線的該等近端耦合於該第二上表面以供該傳導; 施加導熱材料以接觸該等接線的該等遠端,而熱耦合該等接線的該等遠端與散熱器;以及將該散熱器的下表面放置到該導熱材料上;其中該散熱器的該下表面位在該等接線的該等遠端上方以接觸該散熱器的該下表面。
- 根據申請專利範圍第19項的方法,其中該孔陣列之該等接線的該等近端分別是第一孔陣列之第一接線的第一近端;以及該方法進一步包括形成第二孔陣列,其具有其第二接線的第二近端而耦合於該第二上表面,以將該熱傳導離開該積體電路晶粒。
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-
2014
- 2014-12-11 US US14/567,918 patent/US9735084B2/en active Active
-
2015
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- 2015-12-11 TW TW104141689A patent/TW201633457A/zh unknown
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US20160172268A1 (en) | 2016-06-16 |
US9735084B2 (en) | 2017-08-15 |
WO2016094134A1 (en) | 2016-06-16 |
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