KR20150038497A - 재구성된 웨이퍼-레벨 마이크로전자 패키지 - Google Patents
재구성된 웨이퍼-레벨 마이크로전자 패키지 Download PDFInfo
- Publication number
- KR20150038497A KR20150038497A KR1020157005269A KR20157005269A KR20150038497A KR 20150038497 A KR20150038497 A KR 20150038497A KR 1020157005269 A KR1020157005269 A KR 1020157005269A KR 20157005269 A KR20157005269 A KR 20157005269A KR 20150038497 A KR20150038497 A KR 20150038497A
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- South Korea
- Prior art keywords
- microelectronic
- conductive
- package
- elements
- semiconductor die
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
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- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
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- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/076—Connecting or disconnecting of strap connectors
- H10W72/07631—Techniques
- H10W72/07636—Soldering or alloying
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- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
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- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
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- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
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- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/654—Top-view layouts
- H10W70/655—Fan-out layouts
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- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
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- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
- H10W72/07338—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy hardening the adhesive by curing, e.g. thermosetting
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- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
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- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
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- H10W72/30—Die-attach connectors
- H10W72/321—Structures or relative sizes of die-attach connectors
- H10W72/325—Die-attach connectors having a filler embedded in a matrix
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- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
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- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
- H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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- H10W72/00—Interconnections or connectors in packages
- H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
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- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
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- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/877—Bump connectors and die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9413—Dispositions of bond pads on encapsulations
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/944—Dispositions of multiple bond pads
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
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- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
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- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/271—Configurations of stacked chips the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
Landscapes
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/563,085 | 2012-07-31 | ||
| US13/563,085 US9391008B2 (en) | 2012-07-31 | 2012-07-31 | Reconstituted wafer-level package DRAM |
| PCT/US2013/052883 WO2014022485A1 (en) | 2012-07-31 | 2013-07-31 | Reconstituted wafer-level microelectronic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20150038497A true KR20150038497A (ko) | 2015-04-08 |
Family
ID=48980322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020157005269A Withdrawn KR20150038497A (ko) | 2012-07-31 | 2013-07-31 | 재구성된 웨이퍼-레벨 마이크로전자 패키지 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US9391008B2 (enExample) |
| EP (1) | EP2880684B1 (enExample) |
| JP (1) | JP2015523740A (enExample) |
| KR (1) | KR20150038497A (enExample) |
| CN (1) | CN104685624B (enExample) |
| TW (1) | TWI538118B (enExample) |
| WO (1) | WO2014022485A1 (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102053349B1 (ko) * | 2013-05-16 | 2019-12-06 | 삼성전자주식회사 | 반도체 패키지 |
| TWI584387B (zh) * | 2014-08-15 | 2017-05-21 | 矽品精密工業股份有限公司 | 封裝結構之製法 |
| US9679873B2 (en) * | 2015-06-18 | 2017-06-13 | Qualcomm Incorporated | Low profile integrated circuit (IC) package comprising a plurality of dies |
| US9601467B1 (en) | 2015-09-03 | 2017-03-21 | Invensas Corporation | Microelectronic package with horizontal and vertical interconnections |
| IT201700055983A1 (it) | 2017-05-23 | 2018-11-23 | St Microelectronics Srl | Procedimento per produrre dispositivi a semiconduttore, dispositivo a semiconduttore e circuito corrispondenti |
| US10141259B1 (en) * | 2017-12-22 | 2018-11-27 | Micron Technology, Inc. | Semiconductor devices having electrically and optically conductive vias, and associated systems and methods |
Family Cites Families (572)
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| DE1439262B2 (de) | 1963-07-23 | 1972-03-30 | Siemens AG, 1000 Berlin u. 8000 München | Verfahren zum kontaktieren von halbleiterbauelementen durch thermokompression |
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| DE2119567C2 (de) | 1970-05-05 | 1983-07-14 | International Computers Ltd., London | Elektrische Verbindungsvorrichtung und Verfahren zu ihrer Herstellung |
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-
2012
- 2012-07-31 US US13/563,085 patent/US9391008B2/en active Active
-
2013
- 2013-07-22 TW TW102126177A patent/TWI538118B/zh not_active IP Right Cessation
- 2013-07-31 CN CN201380050994.1A patent/CN104685624B/zh active Active
- 2013-07-31 KR KR1020157005269A patent/KR20150038497A/ko not_active Withdrawn
- 2013-07-31 WO PCT/US2013/052883 patent/WO2014022485A1/en not_active Ceased
- 2013-07-31 EP EP13748197.4A patent/EP2880684B1/en active Active
- 2013-07-31 JP JP2015525537A patent/JP2015523740A/ja active Pending
-
2016
- 2016-06-29 US US15/196,635 patent/US9917073B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP2880684B1 (en) | 2018-12-19 |
| TW201411785A (zh) | 2014-03-16 |
| CN104685624B (zh) | 2018-02-02 |
| CN104685624A (zh) | 2015-06-03 |
| US9391008B2 (en) | 2016-07-12 |
| TWI538118B (zh) | 2016-06-11 |
| US9917073B2 (en) | 2018-03-13 |
| EP2880684A1 (en) | 2015-06-10 |
| WO2014022485A1 (en) | 2014-02-06 |
| US20140035153A1 (en) | 2014-02-06 |
| US20160307878A1 (en) | 2016-10-20 |
| JP2015523740A (ja) | 2015-08-13 |
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