JP5887414B2 - 平行な窓を有するマルチダイのワイヤボンドアセンブリのスタブ最小化 - Google Patents

平行な窓を有するマルチダイのワイヤボンドアセンブリのスタブ最小化 Download PDF

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JP5887414B2
JP5887414B2 JP2014534614A JP2014534614A JP5887414B2 JP 5887414 B2 JP5887414 B2 JP 5887414B2 JP 2014534614 A JP2014534614 A JP 2014534614A JP 2014534614 A JP2014534614 A JP 2014534614A JP 5887414 B2 JP5887414 B2 JP 5887414B2
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microelectronic
package
terminals
terminal
microelectronic element
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JP2014530508A (ja
JP2014530508A5 (enExample
Inventor
クリスプ，リチャード・デューイット
ゾーニ，ワエル
ハーバ，ベルガセム
ランブレクト，フランク
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インヴェンサス・コーポレイション
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Priority claimed from US13/337,565 external-priority patent/US8436457B2/en
Priority claimed from US13/337,575 external-priority patent/US8345441B1/en
Priority claimed from US13/440,515 external-priority patent/US8441111B2/en
Application filed by インヴェンサス・コーポレイション filed Critical インヴェンサス・コーポレイション
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • H10W70/635—
    • H10W70/65—
    • H10W70/68—
    • H10W72/00—
    • H10W90/00—
    • H10W70/60—
    • H10W72/29—
    • H10W72/59—
    • H10W72/865—
    • H10W72/884—
    • H10W72/9445—
    • H10W74/00—
    • H10W74/117—
    • H10W74/142—
    • H10W90/24—
    • H10W90/288—
    • H10W90/722—
    • H10W90/724—
    • H10W90/732—
    • H10W90/734—
    • H10W90/754—

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2014534614A 2011-10-03 2012-09-28 平行な窓を有するマルチダイのワイヤボンドアセンブリのスタブ最小化 Expired - Fee Related JP5887414B2 (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201161542553P 2011-10-03 2011-10-03
US61/542,553 2011-10-03
US13/337,565 US8436457B2 (en) 2011-10-03 2011-12-27 Stub minimization for multi-die wirebond assemblies with parallel windows
US13/337,575 2011-12-27
US13/337,575 US8345441B1 (en) 2011-10-03 2011-12-27 Stub minimization for multi-die wirebond assemblies with parallel windows
US13/337,565 2011-12-27
US13/440,515 US8441111B2 (en) 2011-10-03 2012-04-05 Stub minimization for multi-die wirebond assemblies with parallel windows
US13/440,515 2012-04-05
PCT/US2012/057905 WO2013052372A2 (en) 2011-10-03 2012-09-28 Stub minimization for multi-die wirebond assemblies with parallel windows

Publications (3)

Publication Number Publication Date
JP2014530508A JP2014530508A (ja) 2014-11-17
JP2014530508A5 JP2014530508A5 (enExample) 2015-11-19
JP5887414B2 true JP5887414B2 (ja) 2016-03-16

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JP2014534614A Expired - Fee Related JP5887414B2 (ja) 2011-10-03 2012-09-28 平行な窓を有するマルチダイのワイヤボンドアセンブリのスタブ最小化
JP2014534615A Expired - Fee Related JP5887415B2 (ja) 2011-10-03 2012-09-28 平行な窓を有するマルチダイのワイヤボンドアセンブリのスタブ最小化
JP2014534635A Expired - Fee Related JP5887416B2 (ja) 2011-10-03 2012-10-02 直交する窓を有するマルチダイワイヤボンドアセンブリのためのスタブ最小化
JP2014534636A Expired - Fee Related JP5887417B2 (ja) 2011-10-03 2012-10-02 直交する窓を有するマルチダイワイヤボンドアセンブリのためのスタブ最小化

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JP2014534615A Expired - Fee Related JP5887415B2 (ja) 2011-10-03 2012-09-28 平行な窓を有するマルチダイのワイヤボンドアセンブリのスタブ最小化
JP2014534635A Expired - Fee Related JP5887416B2 (ja) 2011-10-03 2012-10-02 直交する窓を有するマルチダイワイヤボンドアセンブリのためのスタブ最小化
JP2014534636A Expired - Fee Related JP5887417B2 (ja) 2011-10-03 2012-10-02 直交する窓を有するマルチダイワイヤボンドアセンブリのためのスタブ最小化

Country Status (6)

Country Link
US (2) US8981547B2 (enExample)
EP (4) EP2764544A1 (enExample)
JP (4) JP5887414B2 (enExample)
KR (4) KR101894823B1 (enExample)
TW (6) TWI512935B (enExample)
WO (4) WO2013052372A2 (enExample)

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US11495519B2 (en) * 2019-06-07 2022-11-08 Dana Canada Corporation Apparatus for thermal management of electronic components
JP7400536B2 (ja) * 2020-02-27 2023-12-19 セイコーエプソン株式会社 半導体装置
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