TWM338433U - Multi-chip package structure - Google Patents

Multi-chip package structure Download PDF

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Publication number
TWM338433U
TWM338433U TW097202729U TW97202729U TWM338433U TW M338433 U TWM338433 U TW M338433U TW 097202729 U TW097202729 U TW 097202729U TW 97202729 U TW97202729 U TW 97202729U TW M338433 U TWM338433 U TW M338433U
Authority
TW
Taiwan
Prior art keywords
substrate
chip
package structure
chip package
opening
Prior art date
Application number
TW097202729U
Other languages
Chinese (zh)
Inventor
Yueh-Ming Tung
Chia-Ming Yang
Shu-Hui Lin
Ya-Wen Kuo
Mien-Fang Sung
Original Assignee
Orient Semiconductor Elect Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Orient Semiconductor Elect Ltd filed Critical Orient Semiconductor Elect Ltd
Priority to TW097202729U priority Critical patent/TWM338433U/en
Priority to JP2008003543U priority patent/JP3143893U/en
Publication of TWM338433U publication Critical patent/TWM338433U/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A multi-chip package structure is disclosed. The structure comprises a substrate, a DRAM chip, a flash memory chip, a first package body, a second package body and a plurality of solder balls. The DRAM chip and the flash memory chip are stacked on the substrate in sequence. The first package body is formed on a first surface of the substrate and encapsulates the DRAM chip and the flash memory chip. The second package body is formed in an opening of the substrate to encapsulate the opening. The solder balls are disposed at a second surface of the substrate.

Description

M338433 八、新型說明： 【新型所屬之技術領域】 本新型是有關於一種多晶片封裝結構，且特別是有關 於同時堆疊多個晶片的多晶片封裝結構。 【先前技術】 在半導體生產過程中，積體電路封裝（IC package)是製 程的重要步驟之一，用以保護1C晶片與提供外部電性連 接，以防止在輸送及取置過程中外力或環境因素的破壞。 此外，積體電路元件亦需與電阻、電容等被動元件組合成 為一個系統，才能發揮既定的功能，而電子封裝（Electronic Packaging)即係用以建立積體電路元件的保護與組織架 構。一般而言，在積體電路晶片製程之後始進行電子封裝， 包括1C晶片的黏結固定、電路連線、結構密封、與電路板 之接合、系統組合、直至產品完成之間的所有製程。電子 封裝之目的為完成1C晶片與其它必要之電路零件的組合， 以傳遞電能與電路訊號、提供散熱途徑、承載與結構保護 等功能。 在現今電子裝置中，單一電子裝置中常需設置多個晶 片來同時執行多種功能，以滿足現代人對於電子裝置之需 求。以行動電話（手機）為例，目前的手機中大多内建有快閃 (Flash)記憶體晶片、動態隨機存取記憶體（Dynamic Random Access Memory ; DRAM)晶片及控制器晶片等。然而，上述 晶片一般係分別形成於不同的封裝結構，因而增加封裝結 構的所佔空間，亦增加電子裝置（手機）實現輕薄和微型化之 M338433 困難。 【新型内容】 因此本新型之—方面係在於提供—種多晶片封裝結 構’藉以堆疊設置動態隨機存取記憶體(D R A M)及快閃記憶 體(Flash Memory)晶片於單一封裝結構中，以節省電子裝^ (例如手機）之内部空間。M338433 VIII. New Description: [New Technology Field] The present invention relates to a multi-chip package structure, and more particularly to a multi-chip package structure in which a plurality of wafers are stacked at the same time. [Prior Art] In the semiconductor manufacturing process, IC package is one of the important steps of the process to protect the 1C chip and provide external electrical connection to prevent external force or environment during transportation and handling. The destruction of factors. In addition, integrated circuit components must be combined with passive components such as resistors and capacitors to form a system to perform the intended functions, and electronic packaging is used to establish the protection and organization of integrated circuit components. In general, electronic packaging begins after the integrated circuit wafer process, including bonding of 1C wafers, circuit wiring, structural sealing, bonding to the board, system combination, and all processes between product completions. The purpose of the electronic package is to complete the combination of the 1C chip and other necessary circuit components to transfer power and circuit signals, provide heat dissipation, load and structure protection. In today's electronic devices, it is often necessary to provide a plurality of wafers in a single electronic device to perform multiple functions simultaneously to meet the needs of modern people for electronic devices. Taking mobile phones (mobile phones) as an example, most of the current mobile phones have built-in flash memory chips, dynamic random access memory (DRAM) chips, and controller chips. However, the above-mentioned wafers are generally formed in different package structures, thereby increasing the space occupied by the package structure, and also increasing the difficulty of realizing the thin and miniaturized M338433 of the electronic device (handset). [New content] Therefore, the aspect of the present invention is to provide a multi-chip package structure 'by stacking dynamic random access memory (DRAM) and flash memory chips in a single package structure to save The internal space of an electronic device (such as a mobile phone).

、根據本新型之實施例’本新型之多晶片封裝結構係至 少包含有基板、動態隨機存取記憶體晶片、快閃記憶體晶 片、至少-第一接線、至少一第二接線、第一封膠體、第 一封膠體及複數個錫球。基板具有第一表面、第二表面及 開口’其中開口係開設於第一表面和第二表面之間。動態 隨機存取記憶體晶片設置於基板之第一表面上，且晶片: 主動面係面向開Π。快閃記憶體晶片設置於動態隨機存取 記憶體(DRAM)晶片上。第-接線電性連接於快閃記憶體晶 片與基板之間。第二接線係經由開口來電性連接動態隨機 存取記憶體晶片之主動面與基板之第二表面。第一封膠體 形成於基板之第一表面上，並包覆動態隨機存取記憶體晶 片、快閃記憶體晶片及第一接線。第二封膠體形成於基板 之開口中，並包覆開口和第二接線。此些錫球設置於基板 之第二表面上，其中錫球在第二表面上之高度高於第二封 膠體之高度。 因此，本新型之多晶片封裝結構可堆疊封裝多個晶片 於單一封裝結構中，因而可節省空間。 M338433 【實施方式】 請參照第1A圖，其係繪示依照本新型之第一實施例之 多晶片封裝結構的剖面示意圖。本實施例之多晶片封裝結 構100包含有基板110、動態隨機存取記憶體（dram)晶片 120、快閃記憶體（Flash Memory)晶片130、控制晶片140、 第一接線150、第二接線160、第一封膠體170、第二封膠 體180及複數個錫球（Solder Ball) 190。DRAM晶片120、快 閃記憶體晶片130及控制晶片140係堆疊設置於基板11〇 上。第一接線150係用以電性連接於快閃記憶體晶片130 與基板110之間，以及控制晶片140與基板11〇之間。第 二接線160係用以電性連接於DRAM晶片120與基板110 之間，第一封膠體170係用以包覆DRAM晶片120、快閃 記憶體晶片130、控制晶片140及第一接線150,第二封膠 體180係用以包覆第二接線160,此些錫球190係設釁於基 板110之一側表面上，以電性連接多晶片封裝結構100於 一電子裝置（例如手機）之載板上，其載板可為：印刷電路板 (Printed circuit board ; PCB)、軟性印刷電路板（Flexible Printed Circuits ; FPC)或主機板。 如第1A圖所示，本實施例之基板110具有第一表面 111、第二表面112及開口 113，第一表面111和第二表面 112係分別位於基板110之相對兩侧，開口 113係開設於第 一表面111和第二表面112之間，且開口 113之面積係至 少小於DRAM晶片120之面積。基板110例如係由介電質 材料所製成，例如·· BT(BismaleimideTriazine)熱固性樹脂 材料、環氧樹脂、陶瓷或有機玻璃纖維，並設有被動元件 M338433 114、接墊115及線路（未繪示）。被動元件114例如為電容、 電感或電阻，接墊115及線路可形成於基板110之第一表 面111和第二表面112上。在本實施例中，被動元件114 可利用表面黏著（SMT)方式來設置於基板110之第一表面 111上，並電性連接於接墊115和線路。然不限於此，在一 些實施例中，被動元件114亦可埋設於基板110中，而形 成整合型被動元件基板。 如第1A圖所示，本實施例之DRAM晶片120可表面 黏著於基板110之第一表面111上，並位於基板110之開 口 113上。此時，DRAM晶片120之主動面較佳係面對於 基板110之第一表面111，並暴露出DRAM晶片120之部 分主動面於開口 113中。快閃記憶體晶片130和控制晶片 140係依序地堆疊設置於DRAM晶片120之背面（亦即 DRAM晶片120的非主動表面）上，其中控制晶片140未完 全覆蓋住快閃記憶體晶片130，並暴露出快閃記憶體晶片 130之一部分表面131。在本實施例中，控制晶片140之面 積例如係小於快閃記憶體晶片130之面積（如第1A圖所 示）；或者，控制晶片140可僅部分設置於快閃記憶體晶片 130上（如第1A圖所示）。 如第1A圖所示，本實施例之第一接線150和第二接線 160例如為金線、銀線、銅線或鋁線，第一接線150係分別 電性連接於快閃記憶體晶片130之主動面與基板110之第 一表面111上的接墊115，以及電性連接於控制晶片140與 基板110之第一表面111上的接墊115。第二接線160透過 基板110之開口 113來電性連接於DRAM晶片120之主動 M338433 面上的中央接墊與基板110之第二表面112上的接墊115。 如第1A圖所示，本實施例之第一封膠體170和第二封 膠體180之材料例如為：環氧樹脂、PMMA、聚碳酸酯 (Polycarbonate)或矽膠。第一封膠體170係形成於基板110 之第一表面111上，用以包覆並密封DRAM晶片120、快 閃記憶體晶片130、控制晶片14〇、第一接線150及被動元 件114。第二封膠體180係形成於基板11〇之開口 113中， 用以包覆並密封開口 113(亦即DRAM晶片120之部分主動 面及中央接墊）和第二接線160。錫球190可利用例如銲球 植球機（未繪示）來設置於基板110之第二表面112上，其中 銲球190的材料例如為：錫、鋁、鎳、銀、銅、鋼或其合 金’其中錫球190在第二表面112上之高度相較於第二封 膠體180之高度係至少高於〇·1ππη以上，因而當多晶片封 裝結構100電性連接於載板上時，第二封膠體18〇不致影 響錫球190對於載板之結合。 當製造本實施例之多晶片封裝結構10〇時，DRAM晶 片120可預先結合於基板11〇，並連接第二接線ι6〇和形成 第二封膠體180。接著，再堆疊快閃記憶體（Fiash Memory) 晶片130和控制晶片140於DRAM晶片120之背面上，並 連接第一接線150和形成第一封膠體170，然後設置錫球 190 〇 在一實施例中，快閃記憶體晶片130和控制晶片140 可預先堆疊接合於DRAM晶片120之背面上，接著，此些 晶片再結合於基板110上，接著，連接第一接線15〇和第 二接線160，以及形成第一封膠體17〇和第二封膠體18〇， M338433 然後設置錫球190。然不限於此，熟悉此領域者亦可藉由其 他不同的製程順序來形成本實施例之多晶片封裝結構1〇〇。 因此，上述多個晶片可封裝於單一封裝結構中，並設 置於一電子裝置（例如手機）中，以降低上述三種晶片於電子 裝置内之佔用空間，因而符合電子裝置輕薄化之需求。 請參照第1B圖，其係繪示依照本新型之第一實施例之 多晶片封裝結構的剖面示意圖。值得注意的是，本新型之 控制晶片140之設置並不限於上述實施例所述之方式，在 一些實施例中，如第1B圖所示，控制晶片140亦可直接設 於基板110上，並利用至少一第三接線141來與基板110 電性連接，而位於堆疊之快閃記憶體晶片13〇|及DRAM晶 片120的一侧，其中，快閃記憶體晶片130及DRAM晶片 120之堆疊及設置方式，亦與第1A圖所示相同。 請參照第2圖，其繪示依照本新型之第主實施你li乡 晶片封裝結構的剖面示意圖。相較於第一實施例，第二實 施例之多晶片封裝結構100a的基板110更具肴一環階無部 116a，其凹設於開口 113内，且連通於第一表面111。當 DRAM晶片120以主動面面向開口並接合於基板110之第 一表面111上時，DRAM晶片120可卡掣於環岵梯部116 a 設置於基板110上，並以與第一實施例所述相同之打線方 式與基板110電性連接，因而降低多個晶片120、130、140 於基板110上堆疊之高度，進而可減少多晶片封裝結構100 之整體高度。 請參照第3圖，其繪示依照本新型之第三實施例之多 晶片封裝結構的剖面示意圖。相較於第一實施例，第三實 10 M338433 施例之夕曰曰片封裝結構1〇〇b的基板ιι〇之環階梯部11补 係凹設於開π U3 m，且位於第二表面112上。此時，環 階梯部116b可設有接墊115b，第二接線16〇可電性連接於 DRAM晶片12〇之中央接墊與環階梯部㈣上的接塾 115，第一封膠體180可形成於開口 113和環階梯部116b :，因而可降低第二封膠體180形成於第二表面112上之 高度；或者，第二封膠體180可未突出於第二表面112。 由上述本新型的實施例可知，本新型之多晶片封裝結 構可同時封裝多個晶片，因而節省封裝結構所佔之空間。 雖然本新型已以一較佳實施例揭露如上，然其並非用 以限=本新型，任何熟習此技藝者，在不脫離本新型之精 神=範圍内，當可作各種之更動與潤飾，因此本新型之保 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 ^為讓本新型之上述和其他目的、特徵、優點與實施例 月色更明顯易懂，所附圖式之詳細說明如下： 第1A圖和第1B圖係繪示依照本新型之第一實施例之 多晶片封裝結構的剖面示意圖。 第2圖係繪示依照本新型之第二實施例之多晶片 結構的剖面示意圖。 ' 晶片封裝 第3圖係繪示依照本新型之第三實施例之多 結構的剖面示意圖。 【主要元件符號說明】 11 M338433 100、100a、100b ··多晶片封裝結構 110 :基板 111 :第一表面 112 :第二表面 113 :開口 114 ··被動元件 115 :接墊 116a、116b :環階梯部 120 :動態隨機存取記憶體晶片 130 :快閃記憶體晶片 140 ··第三晶片 150 :第一接線 170 :第一封膠體 19 0 :錫球 131 :部分表面 141 :第三接線 160 :第二接線 180 :第二封膠體According to an embodiment of the present invention, the multi-chip package structure of the present invention includes at least a substrate, a dynamic random access memory chip, a flash memory chip, at least a first wiring, at least a second wiring, and a first Colloid, first sealant and multiple solder balls. The substrate has a first surface, a second surface, and an opening, wherein the opening is between the first surface and the second surface. The dynamic random access memory chip is disposed on the first surface of the substrate, and the wafer: the active surface is facing the opening. The flash memory chip is disposed on a dynamic random access memory (DRAM) wafer. The first wiring is electrically connected between the flash memory chip and the substrate. The second wiring electrically connects the active surface of the DRAM chip and the second surface of the substrate via the opening. The first gel is formed on the first surface of the substrate and covers the dynamic random access memory chip, the flash memory chip and the first wiring. The second encapsulant is formed in the opening of the substrate and covers the opening and the second wiring. The solder balls are disposed on the second surface of the substrate, wherein the height of the solder balls on the second surface is higher than the height of the second seal. Therefore, the novel multi-chip package structure can stack a plurality of wafers in a single package structure, thereby saving space. [Embodiment] Please refer to FIG. 1A, which is a cross-sectional view showing a multi-chip package structure according to a first embodiment of the present invention. The multi-chip package structure 100 of the present embodiment includes a substrate 110, a dynamic random access memory (dram) wafer 120, a flash memory chip 130, a control wafer 140, a first wiring 150, and a second wiring 160. The first sealant 170, the second sealant 180, and a plurality of solder balls 190. The DRAM wafer 120, the flash memory chip 130, and the control wafer 140 are stacked on the substrate 11A. The first wiring 150 is electrically connected between the flash memory chip 130 and the substrate 110, and between the control wafer 140 and the substrate 11A. The second wiring 160 is electrically connected between the DRAM wafer 120 and the substrate 110. The first sealing body 170 is used to cover the DRAM wafer 120, the flash memory chip 130, the control wafer 140, and the first wiring 150. The second sealing body 180 is used to cover the second wiring 160. The solder balls 190 are disposed on one side surface of the substrate 110 to electrically connect the multi-chip package structure 100 to an electronic device (such as a mobile phone). On the carrier board, the carrier board can be: a printed circuit board (PCB), a flexible printed circuit board (FPC) or a motherboard. As shown in FIG. 1A, the substrate 110 of the present embodiment has a first surface 111, a second surface 112, and an opening 113. The first surface 111 and the second surface 112 are respectively located on opposite sides of the substrate 110, and the opening 113 is opened. Between the first surface 111 and the second surface 112, and the area of the opening 113 is at least smaller than the area of the DRAM wafer 120. The substrate 110 is made, for example, of a dielectric material, such as BT (Bismaleimide Triazine) thermosetting resin material, epoxy resin, ceramic or plexiglass fiber, and is provided with passive components M338433 114, pads 115 and lines (not drawn Show). The passive component 114 is, for example, a capacitor, an inductor or a resistor, and pads 115 and lines may be formed on the first surface 111 and the second surface 112 of the substrate 110. In this embodiment, the passive component 114 can be disposed on the first surface 111 of the substrate 110 by surface adhesion (SMT) and electrically connected to the pad 115 and the wiring. Without being limited thereto, in some embodiments, the passive component 114 may also be embedded in the substrate 110 to form an integrated passive component substrate. As shown in FIG. 1A, the DRAM wafer 120 of the present embodiment is surface-attached to the first surface 111 of the substrate 110 and is located on the opening 113 of the substrate 110. At this time, the active surface of the DRAM wafer 120 preferably faces the first surface 111 of the substrate 110 and exposes a portion of the active surface of the DRAM wafer 120 in the opening 113. The flash memory chip 130 and the control wafer 140 are sequentially stacked on the back surface of the DRAM wafer 120 (ie, the inactive surface of the DRAM wafer 120), wherein the control wafer 140 does not completely cover the flash memory chip 130. A portion of the surface 131 of the flash memory chip 130 is exposed. In this embodiment, the area of the control wafer 140 is, for example, smaller than the area of the flash memory chip 130 (as shown in FIG. 1A); or the control wafer 140 may be only partially disposed on the flash memory chip 130 (eg, Figure 1A)). As shown in FIG. 1A, the first wiring 150 and the second wiring 160 of the embodiment are, for example, gold wires, silver wires, copper wires or aluminum wires, and the first wires 150 are electrically connected to the flash memory chips 130, respectively. The active surface and the pad 115 on the first surface 111 of the substrate 110 are electrically connected to the pads 115 on the first surface 111 of the control wafer 140 and the substrate 110. The second wiring 160 is electrically connected to the central pad on the active M338433 surface of the DRAM wafer 120 and the pad 115 on the second surface 112 of the substrate 110 through the opening 113 of the substrate 110. As shown in Fig. 1A, the materials of the first encapsulant 170 and the second encapsulant 180 of the present embodiment are, for example, epoxy resin, PMMA, polycarbonate or silicone. A first adhesive 170 is formed on the first surface 111 of the substrate 110 for covering and sealing the DRAM wafer 120, the flash memory chip 130, the control wafer 14A, the first wiring 150, and the passive component 114. A second encapsulant 180 is formed in the opening 113 of the substrate 11 to cover and seal the opening 113 (i.e., a portion of the active surface of the DRAM wafer 120 and the center pad) and the second wiring 160. The solder ball 190 can be disposed on the second surface 112 of the substrate 110 by using, for example, a solder ball ball machine (not shown), wherein the material of the solder ball 190 is, for example, tin, aluminum, nickel, silver, copper, steel or The height of the solder ball 190 on the second surface 112 is higher than the height of the second encapsulant 180 by at least 〇·1ππη or more, so when the multi-chip package structure 100 is electrically connected to the carrier board, The two seals 18〇 do not affect the bonding of the solder balls 190 to the carrier. When the multi-chip package structure 10 of the present embodiment is fabricated, the DRAM wafer 120 may be previously bonded to the substrate 11A, and the second wiring member 连接6 and the second sealing body 180 may be formed. Then, the Fiash Memory wafer 130 and the control wafer 140 are stacked on the back surface of the DRAM wafer 120, and the first wiring 150 is connected and the first encapsulant 170 is formed, and then the solder ball 190 is disposed. The flash memory chip 130 and the control wafer 140 may be pre-stacked and bonded on the back surface of the DRAM wafer 120. Then, the wafers are re-bonded to the substrate 110, and then the first wiring 15 and the second wiring 160 are connected. And forming a first encapsulant 17 〇 and a second encapsulant 18 〇, M338433 and then placing a solder ball 190. However, it is not limited thereto, and those skilled in the art can also form the multi-chip package structure of the present embodiment by other different process sequences. Therefore, the plurality of wafers can be packaged in a single package structure and disposed in an electronic device (for example, a mobile phone) to reduce the space occupied by the three types of chips in the electronic device, thereby meeting the demand for thinning of the electronic device. Referring to FIG. 1B, a cross-sectional view of a multi-chip package structure in accordance with a first embodiment of the present invention is shown. It is to be noted that the arrangement of the control chip 140 of the present invention is not limited to the manner described in the above embodiments. In some embodiments, as shown in FIG. 1B, the control wafer 140 may be directly disposed on the substrate 110, and At least one third wire 141 is electrically connected to the substrate 110, and is located on one side of the stacked flash memory chip 13〇 and the DRAM chip 120, wherein the stack of the flash memory chip 130 and the DRAM chip 120 and The setting method is also the same as shown in Figure 1A. Please refer to FIG. 2, which is a cross-sectional view showing the package structure of the circuit in accordance with the first embodiment of the present invention. Compared with the first embodiment, the substrate 110 of the multi-chip package structure 100a of the second embodiment has a ring-shaped portion 116a which is recessed in the opening 113 and communicates with the first surface 111. When the DRAM wafer 120 faces the opening with the active surface and is bonded to the first surface 111 of the substrate 110, the DRAM wafer 120 can be disposed on the substrate 110 with the ring-shaped ladder portion 116a, and is described in the first embodiment. The same wiring method is electrically connected to the substrate 110, thereby reducing the height of stacking of the plurality of wafers 120, 130, 140 on the substrate 110, thereby reducing the overall height of the multi-chip package structure 100. Referring to FIG. 3, a cross-sectional view of a multi-chip package structure in accordance with a third embodiment of the present invention is shown. Compared with the first embodiment, the ring-shaped step portion 11 of the substrate 封装 的 封装 封装 封装 M M M M M M M M M M M M M M M M M 阶梯 阶梯 阶梯 阶梯 阶梯 阶梯 阶梯112 on. At this time, the ring step portion 116b can be provided with a pad 115b, and the second wire 16b can be electrically connected to the central pad of the DRAM chip 12b and the interface 115 on the ring step (4), and the first encapsulant 180 can be formed. The opening 113 and the ring step 116b: thus, the height of the second encapsulant 180 formed on the second surface 112 can be reduced; or the second encapsulant 180 can not protrude from the second surface 112. It can be seen from the above embodiments of the present invention that the multi-chip package structure of the present invention can package a plurality of wafers at the same time, thereby saving space occupied by the package structure. Although the present invention has been described above with reference to a preferred embodiment, it is not intended to limit the present invention, and any skilled person skilled in the art can make various changes and retouchings without departing from the spirit of the present invention. The scope of protection of this new type is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious and easy to understand, the detailed description of the drawings is as follows: FIGS. 1A and 1B are drawn in accordance with A schematic cross-sectional view of a multi-chip package structure of the first embodiment of the present invention. Figure 2 is a schematic cross-sectional view showing a multi-wafer structure in accordance with a second embodiment of the present invention. 'Wafer Package FIG. 3 is a schematic cross-sectional view showing a multi-structure according to a third embodiment of the present invention. [Main component symbol description] 11 M338433 100, 100a, 100b · Multi-chip package structure 110: substrate 111: first surface 112: second surface 113: opening 114 · passive element 115: pads 116a, 116b: ring step Portion 120: Dynamic Random Access Memory Wafer 130: Flash Memory Wafer 140 • Third Wafer 150: First Wiring 170: First Sealant 19 0: Tin Ball 131: Partial Surface 141: Third Wiring 160: Second wiring 180: second sealing body

1212

Claims (1)

M338433 九、申請專利範圍： 1 · 一種多晶片封裝結構，至少包含： 一基板，具有一第一表面、一第二表面及一開口，其 中該開口係開設於該第一表面和該第二表面之間； 一動態隨機存取記憶體（DRAM)晶片，設置於該基板之 該第一表面上，且該動態隨機存取記憶體晶片之一主動面 係面向該開口； 一快閃記憶體（Flash Memory)晶片，設置於該動態隨機 存取記憶體晶片上； 至少一第一接線，電性連接於該快閃記憶體晶片與該 基板之間； 至少一第二接線，經由該開口來電性連接於該動態隨 機存取記憶體晶片之該主動面與該基板之該第二表面； 一第一封膠體，形成於該基板之該第一表面上，並包 覆該動態隨機存取記憶體晶片、該快閃記憶體晶片及該些 第一接線； 一第二封膠體，形成於該基板之該開口中，並包覆該 開口和該第二接線；以及 複數個錫球，設置於該基板之該第二表面上，其中該 些錫球在該第二表面上之高度係高於該第二封膠體之高 度。 同 封裝結構，更 2·如申請專利範圍第1項所述之多晶片 至少包含： 13 M338433 控制晶片’設置於該快閃記憶體晶片上，並與该美 板電性連接。 3·如申請專利範圍第2項所述之多晶片封裝結構，其 中，該控制晶片與該基板之間係以該第一接線電性連接。 4·如申請專利範圍第1項所述之多晶片封裝結構，更 包含： 一控制晶片’設置於該基板之第一表面上，並與該基 板電性連接。 5·如申請專利範圍第4項所述之多晶片封裝結構，更 包含： 至少一第三接線，其電性連接於該控制晶片與該基板 之間。 土 i 6·如申請專利範圍第i項所述之多晶片封裝結構，其 中，該些錫球在該第二表面上之高度係至少高於該第二封 膠體之高度0.1mm以上。 7. 如申請專利範圍第1項所述之多晶片封裴結構，其 中該多晶片封裝結構係電性連接於一手機之一載板上。 8. 如申請專利範圍第7項所述之多晶片封裝結構，其 中該載板為印刷電路板(Printed circuit board pcB)、軟^ 14 M338433 印刷電路板（Flexible Printed Circuits ; FPC)或主機板。 9·如申請專利範圍第1項所述之多晶片封裝結構，其 中該基板設有至少一被動元件。 10·如申請專利範圍第9項所述之多晶片封裝結構， • 其中該被動元件係選自由電容、電感及電阻所組成之一族 -群。 、 11·如申請專利範圍第9項所述之多晶片封裝結構， 其中該被動元件係利用表面黏著（SMT)方式來設置於該其 板之該第一表面上。 12·如申請專利範圍第9項所述之多晶片封裝結構， 其中該被動元件係埋設於該基板中。 # 13_如申請專利範圍第1項所述之多晶片封裝結構， 其中該第一接線和該第二接線為金線、銀線、鋼線或鎔線。 14·如申請專利範圍第1項所述之多晶片封裝結構， 其中該第一封膠體和該第二封膠體之材料為環氧樹脂、 PMMA、聚碳酸酯（p〇lycarb〇nate)或矽膠。 15·如申請專利範圍第1項所述之多晶片封裝結構， 其中該銲球之材料係選自由錫、鋁、錄、、銀、鋼、銦及其 15 M338433 合金所組成之族群 二6其：申請專利範圍第1項所述之多晶片封裝結構， 板更具有一環階梯部，其凹設於該開口内，且連 表面’該動態隨機存取記憶體晶片係切於該 .盆二且如申請專利範圍第1項所述之多晶片封裝結構’ •，、中該基板更具有一環階梯部，其凹設於該開口内，且位 於該第二表面上，該第二接線係電性連接於該動態隨機存 取§己憶體晶片與該環階梯部上。 18· 一種多晶片封裝結構，至少包含： 一基板，具有一第一表面、—第二表面及一_口，其 中該開口係開設於該第一表面和該第二表面之間，· 一動態隨機存取記憶體(DRAM)晶片，設置於該基板之 該第一表面上，且該動態隨椽存取記憶體晶片之主動面係 面向該開口； —快閃記憶體（FlashMemory)晶片，設置於該動態随機 存取記憶體晶片上，· 一控制晶片，設置於該快閃記憶體晶片上； 複數個第-接線，分別電性連接於該快閃記憶體晶月 與該基板之間，以及電性連接於該控制晶片與該基板之間； 至少-第二接線’經由該開口來電性連接於該動態隨 機存取記憶體晶片之另一側與該基板之該第二表面； 16 M338433 一第一封膠體，形成於該基板之該第一表面上，並包 覆該動態隨機存取記憶體晶片、該快閃記憶體晶片、該控 制晶片及該些第一接線； 一第二封膠體，形成於該基板之該開口中，並包覆該 開口和該第二接線； 複數個錫球，設置於該基板之該第二表面上，其中該 些錫球在該第二表面上之高度係高於該第二封膠體之高 度；以及 至少一被動元件，設置於該基板之該第一表面上。 19·如申請專利範圍第18項所述之多晶*封袭結構， 其中該多晶片封裝結構係電性連接於一手機芝栽板上： 20·如申請專利範圍第19項所述之多晶片封裝結構， 其中該載板為印刷電路板(printed circuit board ; pcb)、軟 性印刷電路板（Flexible printed circuits ; FPC)或主機板。 '! · ! 21·如申請專利範圍第18項所述之多晶片封裝結構， 其中該被動元件係選自由電容、電感及電阻蛴組成之一族 群。 、 22·如申請專利範圍第18項所述之多晶片封裝結構， 其中該第一接線和該第二接線為金線、銀線、鋼線或鋁線。 23·如申請專利範圍第18項所述之多晶片封裝結構， 17 M338433 其中該第一封膠體和該第二封膠體之材料為環 PMMA、聚碳酸酯（p〇lycarb〇nate)或矽膠。 24·如申請專利範圍第18項所述之多晶片封裝結構， 其中該銲球之材料係選自由錫、鋁、鎳、銀、， 合金所組叙鱗。 1及其 25·如申請專利範圍第18項所述之多晶片封裝結構， 其中該基板更具有一環階梯部，其凹設於該開口内，且連 通於該第一表面，該動態隨機存取記憶體晶片係卡掣於該 環階梯部。 、~ 26·如申請專利範圍第a項所述之多晶片封裝結構， 其中該基板更具有一環階梯部，其凹設於該開口内，且位 於該第二表面上，該第二接線係電性連接於該動態隨機存 取記憶體晶片與該環階梯部上。 27· —種多晶片封裝結構，至少包含： 一基板，具有一第一表面、一第二表面及一開口，其 中該開口係開設於該第一表面和該第二表面之間； 一動態隨機存取記憶體（DRAM)晶片，設置於該基板之 該第一表面上，且該晶片之該主動面係面向該開口； 一快閃§己憶體（Flash Memory)晶片，設置於該動態隨機 存取記憶體（DRAM)晶片上； 一控制晶片，設置於該基板之第一表面上； 18 M338433 至少一第一接線，電性連接於該快閃記憶體晶#與該 基板之間，以及電性連接於該控制晶片與該基板之間； 至少一第二接線，經由該開口來電性連接於該動態隨 機存取記憶體晶片之另一側與該基板之該第$表面； I · 至少一第三接線，電性連接於該控制晶片與該基板之 間； 一第一封膠體，形成於該基板之該第一表面上，並包 覆該動態隨機存取記憶體晶片、該快閃記憶體晶片、該控 藝制晶片及該些第一接線； 一第二封膠體，形成於該基板之該開口中，並包覆該 開口和該第二接線； 複數個錫球，設置於該基板之該第二表面上，其中該 些錫球在該第二表面上之高度係高於該第二封膠體之高 度；以及 ! 至少一被動元件，設置於該基板之該第一表面上。 I j 19M338433 IX. Patent Application Range: 1 . A multi-chip package structure comprising at least: a substrate having a first surface, a second surface and an opening, wherein the opening is formed on the first surface and the second surface a dynamic random access memory (DRAM) chip disposed on the first surface of the substrate, and one of the active random access memory chips facing the opening; a flash memory ( a flash memory is disposed on the DRAM chip; at least one first wire is electrically connected between the flash memory chip and the substrate; and at least a second wire is electrically connected via the opening Connecting the active surface of the DRAM chip to the second surface of the substrate; a first encapsulant formed on the first surface of the substrate and covering the dynamic random access memory a wafer, the flash memory chip and the first wiring; a second encapsulant formed in the opening of the substrate and covering the opening and the second wiring; and plural The solder balls are disposed on the second surface of the substrate, wherein the height of the solder balls on the second surface is higher than the height of the second encapsulant. In the same package structure, the multi-wafer described in claim 1 includes at least: 13 M338433 control chip disposed on the flash memory chip and electrically connected to the photo-board. 3. The multi-chip package structure of claim 2, wherein the control wafer and the substrate are electrically connected by the first wiring. 4. The multi-chip package structure of claim 1, further comprising: a control wafer disposed on the first surface of the substrate and electrically connected to the substrate. 5. The multi-chip package structure of claim 4, further comprising: at least a third wire electrically connected between the control wafer and the substrate. The multi-chip package structure of claim i, wherein the solder balls have a height on the second surface that is at least 0.1 mm above the height of the second seal. 7. The multi-chip package structure of claim 1, wherein the multi-chip package structure is electrically connected to a carrier of a mobile phone. 8. The multi-chip package structure of claim 7, wherein the carrier board is a printed circuit board (PCB), a flexible printed circuit board (FPC) or a motherboard. 9. The multi-chip package structure of claim 1, wherein the substrate is provided with at least one passive component. 10. The multi-chip package structure of claim 9, wherein the passive component is selected from the group consisting of a capacitor, an inductor, and a resistor. 11. The multi-chip package structure of claim 9, wherein the passive component is disposed on the first surface of the board by surface adhesion (SMT). 12. The multi-chip package structure of claim 9, wherein the passive component is embedded in the substrate. The multi-chip package structure of claim 1, wherein the first wire and the second wire are gold wire, silver wire, steel wire or wire. The multi-chip package structure of claim 1, wherein the first sealant and the second sealant are epoxy resin, PMMA, polycarbonate (p〇lycarb〇nate) or silicone rubber. . The multi-chip package structure according to claim 1, wherein the material of the solder ball is selected from the group consisting of tin, aluminum, aluminum, silver, steel, indium and 15 M338433 alloy thereof. The multi-chip package structure of claim 1, wherein the board further has a stepped portion recessed in the opening, and the surface of the dynamic random access memory chip is cut into the The multi-chip package structure as described in claim 1, wherein the substrate further has a stepped portion recessed in the opening and located on the second surface, the second wiring system is electrically Connected to the dynamic random access § memory wafer and the ring step. A multi-chip package structure comprising: a substrate having a first surface, a second surface, and a port, wherein the opening is formed between the first surface and the second surface, a random access memory (DRAM) chip disposed on the first surface of the substrate, wherein the active access surface of the memory chip faces the opening; - a flash memory chip, set On the DRAM chip, a control chip is disposed on the flash memory chip; a plurality of first-wirings are electrically connected between the flash memory crystal and the substrate And electrically connected between the control wafer and the substrate; at least the second connection is electrically connected to the other side of the DRAM chip and the second surface of the substrate via the opening; a first sealing body is formed on the first surface of the substrate, and covers the dynamic random access memory chip, the flash memory chip, the control chip and the first wires; a sealing body formed in the opening of the substrate and covering the opening and the second wire; a plurality of solder balls disposed on the second surface of the substrate, wherein the solder balls are on the second surface The height is higher than the height of the second encapsulant; and at least one passive component is disposed on the first surface of the substrate. 19. The polycrystalline* encapsulation structure according to claim 18, wherein the multi-chip package structure is electrically connected to a mobile phone board: 20· as described in claim 19 The chip package structure, wherein the carrier board is a printed circuit board (pcb), a flexible printed circuit (FPC) or a motherboard. The multi-chip package structure of claim 18, wherein the passive component is selected from the group consisting of a capacitor, an inductor, and a resistor. The multi-chip package structure of claim 18, wherein the first wire and the second wire are gold wire, silver wire, steel wire or aluminum wire. The multi-chip package structure as described in claim 18, 17 M338433, wherein the first sealant and the second sealant are made of a ring PMMA, a polycarbonate (p〇lycarb〇nate) or a silicone. The multi-chip package structure of claim 18, wherein the material of the solder ball is selected from the group consisting of tin, aluminum, nickel, silver, and alloy. The multi-chip package structure of claim 18, wherein the substrate further has a ring step portion recessed in the opening and communicating with the first surface, the dynamic random access The memory chip is clamped to the step of the ring. The multi-chip package structure as described in claim a, wherein the substrate further has a stepped portion recessed in the opening and located on the second surface, the second wiring system is electrically The connection is performed on the dynamic random access memory chip and the step of the ring. The multi-chip package structure includes at least: a substrate having a first surface, a second surface, and an opening, wherein the opening is formed between the first surface and the second surface; An access memory (DRAM) chip is disposed on the first surface of the substrate, and the active surface of the wafer faces the opening; a flash memory CMOS memory is disposed at the dynamic random Accessing a memory (DRAM) wafer; a control wafer disposed on the first surface of the substrate; 18 M338433 at least a first wiring electrically connected between the flash memory crystal and the substrate, and Electrically connected between the control chip and the substrate; at least one second wire is electrically connected to the other side of the DRAM chip and the first surface of the substrate via the opening; I · at least a third wiring electrically connected between the control wafer and the substrate; a first encapsulant formed on the first surface of the substrate and covering the dynamic random access memory chip, the flash memory a body wafer, the control wafer and the first wiring; a second encapsulant formed in the opening of the substrate and covering the opening and the second wiring; a plurality of solder balls disposed on the substrate On the second surface, the height of the solder balls on the second surface is higher than the height of the second encapsulant; and at least one passive component is disposed on the first surface of the substrate. I j 19
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