TWI238509B - Micro-electronic package structure - Google Patents

Micro-electronic package structure Download PDF

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Publication number
TWI238509B
TWI238509B TW093121847A TW93121847A TWI238509B TW I238509 B TWI238509 B TW I238509B TW 093121847 A TW093121847 A TW 093121847A TW 93121847 A TW93121847 A TW 93121847A TW I238509 B TWI238509 B TW I238509B
Authority
TW
Taiwan
Prior art keywords
layer
metal plate
conductive
microelectronic
microelectronic structure
Prior art date
Application number
TW093121847A
Other languages
Chinese (zh)
Other versions
TW200605306A (en
Inventor
Chu-Chin Hu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW093121847A priority Critical patent/TWI238509B/en
Application granted granted Critical
Publication of TWI238509B publication Critical patent/TWI238509B/en
Publication of TW200605306A publication Critical patent/TW200605306A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A micro-electronic package structure is proposed, wherein at least a semiconductor chip is disposed on a metal plate via a heat-conductive adhesive for dissipating the heat produced from the chip. At least an insulating layer and at least a circuit layer are formed on the metal plate, wherein the circuit layer is electrically connected to the chip via conductive structures. At least an opening is formed in the metal plate for embedding passive components, which are electrically connected to the circuit layer via conductive structures formed in the insulating layer. A plurality of conductive elements are formed on the circuit layer for providing the chip disposed on the metal plate to connect outside directly.

Description

1238509 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種微電子構裝結構，尤指一種同時 整合有散熱件、半導體晶片、線路結構及被動元件之微電 子構裝結構。 【先前技術】 隨著半導體封裝技術的演進，半導體裝置 (Semiconductor device)已開發出不同的封裝型態，其中球 柵陣列式（Ball grid array, BGA)為一種先進的半導體封裝 技術’其特點在於採用一基板來安置半導體晶片，並利用 自動對位（Self-alignment)技術以於該基板背面植置複數個 成柵狀陣列排列之銲球（s〇lder ball)，使相同單位面積之半 導體晶片承載件上可以容納更多輸入/輸出連接端（1/〇 connection)以符合高度集積化（Integrati〇n)之半導體晶片 所需，以藉由此些銲球將整個封裝單元銲結並電性連接至 外部之印刷電路板。 、然而，上述封裝件實際執行卻會產生許多問題：首先， 因為半導體晶片上之電子元件及電子電路之密度高集積 化:其運作產生之熱量多，如不及時將半導體晶片產生之 熱量有效逸散，將嚴重縮短半導體晶片之性能及壽命；再 者，该封裝件缺乏有效遮蔽效果（Shielding)，容易受到外 界電磁及雜訊之干擾。 曰 月《閱第1圖，為解決上述問題，一種習知之底穴置 晶型球拇陣型式封裝結構（Cavity-down ball grid array， 18041 5 1238509 CDBGA)，係為一種特殊形態的球栅陣列式封裝結苴 = =板形成有一開1下底穴，並：半導體 曰曰片以倒置方式安置於該底穴之中。此習知之 封裝結構10至少包含：一基板n、一散熱件1 半導體晶片！3、複數條銲線14、一封裝膠體 ㈣ 銲球16。 複數 該基板η具有一正面lla和一背面llb，且形成有至 少-開孔111;該散熱件12的材質為一例如為銅之 性材料，且其_合至該基板11的正Φ lla上，以使㈣ 基板11的開？L 111形成一開口朝下之底穴；該半導體晶片 13具有-電性作用面i 3a(Aetive surfaee)和—非電性作曰曰用 面13b(lnactive surface)。於組裝過程中，係 1 一置方式安置於基板η的開孔⑴卜並：其二曰電月 性作用13b黏結至散熱件12，然後，進行一銲線製程，藉 以利用If線14將半導體晶片13電性連接至該基板11表面 ，電性連接塾’接著進行—封裝膠體製程，藉此而形成封 裝谬體15來完全包覆半導體晶13片和銲線】4，之後，進 =一植球程序，藉此而於基板n的背面Ub上植置複數個 、干求1 6此即兀成该底穴置晶型球柵陣列式（cdBga)封裝 結構1 0。 h上述封裝單元耗得以湘該散熱件解決其散熱與遮 蔽效果（Shielding) ’但-般為能夠將該銲球順利銲結至外 部印，電路板，該銲球配置高度必須大於該料弧所佔高 度，嚴重影響該基板之佈局性（R〇utabiHty)與銲球配置高 1238509 二：另一方面，由於晶片周圍之線弧密度極高，極易造成 =線不慎觸接產生短路⑽⑽），增加打線作㈣難度；再 行模壓封膠製程時，係將完成佈設晶片與導線之 二且ΐ 裝模具中’俾供一環氧樹脂物哺料注入 杈二中而形成用以包覆該晶片與銲線之封裝移體，然而， 於貫際製程中，該模具由於受限於半導體封裝件之設叶， 尺寸與錢位置勢必有所差異而造成無法緊密央 俟注人樹㈣料時’容易導致封裝膠體溢膠至 ，基板表面，非但降低該半導體封裝件之表面平整度與美 觀’同時更可能污染該基板上後續欲植置銲球之鲜塾位 置’而影響該半導體封裝件之電性連接品質；況且，該樹 月曰旨=:主勝時乃為一流體，於注入該模穴時將對該完成 曰曰片與基板電性連接之導線產生模流壓力，若注入速度控 制不當時’即會因該壓力衝擊導線’使導線產生碰“ 生紐路問題，嚴重影響該半導體封裝件之生產品質及產品 信賴度。 此外，前述封裝單元中為減低半導體晶片運作時產生 之雜訊’通常會在基板線路佈局表面配置許多供電容元件 (capacitor)銲接之銲墊，導致基板線路佈局空間更為不 f，再者為能夠將該鲜球順結至外部㈣電路板，該 銲球配置高度必須大於該電容元件所佔高度，嚴重影響該 基板之佈局性（R0utability)與銲球配置高度；另一方面:由 於半導體晶片周圍之線弧密度極高，極易造成銲線不慎觸 接到電容元件產生短路（Short)，增加打線作業困難度。 18041 7 1238509 f造=生2半導體裝置之製程’係首先由晶片承載件 衣l菜者生產適用於該半導體裝置之 或導線架，之後，再將兮此s 载件，如基板 去進杆署日 再將片承载件交由半導體封裝業 者進仃置日日、模壓、以及植球等 y、 戶端所需之電子功能之半導體裝置。二:;及二完成客 者（即—包含有晶片承载件製造業者與半導體縣業者t程因業 程中不僅步驟繁瑣且界面整合不易，況 ’右各戶端欲進行變更功能設計時， 層面拙：备 ^文·更興整合 夏雜’亦不符合需求變更彈性與經濟效益。 2 ’如何藉由簡單製程、花費較少成 決+導體裝置之散熱、電磁干擾叫解 製程界面整合等問題， 、、、電性品質與 【發明内容】 ㈣欠解決的課題。 裎供參=以上所述習知技術之缺點，本發明之主要目的係 ，：：種微電子構裝結構，俾同時整合晶片承载件之： 與半導體封農技術之製程，以提供客 J =造 同時得以簡化半導體業者製程與界面整合問題Γ 5 爭性， 1遠再一目的係提供一種微電子構裝結構，俾有 體裝f:磁遮蔽效果，避免受外界電磁及雜導 β、，毛月之另-目的係提供一種微電子構裳 提供半導體晶片直接電性s 。冓，係可 質。 *电度*通至外部，藉以提升電性品 本表月之X目的係提供—種微電子構裝結構，避免 1804] 8 1238509 :=晶片電性導接至晶片承载件時所需複雜製程及設備 有另—目的係提供—種微電子構裝結構，以 有效、、.“被動元件但不致影響線路佈局空間及*活性。 免羽又另—目的係'提供—種微電子構^結構，避 之模壓與植球作業中所產生之溢膠與佈設 =問通，俾有效提昇半導體裝置之生產品質及產品信賴 ，=揭及其它目❺’本發明之微電子構裝結構，主 4括开>成有至少一開口之金屬才反；至少一半導體晶 片，係接置於該金屬板上；至少一 面接置有半導體晶片之全屬板i.r 成於該表 在w .月孟屬板上，至少—圖案化線路層， “絕：：：緣！上，且該圖案化線路層係藉由複數形成 及接罟於之導電結構以電性連接至該半導體晶片；以 =接置於該絕緣層上且收納於該金屬板開口中之被動元 其^該半導體晶片具有—電性作用面及-相對之另__ 表面’遠晶 >；之電性作用面具有複數電性連接墊，且該曰 片係可藉由導熱膠黏層而以其另一表面接置於該金屬：曰曰 ’俾糟由該金屬板有效傳遞熱量，另該半導體晶片係可 過其電性連接塾以及複數形成於絕緣層中之導電結構 (‘电凸塊或導電盲孔等），而延伸出線路結構丨另該 收=金屬板中之被動元件，係可藉由形成於該絕緣層中 之導電結構（例如電料通孔），以電性連接至該絕緣層日另 一側之圖案化線路層。 18041 9 1238509 >此外，本發明之微電子構装結構復可包含··一形成於 f圖案化線路層上之圖案化拒銲層，該圖案化拒銲層具有 複數開口以顯露出部分圖案化線路層；以及複數導電元 件係元成於外露出該圖案化拒鮮層之圖案化線路層上。 ^中3拒‘層可例如為綠漆，而該導電元件可例如為鲜 球、銲柱及導電凸塊等，藉以提供接置於該金屬板上之半 導體晶片直接導通至外界。 囚此 不努明之微電子構裝結構係提供至少一半導體 =透過-導熱勝黏層接置於一金屬板上，以有效利用該 1屬板料散熱件來逸散該半導體晶片於運作時產生之熱 '’並可藉由該金屬板提供該半㈣裝置電磁遮蔽效果了 半導合有半導體晶片與承載件，俾可縮短 紅衣 i體厚度’以達輕薄短小目的；此外，本發 明之微電子構裝結構係於晶片上直接外接出線路^ 路結構上植設有多數之導電元件，以提供該構裝 ::接電性連接至外部裝置；另本發明之微電子構裝姓 =亦：將被動元件設置於絕緣層之—侧並收納於金屬板： 二 置空間，同時該被動元件係透過設置於 …U層内之h結構而得與半導體晶片電性連接，夢以 減少雜訊與電磁干擾之產生，再者，該^ 實際需求變更電性功能，-需如同習知半導體裝置 基板佈滿㈣線路之-側接置㈣元件時 間及靈活性，㈣需在如同習知半導體裝置在基板中^ 族埋被動元件時必需針對不同需求電性特性即必須重= 18041 10 1238509 計該基板，造成f造成本的大幅提升，亦 的困擾與材料庫存成本的增加等問題。0 4官理 件、=2:明：微電子構装結構係可藉由整合該散-件、體晶片、線路結構及被動元件，進上 片承載件之製造與半導體封裝技術之製程 ^^曰 較大需求彈性以及簡化半導體 平、各戶褊 同時避免習知半導體晶片‘f 與界面協調問題， 至基板，甚而外部電子,4方式电性導接 題。 电子裒置蚪所需複雜製程及設備等問 【實施方式】 為使本發明之目的、特徵及功效， 料同，_合詳細㈣及圖辆加㈣如后。=瞭^ ::::以多種形式實施之，以下所述係為本發明之 她恕樣’而非用以限制本發明之範圍，合先敛明。、 之刊=Γ2Α，2Β圖’係為本發明之微電子構裝結構 之剖面及底面示意圖。 僻 如圖所示，本發明之微電子構裝結構，主要 :形成有至少一開口 210之金屬板21;至少一接置師全 反2^之半導體晶片22;—形成於該表面接置有半導 曰曰片22之金屬板21上之絕緣層23;以及至少一 該絕緣層23上之圖案化線路層24,且該圖荦化後踗； # ^ , /圆茶化線路層24 成於該絕緣層23中之導電結構240以電性連 / + ¥體晶片22，以及接置於該絕緣層23 於該金屬板21開口 210中之被動元件25。 收、·内 18041 11 1238509 。亥至屬板21之材負可為_具高導熱係數之金屬鋼，而 該半導體晶片22具有一電性作用面…及一相對之另—表 面22b，違半導體晶片之電性作用面22&具有複數電性連 接墊220 L亥日日片22係可藉由—例如銀谬之導熱膠黏層 26而以其另表面22b接置於該金屬板21上，俾透過該 導熱膠黏層26與該金屬板21所構成的散熱途徑 (The_lly _ductive p，直接逸散該半導體晶片u運作 所產生之熱里’並可藉由該金屬板21以提供電磁遮蔽 (Shielding)效果。 該絕緣層23可例如為環氧樹脂（Epoxy resin)、聚乙萨 胺（P〇lyimide)、氰脂（Cyanate 咖）、碳纖維（Carbon - ujinomoto Buil“p Film，曰商味之素公司出 產）、雙順丁烯二酸酿亞胺/三氮_τ， 或混合環氧樹脂與玻璃纖維等材質所構成。此 外’该絕緣層2 3可為显js πν斗、, 屬m ，’、、 _亦或以稷數層型式先後形成於金 =案化線路層24係可透過電鍍、無電鑛或沈積 ^成於該絕緣層23上’此外’該圖案化線路層24係可 :由：：形成於該絕緣層23中之例如導 構240加以電性導接至該半導體晶片：： 塾220以及：ΓΡ’該半導體晶片22係可透過其電性連接 孔等導2士1形成於絕緣層23令例如導電凸塊或導電盲 作時:圖 成卞化線路層24係非以一層或本圖所示之二層為 18041 12 1238509 限，而可擴充至多層以上。 屬板i所t件25係接置於該絕緣層23上且收納於該金 、叹之開口 210中，且該被動元件係可藉由形成 心生：=中例如電錢導通孔(p T H)之導電結構2 7，藉以 、+V肽曰曰片22電性導接，藉以提升電性品質。 此：田如第2q2D圖所示，本發明之微電子構裝結 :二=收納被動元件25之金屬板21開口 210形式 加之外緣厂金屬板210内外，亦可直接設置於該金屬板 含有另=閱弟3圖所示’本發明之微電子構裝結構復包 二圖案化線路層24上之圖案化拒銲層28， 路；“干層28具有複數開口以顯露出部分圖案化線 :，以及形成於外露出該圖案化拒銲層28之圖案化 為^24上之複數導電元件29。其中該拒銲層μ tr:該導電元件29可例如為鲜球、銲柱或導電凸塊· :通:::供接置於該金屬板21上之半導體晶片靖 雕曰=，本發明所揭露之微電子構裝結構主要係將半導 =曰片=過導熱膠黏層而接置於金屬板上，以有效利用該 :屬板作為散熱件來逸散該半導體晶片於運作時產生之熱 藉由該金屬板提供電磁遮蔽效果，且該構裝結構 本正口有半導體晶片與晶片承載件，將可縮短整體厚 度’以達輕薄短小目的；此夕卜， 卜本發明之微電子構裝結構 1238509 設置導直接：接出線路結構，並可在該線路結構上 部裳置.另該構襄結構得以直接電性連接至外 於絕緣層電子構裝結構亦可將被動元件設置 =之側並收納於金屬板之開口中，以節省 ::該被動元件係透過設置於：： 二再者，皮動元件係可因應實際需求變更電性::: 接習知半導體裝置直接在基板佈滿訊號線路之：侧 =元件時，影響線路佈局空間及靈活性，二： ==半導體裝置在基板中直接嵌埋被動 針對不同電性需求來重新設計誃了义須 幅提升，以及物粗;土 w成衣&成本的大 此外士擾與材料庫存成本增加等問題。 半導體ίΓΓ電子構裝結構係可藉由整合該散熱件、 日日片線路結構及被動元件，進而同時姓人s1238509 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a microelectronic structure, especially a microelectronic structure that integrates a heat sink, a semiconductor wafer, a circuit structure, and a passive component at the same time. [Previous technology] With the evolution of semiconductor packaging technology, semiconductor devices have developed different packaging types. Ball grid array (BGA) is an advanced semiconductor packaging technology. Its characteristics are: A substrate is used to set a semiconductor wafer, and a plurality of solder balls arranged in a grid array are planted on the back of the substrate by using self-alignment technology to make semiconductor wafers of the same unit area The carrier can accommodate more input / output connections (1/0 connection) to meet the needs of highly integrated semiconductor chips, so that the entire package unit can be soldered and electrically connected by these solder balls. Connect to an external printed circuit board. However, the actual implementation of the above-mentioned package will cause many problems: First, because the density of electronic components and electronic circuits on the semiconductor wafer is high: the heat generated by its operation is large. If the heat generated by the semiconductor wafer is not efficiently dissipated in time, Dispersion will severely shorten the performance and life of the semiconductor wafer; furthermore, the package lacks effective shielding effect and is susceptible to external electromagnetic and noise interference. "Yueyue" See Figure 1. In order to solve the above problem, a conventional Cavity-down ball grid array (18041 5 1238509 CDBGA) package structure is a special form of ball grid array. In the package type, the bottom plate is formed with a bottom hole, and the semiconductor chip is placed in the bottom hole in an inverted manner. The conventional packaging structure 10 includes at least: a substrate n, a heat sink 1 and a semiconductor wafer! 3. A plurality of bonding wires 14, a package gel ㈣ solder ball 16. The substrate η has a front surface 11a and a back surface 11b, and is formed with at least-openings 111; the material of the heat sink 12 is a material such as copper, and it is coupled to the positive Φ lla of the substrate 11 To make the substrate 11 open? L 111 forms a bottom hole with an opening facing downward; the semiconductor wafer 13 has-an electrically active surface i 3a (Aetive surfaee) and-a non-electrically active surface 13b (lnactive surface). During the assembly process, system 1 is arranged on the openings of the substrate η in one way: the second is that the electrical function 13b is bonded to the heat sink 12, and then a bonding process is performed to use the If line 14 to semiconductors The chip 13 is electrically connected to the surface of the substrate 11, and the electrical connection is then performed—the encapsulation process, thereby forming a package body 15 to completely cover the 13 semiconductor crystals and the bonding wires] 4. The ball-implantation procedure is used to plant a plurality of substrates on the back surface Ub of the substrate n to obtain 16. This results in the bottom-cavity crystal ball grid array (cdBga) package structure 10. h The above-mentioned packaging unit can use the heat sink to solve its heat dissipation and shielding effect. However, in general, the solder ball can be successfully bonded to an external printed circuit board. The height of the solder ball must be greater than that of the material arc. Occupy height, which seriously affects the layout of the substrate (RoutabiHty) and the solder ball configuration is 1238509 high Second: On the other hand, because the density of the line arc around the wafer is extremely high, it is very easy to cause = the line accidentally touches and generates a short circuit ⑽⑽) To increase the difficulty of wire bonding; when the molding and sealing process is performed, the wafer and the wire are laid two and the mold is filled with an epoxy resin feeding material into the fork two to form a coating Removal of the package of the chip and the wire. However, in the inter-process, the mold is limited by the leaves of the semiconductor package. The size and position of the mold will inevitably be different. 'It is easy to cause the packaging colloid to overflow to the substrate surface, which not only reduces the surface flatness and aesthetics of the semiconductor package', but is also more likely to contaminate the fresh spot of subsequent solder balls on the substrate. The quality of the electrical connection of the semiconductor package; Moreover, the purpose of the tree = = when the main win is a fluid, when the cavity is injected, a mold current will be generated to the wire that electrically connects the completed wafer to the substrate. Pressure, if the injection speed is not properly controlled, 'the pressure will impact the wire', which will cause the wire to run into a "new road" problem, which will seriously affect the production quality and product reliability of the semiconductor package. In addition, the aforementioned packaging unit is to reduce the semiconductor The noise generated during the operation of the chip usually places a lot of pads on the surface of the circuit layout of the substrate for the capacitors (capacitors) to solder, which results in a less space for the circuit layout of the substrate. Furthermore, the fresh ball can be knotted to the outside. ㈣For circuit boards, the height of the solder ball configuration must be greater than the height occupied by the capacitive element, which seriously affects the layout of the substrate (Routability) and the height of the solder ball configuration. On the other hand: due to the extremely high line arc density around the semiconductor wafer, It is easy to cause the solder wire to accidentally touch the capacitive element to cause a short circuit (Short), which increases the difficulty of wire bonding operation. 18041 7 1238509 f == 2 semiconductor device system 'Firstly, the wafer carrier is used to produce the semiconductor device or lead frame, and then the carrier, such as the substrate, is placed on the pole and then the wafer carrier is handed in to the semiconductor packaging industry. Set up the semiconductor device with electronic functions required by the client, such as molding, molding, and ball planting, etc. II :; and II completed customers (that is, including wafer carrier manufacturing manufacturers and semiconductor county operators) Not only the steps are tedious and the interface integration is not easy. When the right clients want to change the function design, the level is awkward: preparing the text and more integrated Xia Za. It also does not meet the needs to change the flexibility and economic benefits. 2 'How to make it simple Manufacturing process, less cost + heat dissipation of conductor device, electromagnetic interference is called process interface integration, etc., electrical quality, and [contents of the invention] ㈣ unsolved issues.裎 For reference = the disadvantages of the conventional technology described above, the main purpose of the present invention is :: a microelectronic structure, and simultaneously integrate the wafer carrier: and the process of semiconductor packaging technology to provide customers J = At the same time, it can simplify the process and interface integration of the semiconductor industry. Γ 5 is competitive. The goal is to provide a microelectronic structure, which has a body f: magnetic shielding effect, to avoid being affected by external electromagnetic and miscellaneous conductance β ,, Mao Yuezhi's other purpose is to provide a microelectronic structure to provide direct electrical conductivity of semiconductor wafers. Alas, Department of quality. * Electricity * To the outside, in order to improve the electrical product, the purpose of the month X is to provide a kind of microelectronic structure to avoid 1804] 8 1238509: = complicated process required when the chip is electrically connected to the chip carrier And the equipment has another-the purpose is to provide-a kind of microelectronic structure, which is effective, ". Passive components but does not affect the layout space and * activity. Overflow of glue and layout generated during the avoidance of molding and ball-planting operations = asking questions, effectively improving the production quality of semiconductor devices and product trust, = revealing and other objectives, "Microelectronic structure of the present invention, main 4 Enclose the metal with at least one opening before reversing; at least one semiconductor wafer connected to the metal plate; at least one side of the metal plate on which the semiconductor wafer is connected is formed on the watch. On the board, at least-the patterned circuit layer, "Absolutely ::: edge! And the patterned circuit layer is electrically connected to the semiconductor wafer by a plurality of conductive structures formed and connected to it; a passive element placed on the insulating layer and received in the opening of the metal plate ^ The semiconductor wafer has an -electrically active surface and -opposite another __ surface 'telecrystalline>; the electrically active surface has a plurality of electrical connection pads, and the chip system can be formed by a thermally conductive adhesive layer. The other surface is connected to the metal: "俾" is used to effectively transfer heat from the metal plate, and the semiconductor wafer can be electrically connected through it and a plurality of conductive structures formed in the insulating layer ('electric bumps' Or conductive blind holes, etc.), and extend the circuit structure 丨 Another passive element in the metal plate can be electrically connected to the conductive structure (such as electrical material through hole) formed in the insulating layer The insulating layer is a patterned circuit layer on the other side. 18041 9 1238509 > In addition, the microelectronic structure of the present invention may include a patterned solder resist layer formed on the f-patterned circuit layer, the patterned solder resist layer having a plurality of openings to expose part of the pattern A patterned circuit layer; and a plurality of conductive elements formed on the patterned circuit layer exposing the patterned antireflective layer. The ^ 3 layer can be, for example, a green paint, and the conductive element can be, for example, a fresh ball, a soldering post, and a conductive bump, so as to provide a semiconductor chip directly connected to the metal plate to the outside. The unknown microelectronic structure structure provides at least one semiconductor = through-thermal conductive adhesive layer connected to a metal plate, so as to effectively use the 1 sheet heat sink to dissipate the semiconductor chip during operation. It can provide the electromagnetic shielding effect of the semi-conductor device through the metal plate. The semiconducting semiconductor chip and the carrier are semi-conducted, and the thickness of the red body can be shortened to achieve the purpose of lightness, thinness, and shortness. In addition, the invention The microelectronic structure is directly connected to an outgoing line on the chip. A plurality of conductive elements are planted on the circuit structure to provide the structure: electrically connected to an external device; and the microelectronic structure of the present invention is also = : Passive components are placed on the side of the insulating layer and housed in a metal plate: Two spaces, meanwhile, the passive components are electrically connected to the semiconductor wafer through the h structure arranged in the U layer, dreaming to reduce noise And the generation of electromagnetic interference, in addition, the actual needs to change the electrical functions,-as in the conventional semiconductor device substrate full of circuits-side-mounted components time and flexibility, do not need to Body means in the substrate when the Group ^ embedded passive components required for the electrical characteristics of the different needs which must re = 18041101238509 meter of the substrate, resulting in f resulting in significantly improved according to the present, is also plagued with increasing material inventory costs and other issues. 0 4 official parts, = 2: Ming: The microelectronic structure structure can be integrated into the manufacturing process of the on-chip carrier and the semiconductor packaging technology process by integrating the loose parts, body wafers, circuit structures and passive components ^^ That is, greater demand elasticity and simplified semiconductor flatness, households while avoiding the conventional semiconductor wafer 'f and interface coordination issues, to the substrate, and even external electronics, 4-way electrical conduction problems. [Complex process and equipment required for electronic device installation] [Embodiment] In order to make the purpose, characteristics and effects of the present invention, the same, detailed details and drawings are added later. = 了 ^ ::: Implemented in various forms, the following description is forgiveness of the present invention 'and is not intended to limit the scope of the present invention. The publication of ZHI = Γ2A, 2B is a schematic diagram of the cross section and the bottom surface of the microelectronic structure of the present invention. As shown in the figure, the microelectronic structure of the present invention mainly includes: a metal plate 21 formed with at least one opening 210; at least one semiconductor wafer 22 having a reverse reflection 2 ^; formed on the surface and having The insulating layer 23 on the metal plate 21 of the semiconducting sheet 22; and at least one patterned circuit layer 24 on the insulating layer 23, and the figure is transformed; # ^, / 圆 茶 化 电路 层 24 成The conductive structure 240 in the insulating layer 23 is electrically connected to the body chip 22 and the passive element 25 connected to the insulating layer 23 in the opening 210 of the metal plate 21. Close, · In 18041 11 1238509. The material of the helium plate 21 may be metal steel with high thermal conductivity, and the semiconductor wafer 22 has an electrical active surface ... and an opposite surface 22b, which violates the electrical active surface 22 of the semiconductor wafer. The plurality of electrical connection pads 220 L of the Haierian film 22 can be connected to the metal plate 21 with the other surface 22b by, for example, the silver heat conductive adhesive layer 26, and through the heat conductive adhesive layer 26 The heat dissipation path (The_lly_ductive p) formed with the metal plate 21 directly dissipates the heat generated by the operation of the semiconductor chip u, and the metal plate 21 can be used to provide an electromagnetic shielding effect. The insulating layer 23 Examples include Epoxy resin, Polyimide, Cyanate coffee, Carbon fiber (Carbon-ujinomoto Buil "p Film," manufactured by Ajinomoto Co., Ltd.), Shuangshunding Arylene diimide / triazine_τ, or a mixture of epoxy resin, glass fiber, and other materials. In addition, 'the insulating layer 23 may be a js πν bucket ,, belongs to m,' ,, _ or稷 Several layers are successively formed in gold = cased circuit layer 24. Electroless deposits or deposits are formed on the insulating layer 23, and in addition, the patterned circuit layer 24 can be electrically connected to the semiconductor wafer by: such as a conductive structure 240 formed in the insulating layer 23 ::塾 220 and: ΓΡ ′ The semiconductor wafer 22 can be formed on the insulating layer 23 through its electrical connection holes and the like. When the conductive bump or conductive blind operation is performed, for example, the circuit layer 24 is not a layer. Or the two layers shown in this figure are limited to 18041 12 1238509, and can be expanded to more than multiple layers. The pieces 25 of the board i are connected to the insulating layer 23 and housed in the gold and sigh openings 210, and The passive component can be formed by forming a conductive structure 27 such as an electrical money via (p TH), by which the + V peptide 22 is electrically connected to improve the electrical quality. This: Tian as shown in Figure 2q2D, the microelectronic structure of the present invention is as follows: two = the metal plate 21 receiving the passive element 25 is in the form of an opening 210 plus the outer edge metal plate 210 inside and outside, and can also be directly set on the metal plate containing another = Figure 3 shows the picture on the patterned circuit layer 24 of the microelectronic structure structure package 2 of the present invention "The dry solder layer 28 has a plurality of openings to expose part of the patterned lines :, and a plurality of conductive elements 29 formed on the outer surface of the patterned solder resist layer 28 patterned to ^ 24." The solder resist layer μ tr: the conductive element 29 may be, for example, a fresh ball, a solder post, or a conductive bump. ::::: Semiconductor wafer for receiving and placing on the metal plate 21, as disclosed in the present invention The microelectronic structure is mainly composed of semiconducting = chip = super thermally conductive adhesive layer and placed on a metal plate to effectively use this: the metal plate as a heat sink to dissipate the heat generated by the semiconductor wafer during operation The metal plate provides an electromagnetic shielding effect, and the structure has a semiconductor wafer and a wafer carrier at the front of the structure, which can shorten the overall thickness to achieve lightness, shortness, and shortness; furthermore, the microelectronic structure of the present invention 1238509 Direct installation: connect the circuit structure and place it on the upper part of the circuit structure. In addition, the structure can be directly and electrically connected to the external insulation electronic structure. The passive component can also be placed on the side of = In the opening of the metal plate, Saving :: The passive component is installed in :: Secondly, the electrical component can be changed according to the actual needs. ::: It is known that when a semiconductor device is directly covered with signal lines on the substrate: side = component, the impact Circuit layout space and flexibility, two: == semiconductor devices are directly embedded in the substrate, passively redesigned for different electrical requirements. Problems with increased material inventory costs. The semiconductor ΓΓ electronic electronic structure can integrate the heat sink, the Japanese-Japanese chip circuit structure, and the passive components, so as to simultaneously name people s

造料導體料技術之製程，俾提供二二L 或置晶4方式電性導接至基 甚而外#電子裝置時所f複雜製程及設備等問題。 以上所述之具體實施態樣，僅係用以例釋 而非用以限定本發明之可實叫在未脫:: x晏之精神與技術範疇下，任何運用本發明 二容而完成之等效改變及修飾，均仍應為下述之申請專利 乾圍所涵蓋。 【圖式簡單說明】 18041 14 1238509The manufacturing process of the conductive material technology provides two or two L or crystal 4 ways to electrically connect to the basic and even external #electronic devices to deal with complex processes and equipment problems. The specific implementation aspects described above are only for illustration and not to limit the actuality of the present invention. It can be called in the spirit and technical scope of xituo :: x Yan, any completion of using the second aspect of the present invention, etc. The effect changes and modifications shall still be covered by the patent application. [Schematic description] 18041 14 1238509

第1圖係習知之CDBGA 半導體封裝件之剖面示意 第2A圖係本發明之微電子構農結構之剖面示音圖； 第2B圖係本發明之微電子構褒結構之底面示意圖； 第2C圖係本發明之微電子構 _ 剖面示意圖； 以、、·。構另-貫施態樣之 一實施態樣之 第2D圖係本發明之微電子構裝結構另 底面示意圖；以及 及導電元件之微電子 第3圖係本發明中包含有拒銲層 構裝結構之剖面示意圖。 【主要元件符號說明】 10 封裝結構 11a 正面 12 散熱件 13a 電性作用面 14 銲線 16 鮮球 21 金屬板 22 半導體晶片 22b 另一表面 23 絕緣層 240 導電結構 26 導熱膠黏層 28 拒銲層 11 基板 lib 背面 13 半導體晶片 13b 非電性作用面 15 封裝膠體 111 開孔 210 開口 22a 電性作用面 220 電性連接墊 24 線路層 25 被動元件 27 導電結構 29 導電元件 1 ΟΠ >11 15FIG. 1 is a cross-sectional view of a conventional CDBGA semiconductor package. FIG. 2A is a cross-sectional audio chart of a microelectronic structure of the present invention. FIG. 2B is a schematic bottom view of the microelectronic structure of the present invention. FIG. 2C It is a schematic cross-sectional view of the microelectronic structure of the present invention; The second 2D picture of one embodiment of the embodiment is a schematic diagram of the bottom surface of the microelectronic structure of the present invention; and the third diagram of the microelectronics of the conductive element is a structure of the solder mask included in the present invention. Schematic cross-section of the structure. [Description of main component symbols] 10 Package structure 11a Front side 12 Heat sink 13a Electrically active surface 14 Welding wire 16 Fresh ball 21 Metal plate 22 Semiconductor wafer 22b The other surface 23 Insulating layer 240 Conductive structure 26 Thermally conductive adhesive layer 28 Solder resist layer 11 Back of substrate lib 13 Semiconductor wafer 13b Non-electrically active surface 15 Packaging gel 111 Opening 210 Opening 22a Electrically active surface 220 Electrical connection pad 24 Circuit layer 25 Passive element 27 Conductive structure 29 Conductive element 1 ΟΠ > 11 15

Claims (1)

1238509 、申請專利範圍·· 一種微電子構裝結構，係包含·· 一形成有至少一開口之金屬板； 至少一接置於該金屬板上之半導體晶片； 至少一形成於該表面接置有半導體晶片之金屬板 上之絕緣層； 安至少一形成於該絕緣層上之圖案化線路層，且該圖 案化線路層係藉由複數形成於該絕緣層中之導電結構 以電性連接至該半導體晶片；以及 " 於該絕緣層上並收納於該金屬 中之被動元件 2. t申請專利範圍第1項之微電子構裝結構，其中，該与 V體晶片具有一電性作用面及一相 二 性作用面具有複數電性連接墊。 、面，4 1 3·如申請專利範圍第2項之微電子構裝結構 性連接墊係藉由複數形成於該 性導接至該圖案化線路層。纟層中之”結構電 4.如申請專利範圍第2項之微電子構襄結構 導體晶片之另一表面俜^中，该半 金屬板上。错導熱膠黏層而接置於該 5.如申請專利範圍第1項之微電子構裳結構，I 成於絕緣層中之導電結構係為♦ “中，自 中-者。 电凸塊及導電盲孔. 6·如申請專利範圍第】項之微電子構裳結構，其中， 1238509 屬板之材質係為具高導熱係數之金屬銅。 7·如申請專利範圍第〗項之微電子構裝結構，其中，該絕 緣層為環氧樹脂（Epoxy resin)、聚乙醯胺（p〇iyimide)、 氰脂（Cyanate ester)、碳纖維（Carbon fiber)、 ABF(Ajinomoto Build_up Film)、雙順丁 烯二酸醯亞胺/ 二虱阱（BT，Bismaleimide triazine)及混合環氧樹脂與玻 璃纖維之其中一者。 8. 如申請專利範圍第1項之微電子構裝結構，其中，該与 動元件係藉由形成於該絕緣層中之導電結構以電性連 接至該圖案化線路層。 9. ί申請專利範圍第8項之微電子構|結構，其中，該丢 電結構係為電鍍導通孔（ΡΤΗ)。 1〇.如申科利範圍第1項之微電子構裝結構，復包含： 一形成於該圖案化線路層上之圖案化 路出部分線路層；以及 ” 之導成於線路層上並自該圖案化拒銲層外露出 專利範圍第1G項之微電子構 產干層為綠漆。 及 士申凊專利範圍第10項之微電子 電元件為銲球、銲柱及導電凸塊之=構’其中，該 接置於兮入屆 鬼之“中一者，藉以提 、“i屬板上之半導體晶片導通至外界。 18041 171238509, patent application scope ... A microelectronic structure, comprising: a metal plate with at least one opening formed; at least one semiconductor wafer connected to the metal plate; at least one formed on the surface and connected with An insulation layer on a metal plate of a semiconductor wafer; at least one patterned circuit layer formed on the insulation layer, and the patterned circuit layer is electrically connected to the insulation layer through a plurality of conductive structures formed in the insulation layer; A semiconductor wafer; and a passive component on the insulating layer and housed in the metal. 2. The microelectronic structure of the first patent application scope, wherein the V-body wafer has an electrical active surface and The one-phase and two-action surface has a plurality of electrical connection pads. ， 面 ， 4 1 3 · The microelectronic structure structural connection pad according to item 2 of the patent application scope is formed by a plurality of conductive leads connected to the patterned circuit layer. The "structure layer" of the structure 4. If the second surface of the patent application scope of the microelectronic structure structure of the conductor wafer on the other surface 俜 ^, the semi-metal plate. The thermally conductive adhesive layer is placed in the 5. For example, in the case of the microelectronic structure of the first patent application scope, the conductive structure formed in the insulation layer is "medium, self-neutral". Electrical bumps and conductive blind holes. 6 · As in the microelectronic structure of item [Scope of application for patent], the material of the 1238509 metal plate is metal copper with high thermal conductivity. 7. The microelectronic structure according to the scope of the patent application, wherein the insulating layer is epoxy resin, polyimide, cyanate ester, and carbon fiber. fiber), ABF (Ajinomoto Build_up Film), Bismaleimide / Bismaleimide triazine (BT), and mixed epoxy resin and glass fiber. 8. The microelectronic structure according to item 1 of the patent application scope, wherein the passive element is electrically connected to the patterned circuit layer through a conductive structure formed in the insulating layer. 9. The microelectronic structure | structure of the scope of patent application No. 8 in which the power loss structure is a plated through hole (PTT). 10. The microelectronic structure according to item 1 of the Shenkeley scope, further comprising: a patterned circuit formed on the patterned circuit layer and a part of the circuit layer; The dry layer of the microelectronic structure exposed by the patterned solder resist layer in the patent scope item 1G is green paint. And the microelectronic electrical component of the Shi Shenjun patent scope item 10 is the solder ball, the solder post and the conductive bump = In the structure, the connection should be placed in the "one of the junior ghosts", so that the "semiconductor wafer on the board belongs to the outside world. 18041 17
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Publication number Priority date Publication date Assignee Title
TWI479639B (en) * 2011-10-03 2015-04-01 Invensas Corp Stub minimization for multi-die wirebond assemblies with orthogonal windows

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US20080157340A1 (en) * 2006-12-29 2008-07-03 Advanced Chip Engineering Technology Inc. RF module package

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI479639B (en) * 2011-10-03 2015-04-01 Invensas Corp Stub minimization for multi-die wirebond assemblies with orthogonal windows

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