TW567593B - Packaging method of memory and apparatus of the same - Google Patents

Abstract

There is provided a memory packaging method for packaging first and second memory chips as a stack-packaged memory chip, wherein the first and second semiconductor chips have bonding electrodes of the same definition. The method comprises: providing circuits having first and second stacking functions in the first and second memory chips respectively, wherein each of the first and second stacking function circuits has a selecting terminal and a starting terminal; electrically connecting the bonding electrodes of the first and second memory chip to the electrodes of the same definition of the substrate, electrically connecting the selecting terminal of the first stacking function circuit to a first voltage level, and electrically connecting the selecting terminal of the second stacking function circuit to a second voltage level; and electrically connecting the starting terminals of the first and second stacking function circuits to a power supply voltage.

Description

567593 V. Description of the invention (1) The present invention relates to a memory device, and more particularly to a memory device in a stacked package. Due to the continuous development of memory technology, the capacity of memory devices has been expanded from the previous 1Mb to the current 512Mb, and it is moving towards greater capacity. Usually, a smaller Gu 篁 memory technology has developed to a level of maturity, and then it will break into a larger capacity memory technology, for example, 2 5 6 M b memory Relevant technology, because the development time is longer than the related technology of 51 2 μ b memory, so the related technology of process, test, packaging, etc. is more stable and mature than the related technology of 5 12 Mb memory. If the finished product with smaller capacity can be stacked to make a larger capacity memory, it will be a very feasible method if the technology of the smaller capacity memory is quite mature. However, to form a large-capacity memory in a stacked manner, there are also some areas to be overcome. Due to the standard 256Mb DDR memory chip, 廿 ^ is a perfect match with the standard 512Mb memory chip: body; side-by-side test is not listed in Table 1.

0548-7420TWf (N) · 90106; dennis.ptd page 4 567593 5. Description of the invention (2) Table 1

Chip size 256Mb ~-512Mb ~ mm (Item) 64M x 4 128M x 4 architecture (orginizaton) 16M x 4 x 4 32M x 4 x 4 Crow address AxO ~ Axl2 AxO ~ Axl2 Row address (column address) AyO ~ Ay9, Ay11 Ay0-Ay9, Ayll, Ay12 bank address (BAO, BA1 BAO, BA1) pre-dead power flag (auto precharge —- A10 A10 update_ (refersh) 8K 8K by The above table 1 shows that the 256Mb memory chip and the 512-memory chip, which also have a four-input / output configuration (4 I / O configuration), the only difference is that the 51 2Mb memory chip has an additional Ayl2 pin. That is to say, the 256Mb memory Y (row) address range is Ay0 ~ Ayll, and the 512Mb memory Y (row) address range is Ay0 ~ Ayl2, so the 256Mb memory has no control signal of address Ayl2.

As shown in Figure 1, 'C1 is a 512Mb DDR (Double Data Rate) memory chip in a standard package, and C2 is a 512Mb DDR memory chip in a traditional stacked package. Since the 256Mb memory does not have the control signal of the address Ayl2, it is necessary to use the two pins of / CS0 and / CS1 to determine the action of the two internal 256Mb memory chips in the 512Mb memory particles of the traditional stacked package. Therefore, traditional stacked packaging

5. Description of the invention (3) 5 12Mb memory particles are completely compatible. " θ said that the 512Mb memory particle of the tablet is not the case, the purpose of the present invention is to provide a spot # 准 # $ of the 512Mb memory particle is fully compatible with the two / CSO and / CSI pins of Fengfeng Packaging It is big and hidden, and it is not necessary to use the standard packing of the memory particles according to one aspect of the present invention: the second control. A memory chip for packaging a first and a second memory packaging method, in which the above:-said "2 packed into-stacked packaging-", the second stacking function first mentions r a The first and second stacked functional circuits each include a two-choice start terminal. Next, Shang Cheng Di ^ select ^ and one are respectively electrically connected to a substrate; the sheet is bonded to two electrodes, and electrically connected: Γ 第 ίϋίί alternative terminal to -th-voltage level, electrically connected to the above-, The second start is to a power supply potential. * Qiaodao This electric sand According to the above another object, the present invention includes a first-memory chip;-first-type memory, at least -memory crystal ... and first; tablets 'connected to the above functional circuit' respectively It is arranged in the above-mentioned first circuit:-the circuit and the second stack individually have a -selection terminal, the first stack of the first: the memory chip is connected to a high level voltage, and the selection terminal of the above-mentioned circuit is connected to the The selection terminal of a stacking function circuit is connected to 367593 V. Description of the invention (4) Connect to a low level voltage; where the above-mentioned, when a control signal is at a high level, the previous stacking function circuit is accessed; The control signal is low: the memory chip executes the memory chip to perform the access operation. _Funshi, make the second note above, the features and advantages of the present invention will be described in the following. Pp points will appear in the description, or learned through t invention *, the present invention. This attached Ξ: will be understood and obtained through its description, the scope of patent applications, and the structures and methods carefully referred to in the 'Not Included'. Invention on the Body = Memories Packaging Method 1 to package a U-1 'in a first and second memory into a stacked packaged memory chip. One of them is: the second semiconductor chip Cpl, Cp2 has the same definition as the connection 1 ,? + It is said that the first and second semiconductor wafers Cpl and Cp2 are each a DDR memory chip. Both have the same definition of power supply pads (bonding pads, data bonding pads, etc.). The above-mentioned memory packaging method & of the present invention includes firstly providing first stacking function circuits Ccl and Cc2 to the first and second memory chips t, respectively, wherein the first stacking function circuit Ccl contains a selection ( The column address 3616 (: 1 ^ 〇11) terminal (: _ and a stack unction enable terminal (: _), and the second stacking function circuit Cc2 each includes a selection terminal C2SFE and a startup terminal. ^ Because of the standard 256Mb The DDR memory is not the same as the standard 512Mb DDR §memory body. 'You can decide whether to access the function of that chip according to the control signal on the AY 12 pin. Therefore, the present invention is described in the first and second records above.

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IM 0548-7420TWf (N); 90106; dennis.ptd 567593 V. Description of the invention (5) In the memory chips Cpl, Cp2, a stack function circuit Cel, Cc2 is added in a design (design in) manner, in accordance with the above The control signal on the AY12 pin determines which memory chip is used for access. Moreover, in the stacking function circuits Cel and Cc2, if the startup terminals ClCAS and C2CAS are connected to a power supply potential, the stacking functions of the first and second memory chips Cpl and Cp2 can be activated, that is, the first And the second memory chip Cpi and Cp2 are stacked into a memory chip having double the capacity of the original first memory chip C p 1. In addition, the start ends and C2cas of the first and second memory chips Cpl and Cp2 are completely the same as a standard 256Mb DDR memory if they are not connected to a power supply potential. Then, 'bonding wire' is used to connect the bonding pads with the same definition in the first and second memory chips Cpl and Cp2 to the substrate T1, such as a lead frame or a printed circuit board ( printed circuit board (Oard) to form a Ball Grid Array package or a thin small size package (Tmη Smau Out 1 ine Package). For example, the A0 bonding pads of the first and second memory chips Cpl, Cp2 are wire-bonded to a lead 29 for receiving the A0 signal of an external electrical signal, and other bonding pads are wire-bonded to The corresponding lead wire 66 on the lead frame. Then, wire the bonding terminals C1CAS of the first and second stacking functional circuits Cci, Cc2, (: to a power supply potential to activate the previous and second stacking functional circuits Ccl, Cc2. And wire bonding to the first The above-mentioned selection terminal Cisfe of the stacked functional circuit Cel to a first voltage level, and

567593

Serving the above-mentioned memory chip Cpl at the AY12 pin control signal, it is the first lightning pressure payment pin. Brake bismuth ^. The hidden body Japanese film Cp2 said that the above-mentioned AY12 foot violated the control k and said that it is an upstream flute—φ ^. „M + 7 fans perform an external flick when the first voltage level is reached. In this example + 'the above-mentioned, the above-mentioned A stacking function Leiyou r 〇 enter you, you π L, the above-mentioned selection terminal C1SFF of the circuit Cc2 to a 256Mb DDR record, from 0 to 丄 your basket day and day film, G hidden, so at this time, two 512Mb DDR memory is formed by stacking 256Mb DDR, and it is completely compatible with the 512Mb DDR memory C1 in the first package. Wire the circuit on the access bit of the above path on the second voltage. Save the cPl and Cp2 memory stack standard. The above first and second memory chips Cpl and Cp2 are 256 cores. 圮 Memory to explain the operation of the stacked memory of the present invention, please refer to Figure 3, when a When an external circuit (not shown in the figure) executes a write instruction, the first and second memory chips Cpl, Cp2 will be activated at the same time, that is, two 64MB intervals (item) will be activated, and according to the bit The column address signals axO ~ axl2 and row address signals ay decoded by the address decoder ~ Ayi2 to write data, if the column address signal ay 丨 2 solved there is a high logic level on time, then write the above data into the first memory chip CP 1 and address it as the above column address axO ~ Xl2 and the memory cells of row address ay0 ~ ayll, at the same time, the second stack function circuit Cc2 will block the data and write to the second memory chip Cp2 and address it as the column address ax0 ~ axl2 and Memory cells of row addresses ay 0 to ay 11. Conversely, if the above-mentioned row address signal ayl2 is a low logic level, the above data is written into the second memory chip Cp2 and addressed. For the above column addresses axO ~ axl2 and row addresses ayO ~ ayll

567593 V. Description of the invention (7) " " ''-" ^ In the hidden cell, at the same time, the first stacked functional circuit Cc 1 will prevent the material from being written into the first s memory chip C p The address in 1 is the memory cell of the above-mentioned column address axO ~ axl2 and row position aayoiyu. As shown in FIG. 2, the present invention forms a stacked memory, which at least includes a first memory chip Cpl, a second memory chip Cp2, a first stacking function circuit Cel, and a second stacking function. Circuit (^ 2. Among them, the first and second memory chips Cpl, ". For example, it can be two 256Mb DDR memory, and the same definition of the bonding pad (pin 70pin), wire bonding (B〇nding wire) onto a lead frame or printed circuit board to form a Ball Grid Array package or a Thin Small Outline Package In addition, the above-mentioned first stacking function circuit Ccl and the second stacking function circuit stacking function circuit Cc2 are respectively disposed in the above-mentioned first and second memory chips Cpl and CP2, and each has a selection terminal c. The selection terminal C1SFE of the first stacking function circuit is connected to a high level voltage, and the selection terminal (2) of the second stacking function circuit is connected to a low level voltage. Among them, the first stacking function circuit is Ccl and second stacking function circuit Cc2 are used to enable the first memory chip C p 1 to perform an access operation when a control signal is at a high level; and when the control signal is at a low level, to make the second The memory chip Cp2 performs an access operation. For example, the above control signal is one of the row address LyO ~ ayl2 decoded by an external address decoder, such as ayi2, if above ^

567593 V. Description of the invention (8) When the column address signal ay 1 2 is at a high logic level, the external input data is written into the above-mentioned first memory chip CP1, and the address is the above-mentioned column addresses axO ~ axl2 and In the memory cells of row addresses ayO ~ ayll, at the same time, the two stacked functional circuits Cc2 will block the externally inputted data and write it into the previous second memory chip CP2, addressing the column addresses ax0 ~ axi2 and Memory cells of row addresses ayO ~ ayll. Conversely, if the above-mentioned column address signal 諕 ayl2 is at a low logic level, the externally input data will be b. In the second memory chip CP2, the above-mentioned column address ax0 ~ a ^ i2 and row L will be addressed. In the memory cells of the addresses ayO ~ ayll, at the same time, ^ ^ t 阻 will hinder the above-mentioned external input data. In the above description, the μ stacking function circuit chip Cpl is addressed as the above-mentioned column position-axl2 and row position. Hidden body: The same principle is used during the reading operation as the writing operation. Therefore, the transparent memory packaging method can package two chips into a double-capacity stacked memory crystal. The double-capacity standard packaged memory chip is fully compatible, which is compatible with signals from external circuits, thereby reducing differences and increasing productivity. And & 刿 ΛI Private difference = The present invention has been disclosed in the preferred embodiment as above. Within the scope of the sound, when it can be done slightly: No: from the spirit of the present invention, please attach the scope of patents as attached. What is defined is the protection of the present invention. Page 11 0548-7420TWf (N); 90106; dennis.ptd 567593 The diagram is briefly explained. The first diagram is a standard package of 5 12Mb memory particles and a traditional stacked package 5 1 2Mb. Schematic diagram of memory particles. FIG. 2 is a schematic diagram of a stacked memory according to the present invention. FIG. 3 is another schematic diagram of the stacked memory of the present invention. [Symbol description] C. Standard packaging of 512Mb memory particles; C2 ~ traditional stacked packaging 5 12Mb memory particles; 1 0 1 ~ stacked memory of the present invention;

Cpl ~ first memory chip; Xin

Cp2 ~ second memory chip;

Cel ~ first stacking function circuit;

Cc2 ~ second stack function circuit;

ClCAS, C2CAS ~ Initiator ’

CiSFE, CgsPE ~ selection terminal '1-66 ~ lead; 110-120 ~ lead wire; a X 0-a X1 2 ~ column address signal; a y 0-a y 1 2 ~ row address signal; π ~ substrate.

0548-7420TWf (N); 90106; dennis.ptd page 12

Claims (1)

i〇 -------- September 91105491 < ^ / > VI. Application for Special Purpose-1 Mb; ^ J-body sealing method 'for ^ in the above-mentioned stacked packaged memory: slice the above The method includes:-a piece of bonding electrode having the same definition is provided, and a first, 篦-: memory chip is provided, wherein: the 'sa 端 has a selection end and a start end; the first 功 f function This circuit each includes a bonding electrode connected to the second memory chip, which is electrically connected to the first selection end of the functional circuit to the first, and the second stack function is electrically and electrically connected and connected to the above. Select the voltage level from 鳊 to ； 2; electrically connect the power supply potentials of the first and second stacking functions described above, and start the operation to 嫱 _ hunt the above first and second The stacking function circuits are the jealous-, the first-level and the second-level, which respectively cause the above-mentioned packaged memory. Take action to be compatible with the standard 5 Li 2 · The memory packaging method described in item 1 of the scope of patent application, wherein the above-mentioned substrate is a lead frame, which is the same as the above-mentioned first and third memory chips Define the electrodes. 3. The memory packaging method according to item 1 of the scope of the patent application, wherein the substrate is a printed circuit board and has the same defined electrodes as the first and second memory chips. 4. Packaging method of memory as described in item 1 of the scope of patent application, 0548-7420twfl (n); 90106; dennis.ptc page 13 575993 case number 91H1FUQ1 VI. Scope of patent application where the above electrical connections are connected 0 5 · — a pile of a first record a second record of the above first amount; and a first pile is placed on the first end, the first stacked memory chip memory chip one and second stack function Electrical and second stacking function voltage 'and the above-mentioned second stacking level voltage; wherein, each of the upper memory cells; the above-mentioned one-piece wire bonding (bonding wire) conjoined, at least including:,' electrically connected to the first The memory chip memory has a memory capacity of 2 5 6 Mb and a second stacking function circuit. The memory chip is respectively provided with a selection terminal having a selection circuit electrically connected to a high-level function circuit. Select the terminal to be electrically connected to a low-memory system compatible with standard 512Mb packaging and two stacked functional circuits. At the same time, a first level _, so that the above-mentioned memory chip performs storage = No .; No.-No. Bit time 'so that the second memory crystal: in item 5 of the above-described stacked memory stack of the functional circuit, having individually - voltage. The above mentioned stacking type described in item 5 is the above power supply voltage. ~ 'The above-mentioned stacked memory of the second item, a ground voltage. Describe the stacked first and second to perform the access action on the control letter 6 · If you apply for the first mobile terminal connected to a 7 · If you apply for the above position 8.If you apply for the above-mentioned lower patent scope and second The quasi-voltage of the patent scope of the reactor power supply is 0548-7420twfl (n); 90106; dennis.ptc page 14 567593 0548-7420twfl (n); 90106; dennis.ptc Page 15