•M363079 - 五、新型說明： 【新型所屬之技術領域】 本創作有關於一種半導體封裝技術，特別是有關於 一種半導體裝置中用於陣列封裝佈線結構。 【先前技術】 ' 隨著電子或光電產品諸如數位相機、具有影像拍攝 •功能的手機、條瑪知猫器（bar code reader )、射*員功率 籲計（RF power meter)以及監視器逐漸普及化，電子或光 電裝置的需求也與日倶增。電子或光電裝置通常包括. 雷射二極體、發光二極體（LEDs )、電荷耦合裝置 . (charge-coupled device, CCD )、互補式金氧半導體 (complementary metal oxide semiconductor , CMOS) ψ 置、功率感測器（power sensor)且使用於印刷、資料儲 存、或光資料的傳送與接收。 大多數的半導體裝置如電子或光電裝置通常為了效 _ 能上的需求而置放於一密封的封裝體，其有助於操作上 的穩定性。上述半導體裝置可藉由一種稱作晶圓級晶片 尺寸封裝（wafer level chip scale package, WLCSP)技術 來進行封裝。在傳統的封裝技術中，係先將具有如電子 裝置、微機電裝置、或是光電裝置等微裝置的晶圓切割 成多個晶片之後，再將其封裝。而不同於傳統的封裝方 式，WLCSP技術中，微裝置的封裝係在晶圓切割成多個 晶片之前進行。另外，上述裝置進一步藉由陣列封裝技 9002-A33375TWF/X07-046/spin 3 地63079 1丁例如球拇陣列（baI1 grid array, BGA )封裝，使裝置 电性連接至—印刷電路板（primed circuit board P⑻ 以進行特定操作。 然而，隨著產品尺寸的縮小及功能的複雜化， 提二必須儘可能的縮小’同時也可能必須 ♦、电子接觸點以因應電裝置中增加的積體電路。 對於封裝的佈線設計者而言，將面臨嚴苛的挑戰 【新型内容】 f鐘於此，本創作的目的在於提供—種用 I之佈線結構及具有該佈線結構的半導體裝置，並= =糊連接用於陣列封裝的接墊：： ^墊間距進而縮小整體裝置尺寸或是在相 = 中設置更多接墊以供晶片使用。 尺寸 裙據上返之目的’本創作提供一種 織構，包括、承載基板、-絕緣層、第= 每形接塾陣列、複數走線以及複數下通道導電層。第一 及第二環形接墊陣列及走線，分職置於承载^ :絕緣層上，其中第二環形接墊陣列位於第一環形接墊 陣列相對内侧，而走線依序環繞排列於絕緣層邊緣。下 通迢導電層設置於承載基板舆絕緣層之間。這些 Ή伸至第一環形接墊陣列中-對應的接墊， 而至-走線經由其中一下通道導電層而電性連接至第 9002-A33375TWF/X07-046/spin 4 M363079 二環形接墊陣列中一對應的接墊。 又根據上述之目的，本創作提供一種半導體裝置， =:具有—非主動表面的—襄置基板，—承載基板、 -絕緣層、第-及第二環形接墊陣列、複數走線以及 數I通道導電層。承載基板設置於非主動表面上。第一 及昂一㈣接墊陣列及走線，分別設置於承載基板上方 的絕緣層上’其中第二環形接墊陣列位於第—環形接塾 陣列相對㈣]’而走線依序環繞排列於絕緣層邊緣且延 伸至承載基板及裝置基板的側壁上。下通 於㈣基板與絕緣層之間。這些走線中至少-走 至弟-㈣接墊陣列中—對應的接塾，而至少 ^其中-下通道導電層而電性連接至第二環形接塾^ 中一對應的接墊。 【實施方式】 以下說明本創作之實施例。此說明之目的在 本創作的總體概念而並非用 、" ^ 非用以偈限本創作的範圍。本創 作之保護範圍當視後附之申社直斗丨> m ^ 本幻 & *咖 曱5月專利範圍所界定者為準。 §月蒼照弟1及2圖，直由缺， y , /、中弟1圖係緣示出一範例之 半導體裝置中用於陣列封奘沾社^ ^靶例之 Μ ? m φ ^ 9佈線結構平面示意圖，而 弟2圖係、.、曰不出弟1圖中〉VL 9 & U 口 2_2線之剖面示意圖。本例 係以光電裝置為例，例如旦彡你 , 扪如衫像感測裝置，包括：一裝置 基板100及一用於陣列封穿 匕秸 扃置 ,,,^ a , ^ 了衣的佈線結構。裝置基板100， 例如一矽晶片或其他半導 、版曰曰片’其具有一非主動面 9002-A33375TWF/X07-046/spin 5 •M363079 -100a。此處的非主動面所指的是，不具有積體電路或電 子部件形成於其上的表面。在本實施例中，裝置基板1〇〇 内包含影像感測元件，例如晝素二極體，及控制影像感 測元件的積體電路。此處，為了簡化圖式，僅繪示出一 平整的基板。用於陣列封裝的佈線結構係設置於裝置基 板100的非主動面l00a上’包括：一承載基板1〇2，例 •如一玻璃基板或其他透明基板，以及設置於承載基板102 .上的絕緣層1 〇4及1 〇8、複數接墊1 〇6a及1 〇6c、以及走 •線 106b。 絕緣層104及1〇8的材質可為綠漆（s〇ldermask)、 樹脂、習知的介電材料，或其組合。由複數接墊1〇仏所 .構成的第一環形接墊陣列及由複數接墊106c所構成的第 二環形接墊陣列分別設置於絕緣層1〇4上，其中第二環 形接墊陣列位於第一環形接墊陣列的對内侧。再者，複 數走線106b設置於絕緣们04上，且依序環繞排列於^ 緣層104的邊緣。走線10613可由金屬所構成。每一走線 鲁的一端係延伸至接墊106a或1〇6c，而另一端則延 伸至承載基板102及裝置基板100的侧壁上，i中裝置 基板⑽的難設置有-絕緣層1G1，例如—環氧樹脂 層，使裝置基板100與走線106b絕緣，如第2圖所示。 .=一方面，走線1〇补會藉由露出於裝置基板100侧壁的 .电極（未|不）’而與裝置基板⑽内的積體電路電性 在本貫施例_，-—些 陣列中對應的接墊106a， 走線106b延伸至第一環形接墊 而其他的走線l〇6b則延伸至第 9002-A333 75TWF/X07-〇46/spin M363079 二環形接墊陣列中對應的接墊106c，如第i圖所示。再 者，設置於絕緣層104上的絕緣層108覆蓋走線1〇补且 具有複數開口 108a而局部露出第一及第二環形接墊陣列 中的接墊106a及l〇6c。複數焊球11〇依序設置於對應的 接墊1〇6&及l〇6c，並經由開口 1〇8a而與下方的接墊1〇6& 及106c電性連接。然而，在上述的佈線結構中，由於絕 緣層1G4上的每—走線祕需延伸至對應的接墊1〇6a 或106c，故焊球110的球距ρι (或接墊間距）受限於走 線職的線寬。若為了縮小球距ρι來縮小整體襄置尺 寸，則走線106b的、線寬必須縮丨。如此將導致製程料 度（Pr〇CeSSWind〇W)降低而降低裝置的可靠度。另外， 製程料度_加走線嶋的線寬，則球距 在二^二二—來，走線1嶋及料咖或⑽ 在#線結構中所佔用的面積將 體裝置尺寸難以縮小。以進—步的縮小而使整• M363079 - V. New Description: [New Technology Field] This work is about a semiconductor package technology, especially related to an array package wiring structure in a semiconductor device. [Prior Art] ' With electronic or optoelectronic products such as digital cameras, mobile phones with video capture capabilities, bar code readers, RF power meters, and monitors The demand for chemical, electronic or optoelectronic devices is also increasing. Electronic or optoelectronic devices typically include: laser diodes, light-emitting diodes (LEDs), charge-coupled devices (CCDs), complementary metal oxide semiconductors (CMOS) devices, Power sensor and used for printing, data storage, or transmission and reception of optical data. Most semiconductor devices, such as electronic or optoelectronic devices, are typically placed in a sealed package for efficiency, which contributes to operational stability. The above semiconductor device can be packaged by a technique called wafer level chip scale package (WLCSP). In the conventional packaging technology, a wafer having a micro device such as an electronic device, a microelectromechanical device, or an optoelectronic device is first diced into a plurality of wafers, and then packaged. Unlike traditional packaging methods, in WLCSP technology, the package of the micro device is performed before the wafer is diced into multiple wafers. In addition, the above device is further electrically connected to the printed circuit board by the array package technology 9002-A33375TWF/X07-046/spin 3 63079 1 butyl, for example, a ball array (BGA) package. Board P (8) for specific operations. However, as the product size shrinks and the function is complicated, the second must be reduced as much as possible. At the same time, it may be necessary to contact the electronic contacts to increase the integrated circuit in the electrical device. The packaged wiring designer will face severe challenges [new content] f clock, the purpose of this creation is to provide a wiring structure using I and a semiconductor device having the wiring structure, and = = paste connection Pads for Array Packages:: ^The pad pitch further reduces the overall device size or sets more pads in the phase = for wafer use. The size of the skirt is for the purpose of returning. 'This creation provides a texture, including, The carrier substrate, the insulating layer, the argon-shaped array, the plurality of traces, and the plurality of lower channel conductive layers. The first and second annular pad arrays and traces are placed separately On the insulating layer, wherein the second annular pad array is located on the opposite inner side of the first annular pad array, and the traces are sequentially arranged around the edge of the insulating layer. The lower via conductive layer is disposed on the carrier substrate and the insulating layer. Between the first ring pad array and the corresponding pad, the to-wire is electrically connected to the 9002-A33375TWF/X07-046/spin 4 M363079 via the lower channel conductive layer. A corresponding pad in the pad array. According to the above object, the present invention provides a semiconductor device, =: a substrate having an inactive surface, a carrier substrate, an insulating layer, a first and a second ring a pad array, a plurality of traces, and a plurality of I-channel conductive layers. The carrier substrate is disposed on the inactive surface. The first and the first (four) pad arrays and the traces are respectively disposed on the insulating layer above the carrier substrate, wherein the second The annular pad array is located on the first ring-shaped array relative to (4)]', and the traces are sequentially arranged around the edge of the insulating layer and extend to the sidewalls of the carrier substrate and the device substrate. The lower layer is connected between the (four) substrate and the insulating layer. At least in the trace - go to the younger - (four) pad array - the corresponding interface, and at least ^ the lower channel conductive layer and electrically connected to a corresponding one of the second annular interface ^. The following is an example of the creation of this creation. The purpose of this description is in the overall concept of the creation and not the use of " ^ is not intended to limit the scope of this creation. The scope of protection of this creation is attached to the Shenshe丨> m ^ 本幻& *Curry is defined by the scope of the patent in May. §Yue Cang Zhaodi 1 and 2, straight from lack, y, /, Zhongdi 1 map shows an example In the semiconductor device, the array is used for the array sealing 奘^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ A schematic view of the line. In this example, an optoelectronic device is taken as an example. For example, a device such as a shirt sensing device includes: a device substrate 100 and a wiring for the array to seal the straw device, and the wiring of the clothing structure. The device substrate 100, such as a germanium wafer or other semiconductor, has a non-active surface 9002-A33375TWF/X07-046/spin 5 • M363079-100a. The inactive surface herein refers to a surface on which an integrated circuit or an electronic component is formed. In the present embodiment, the device substrate 1A includes image sensing elements such as a halogen diode and an integrated circuit for controlling the image sensing element. Here, in order to simplify the drawing, only a flat substrate is shown. The wiring structure for the array package is disposed on the inactive surface 100a of the device substrate 100' including: a carrier substrate 1 2, such as a glass substrate or other transparent substrate, and an insulating layer disposed on the carrier substrate 102. 1 〇 4 and 1 〇 8, multiple pads 1 〇 6a and 1 〇 6c, and walking line 106b. The material of the insulating layers 104 and 1 8 may be a green lacquer, a resin, a conventional dielectric material, or a combination thereof. The first annular pad array formed by the plurality of pads 1 and the second annular pad array formed by the plurality of pads 106c are respectively disposed on the insulating layer 1〇4, wherein the second annular pad array Located on the inner side of the first annular pad array. Furthermore, the plurality of traces 106b are disposed on the insulators 04 and are sequentially arranged around the edges of the edge layer 104. Trace 10613 can be constructed of metal. One end of each of the wires extends to the pads 106a or 1〇6c, and the other end extends to the side walls of the carrier substrate 102 and the device substrate 100. The device substrate (10) is difficult to be provided with an insulating layer 1G1. For example, an epoxy resin layer insulates the device substrate 100 from the trace 106b as shown in FIG. On the one hand, the trace 1 〇 complements the integrated circuit in the device substrate (10) by the electrode (not | not) exposed on the side wall of the device substrate 100 in the present embodiment _, - The corresponding pads 106a in the array, the trace 106b extends to the first annular pad and the other traces l〇6b extend to the 9002-A333 75TWF/X07-〇46/spin M363079 two ring pad array The corresponding pad 106c is as shown in the figure i. Furthermore, the insulating layer 108 disposed on the insulating layer 104 covers the wiring 1 and has a plurality of openings 108a to partially expose the pads 106a and 106c in the first and second annular pad arrays. The plurality of solder balls 11 are sequentially disposed on the corresponding pads 1〇6& and l〇6c, and are electrically connected to the lower pads 1〇6& and 106c via the openings 1〇8a. However, in the above wiring structure, since each of the traces on the insulating layer 1G4 is extended to the corresponding pads 1〇6a or 106c, the ball pitch ρι (or the pitch of the pads) of the solder balls 110 is limited by The line width of the line. If the overall size is reduced to reduce the pitch ρι, the line width of the trace 106b must be reduced. This will result in a reduction in process quality (Pr〇CeSSWind〇W) and a reduction in the reliability of the device. In addition, the process material _ plus the line width of the line ,, the ball distance is in the second ^ 22 -, the line 1 嶋 and the coffee shop or (10) the area occupied by the # line structure will be difficult to reduce the size of the body device. Take the step-by-step reduction
因此，本創作人提出另—種半導體裝 封I的佈線結構，如第3、4、 、車歹J 係㈣出根據本創作實施例之二圖:=中第3圖 裝的佈線結構平面示意圖，第4+=:置中用於陣列封 4 4,娩·>立丨t - & 弟4圖係繪不出第3圖中沿 4-4線之DlJ面示意圖而第 線之立丨丨面千立闫+丄 M诉、、'日不出弟3圖中沿5_5， ° ^、思圖。在本實施例中，以φ壯 如影像感測裝置，包括·· I 包衣置為例，例 置基板細以及位於非主動^非主動表面職的一裝 佈線結構。裝置基板200可==上用於陣列封裝的 基板100。 了相同於弟1及2圖中的裝置 φιΐ) 9〇〇2-A33375TWF/X〇7.〇46/s 7 M363079 佈線結構係設置於裝置基柘, ^ , 土不反200的非主動面2〇〇a 上’包括：一承載基板202、絕绦 巴緣層203、204、及208、 第一及第二環形接墊陣列'複數去 … &双％線206b、複數下通道 導電層205以及複數焊球21 〇。承丧甘l ^u丄 來载基板2〇2的材質可相 同或類似於第1及2圖中的承载基板2〇2。絕緣層2〇3、 204、及208依序設置於承載基板2〇2上。同樣地，絕緣 層203、204、及208的材質可相同或類似於第1及2圖 中的絕緣層104及108。 • 由複數接墊206a所構成的第一環形接墊陣列.及由複 數接墊206c所構成的第二環形接墊陣列分別設置於絕緣 層204上，其中第二環形接墊陣列位於第一環形接墊陣 列的對内侧。再者’被數走線2 0 6 b亦設置於絕緣層2 〇 4 上’且依序環繞排列於絕緣層204的邊緣。每一走線2〇6b • 的一端延伸至承載基板202及裝置基板200的側壁上， 且藉由裝置基板200側壁上的一絕緣層201與|置美板 200絕緣’如第4或5圖所示。再者，走線2〇6b的另一 •端則與第一環形接墊陣列中對應的接墊206a電性連接或 與第二環形接墊陣列中對應的接墊206c電性連接。 在本實施例中，一些走線2〇6b延伸至第一環形接塾 陣列中對應的接墊206a。特別的是其他未延伸至接塾 ” 206a的走線206b則經由設置於絕緣層204下方的下通道 •導電層205而電性連接至第二環形接墊陣列中對應的接 墊206c。請參照第4及5圖，下通道導電層2〇5，例如 一金屬層，夾設於絕緣層2〇3與絕緣層204之間。在其 他實施例中，承載基板202上可不設置絕緣層203，使下 9002-A3 3 3 7 5T WF/X07-046/spin 8 M363079 - 通道導電層205夾設於承載基板202與絕緣層204之間。 由於下通道導電層205位於絕緣層204下方而不影響接 墊206a及206c的配置，故下通道導電層205可通過第 一環形接墊陣列中接墊206a的下方（如第3及5圖所示） 或是設置於兩相鄰接墊206a之間的絕緣層204下方（如 第3及4圖所示）。另外，絕緣層204具有複數對通孔 -204a及204b對應於下通道導電層205的兩端並局部露出 . 下通道導電層205。通孔204b提供走線206b與對應的下 籲 通道導電層205之間的電性連接。舉例而言，走線206b 經由通孔204b而與露出的下通道導電層205接觸。通孔 204a提供第二環形接墊陣列中的接墊206c與對應的下通 道導電層205之間的電性連接。舉例而言，接墊206c經 由通孔204a而與露出的下通道導電層205接觸。在本實 ' 施例中，通孔204a及204b的上視輪廓為矩形。然而， 在其他實施例中，通孔204a及204b的上視輪廓可為圓 形、三角形、或其他多邊形。 籲 設置於絕緣層204上的絕緣層208覆蓋走線206b且 具有複數開口 208a而局部露出第一及第二環形接墊陣列 中的接墊206a及206c。複數焊球210依序設置於對應的 接墊206a及206c，並經由開口 208a而與下方的接墊206a 及206c電性連接。 在上述的實施例中，由於一些走線206b係藉由下通 ' 道導電層205電性連接至接墊206c，而不是直接延伸至 接墊206c。因此，在不縮小走線206b線寬的情形下，焊 球210的球距P2 (或接墊間距）得以縮小，進而縮小整 9002-A33375TWF/X07-046/spin 9 -M363079 體裝置尺寸。亦即，可换 可靠度。另外，Γ 許叙提升裝置 也」在不鈿小整體裝置尺，楂 線結構可提供更多面積來 y ，佈 接執仰#、 積U更多的電子接觸點（即， 接祕球），以因應具有複雜積體電路的晶片所J 雖然本創作已以較佳實施例揭露如上，铁而 W本創作，任何所屬技術領域中具有通常二：用 ==之精神和範圍内，當可作更動與二， 者為Γ 圍當視㈣之申請專利範圍所界定Therefore, the present author proposes a wiring structure of another semiconductor package I, such as the third, fourth, and ruthless J series (four) according to the second diagram of the present embodiment: = the third diagram of the layout of the wiring structure , 4+=: centering for array sealing 4 4, delivery · > 丨 丨 t - & brother 4 figure can not draw the DlJ surface diagram along line 4-4 in the third figure and the first line丨丨面千立闫+丄M v,, 'Don't go out in the 3rd picture along the 5_5, ° ^, think. In the present embodiment, a sturdy image sensing device, including a coating device, is exemplified, and the substrate is thin and a wiring structure is disposed on the non-active/inactive surface. The device substrate 200 can == the substrate 100 for the array package. Same as the device φιΐ in the brothers 1 and 2) 9〇〇2-A33375TWF/X〇7.〇46/s 7 M363079 The wiring structure is set on the device base, ^, the non-active surface of the soil is not reversed 2 〇〇a' includes: a carrier substrate 202, an insulating barrier layer 203, 204, and 208, and a first and a second annular pad array multiplexed... & double % line 206b, a plurality of lower channel conductive layers 205 And a plurality of solder balls 21 〇. The material of the carrier substrate 2 〇 2 can be the same or similar to the carrier substrate 2 〇 2 in FIGS. 1 and 2 . The insulating layers 2〇, 204, and 208 are sequentially disposed on the carrier substrate 2〇2. Similarly, the insulating layers 203, 204, and 208 may be the same or similar to the insulating layers 104 and 108 of Figures 1 and 2. The first annular pad array formed by the plurality of pads 206a and the second annular pad array formed by the plurality of pads 206c are respectively disposed on the insulating layer 204, wherein the second annular pad array is located at the first The inner side of the annular pad array. Further, 'the number of traces 2 0 6 b is also disposed on the insulating layer 2 〇 4 ' and is sequentially arranged around the edge of the insulating layer 204. One end of each of the traces 2〇6b • extends to the sidewalls of the carrier substrate 202 and the device substrate 200, and is insulated from the slab 200 by an insulating layer 201 on the sidewall of the device substrate 200 as shown in FIG. 4 or 5. Shown. Furthermore, the other end of the trace 2〇6b is electrically connected to the corresponding pad 206a of the first annular pad array or to the corresponding pad 206c of the second annular pad array. In this embodiment, some of the traces 2〇6b extend to corresponding pads 206a in the first annular interface array. In particular, the other traces 206b that are not extended to the interface 206a are electrically connected to the corresponding pads 206c of the second annular pad array via the lower via conductive layer 205 disposed under the insulating layer 204. Please refer to 4 and 5, the lower channel conductive layer 2〇5, for example, a metal layer, is interposed between the insulating layer 2〇3 and the insulating layer 204. In other embodiments, the insulating substrate 203 may not be disposed on the carrier substrate 202. The lower 9002-A3 3 3 7 5T WF/X07-046/spin 8 M363079 - channel conductive layer 205 is sandwiched between the carrier substrate 202 and the insulating layer 204. Since the lower via conductive layer 205 is located below the insulating layer 204, it does not affect The pads 206a and 206c are disposed such that the lower via conductive layer 205 can pass through the underside of the pads 206a in the first annular pad array (as shown in Figures 3 and 5) or in the adjacent pads 206a. The insulating layer 204 is underneath (as shown in Figures 3 and 4). In addition, the insulating layer 204 has a plurality of pairs of vias -204a and 204b corresponding to both ends of the lower via conductive layer 205 and partially exposed. The lower via conductive layer 205 The via 204b provides the electrical connection between the trace 206b and the corresponding lower-channel conductive layer 205. For example, the trace 206b is in contact with the exposed lower via conductive layer 205 via the via 204b. The via 204a provides between the pad 206c in the second annular pad array and the corresponding lower via conductive layer 205. For example, the pad 206c is in contact with the exposed lower channel conductive layer 205 via the via 204a. In the present embodiment, the top views of the vias 204a and 204b are rectangular. In other embodiments, the top view of the vias 204a and 204b may be circular, triangular, or other polygonal. The insulating layer 208 disposed on the insulating layer 204 covers the trace 206b and has a plurality of openings 208a to partially expose the first And the pads 206a and 206c in the second annular pad array. The plurality of solder balls 210 are sequentially disposed on the corresponding pads 206a and 206c, and are electrically connected to the underlying pads 206a and 206c via the opening 208a. In the embodiment, since some of the traces 206b are electrically connected to the pads 206c by the underlying conductive layer 205 instead of directly extending to the pads 206c, the line width of the traces 206b is not reduced. , the ball pitch P2 of the solder ball 210 ( The pitch of the pads can be reduced, and the size of the 9002-A33375TWF/X07-046/spin 9-M363079 body device can be reduced. That is, the reliability can be changed. In addition, the 提升 叙 lifting device is also not small. The 楂 line structure can provide more area to y, the cloth is connected to the yoke, and the U is more electronic contact points (ie, the ball is attached) to meet the chip with a complex integrated circuit. The preferred embodiment discloses the above, the iron and W creation, any of the technical fields of the art have two: use the spirit and scope of ==, when the change can be made and the second, the scope of the patent application (4) Define
9002-A33375TWF/X07-046/spin 10 M3 63 079 【圖式簡單說明】 # @ ^係、曰不出—範例之半導體裝置中用於陣列封 衣的佈線結構平面示意圖； ^圖係/會示出第1圖中沿2-2,線之剖面示意圖； 用於_ ^ ^ ^^狀”體裝置中 及第4圖係繞示出第3圖中沿4-4,線之剖面示意圖； 弟5圖係繪示出第 圖中沿5-5’線之剖面示意圖 【主要元件符號說明】 100、 200〜裝置基板； 100a、200a〜非主動面； 102、202〜承載基板； 101、 104、108、2(H、203、204、208〜絕緣層 108a、208a~開口； 106a、l〇6c、206a、206c〜接墊； 106b、206b〜走線； 110、210〜焊球； 204a、204b〜通孔； 205〜下通道導電層； PI、P2〜球距。 9002-A33375TWF/X〇7_〇46/spin 119002-A33375TWF/X07-046/spin 10 M3 63 079 [Simple diagram of the diagram] # @^系,不曰出—A schematic diagram of the wiring structure used for array sealing in the semiconductor device of the example; ^图/示Figure 2 is a cross-sectional view taken along line 2-2 of the first figure; used in the _ ^ ^ ^^-like body device and the fourth figure is shown in the third figure along the line 4-4, a schematic view of the line; 5 is a schematic cross-sectional view along the line 5-5' in the figure [main symbol description] 100, 200 ~ device substrate; 100a, 200a ~ non-active surface; 102, 202 ~ carrier substrate; 101, 104, 108, 2 (H, 203, 204, 208~ insulating layer 108a, 208a~ opening; 106a, l6c, 206a, 206c~ pad; 106b, 206b~ trace; 110, 210~ solder ball; 204a, 204b ~ Through hole; 205~ lower channel conductive layer; PI, P2 ~ ball pitch. 9002-A33375TWF/X〇7_〇46/spin 11