CN112470270A - Tsv上的偏移焊盘 - Google Patents

Tsv上的偏移焊盘 Download PDF

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Publication number
CN112470270A
CN112470270A CN201980048835.5A CN201980048835A CN112470270A CN 112470270 A CN112470270 A CN 112470270A CN 201980048835 A CN201980048835 A CN 201980048835A CN 112470270 A CN112470270 A CN 112470270A
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China
Prior art keywords
substrate
tsv
bonding
bonding surface
recess
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Granted
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CN201980048835.5A
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CN112470270B (zh
Inventor
B·李
G·高
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Insulation Semiconductor Bonding Technology Co
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Evanss Adhesive Technologies
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Priority to CN202210538162.5A priority Critical patent/CN114899166A/zh
Publication of CN112470270A publication Critical patent/CN112470270A/zh
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Abstract

可以采用包括过程步骤的代表性技术和设备来减轻由于键合界面处的金属膨胀而导致的经键合微电子衬底的分层的可能性。例如，金属焊盘可以设置在微电子衬底中的至少一个微电子衬底的键合表面处，其中接触焊盘相对于衬底中的TSV偏移地定位并且电耦合到TSV。

Description

TSV上的偏移焊盘
优先权和相关申请的交叉引用
本申请要求根据35U.S.C.§119(e)(1)要求于2019年6月13日提交的美国非临时申请号16/440,633和于2018年6月13日提交的美国临时申请号62/684,505的权益，其全部内容通过引用并入本文。
技术领域
以下描述涉及集成电路(“IC”)。更具体地，以下描述涉及制造IC管芯和晶片。
背景技术
微电子元件通常包括由半导体材料(诸如硅或砷化镓之类)形成的薄平板(通常被称为半导体晶片)。晶片可以被形成为包括位于晶片的表面上和/或部分嵌入晶片内的多个集成芯片或管芯。与晶片分开的管芯通常作为单独、预先封装单元提供。在一些封装设计中，管芯被安装到衬底或芯片载体，而衬底或芯片载体又被安装在诸如印刷电路板(PCB)之类的电路面板上。例如，许多管芯提供在适于表面安装的封装中。
封装半导体管芯还能够以“堆叠”布置提供，其中一个封装被设置在例如电路板或其他载体上，而另一封装被安装在第一封装的顶部上。这些布置可以允许若干个不同的管芯或器件被安装在电路板上的单个覆盖区中，并且可以通过在封装之间提供短互连来进一步促进高速操作。通常，该互连距离只能稍微大于管芯本身的厚度。为了在管芯封装的堆叠内实现互连，可以在每个管芯封装(除了最顶部封装之外)的两侧(例如，多个面)上提供用于机械连接和电连接的互连结构。
附加地，管芯或晶片可以以三维布置堆叠，以作为各种微电子封装方案的一部分。这可以包括将一个或多个管芯、器件和/或晶片的层堆叠在较大的基部管芯、器件、晶片、衬底等上；以垂直布置或水平布置堆叠多个管芯或晶片；以及两者的各种组合。
管芯或晶片可以使用各种键合技术在堆叠布置中被键合，这些键合技术包括直接电介质键合、非粘合技术(诸如
Figure BDA0002909414900000021
)或混合键合技术(诸如
Figure BDA0002909414900000022
)，两者均可从Invensas Bonding Technologies,Inc.(以前Ziptronix，Inc.)、Xperi公司获得。键合包括自发过程，当两个已准备好的表面放在一起时，在周围条件下发生该自发过程(参见，例如，美国专利号6,864,585和7,485,968，其全部内容通过引用并入本文)。
键合的管芯或晶片的相应配合表面通常包括嵌入式导电互连结构(其可以是金属)等。在一些示例中，键合表面被布置和对准，使得来自相应表面的导电互连结构在键合期间被接合。接合的互连结构在堆叠管芯或晶片之间形成连续导电互连(用于信号、功率等)。
实现堆叠管芯和晶片布置可能存在多种挑战。当使用直接键合技术或混合键合技术来键合堆叠的管芯时，通常期望要键合的管芯的表面极其平坦、光滑且干净。比如，通常，这些表面在表面拓扑上应当具有非常低的变化(即，纳米级变化)，以使这些表面可以紧密配合以形成持久键合。
可以形成和制备双面管芯以用于堆叠和键合，其中管芯的两侧将被键合到其他衬底或管芯，诸如在多个管芯到管芯的应用或管芯到晶片的应用的情况下。制备管芯的两侧包括修整两个表面以满足电介质粗糙度规格和金属层(例如，铜等)凹部规格。比如，可以使键合表面处的导电互连结构稍微凹陷，刚好在键合表面的绝缘材料下方。键合表面下方的凹陷量可以由设备或应用的尺寸容差、规格、或物理限制确定。可以制备混合表面以使用化学机械抛光(CMP)工艺等与另一管芯、晶片或其他衬底键合。
通常，当包含电介质层和一个或多个金属特征(例如，嵌入式导电互连结构)的组合的直接键合表面被键合在一起时，电介质表面首先在较低温度下键合，之后由于金属在退火期间被加热，所以特征的金属膨胀。金属的膨胀会导致来自两个键合表面的金属接合成统一的导电结构(金属到金属键合)。虽然在退火期间同时加热衬底和金属，但相对于衬底的热膨胀系数(CTE)，金属的CTE通常指示金属在特定温度(例如，
Figure BDA0002909414900000031
300℃)下的膨胀比衬底大得多。比如，铜的CTE为16.7，而熔融二氧化硅的CTE为0.55，而硅的CTE为2.56。
在一些情况下，对于直接键合而堆叠的管芯或晶片，金属相对于衬底的更大膨胀可能是个问题。如果金属焊盘位于穿硅过孔(through silicon via，TSV)上方，则TSV金属的膨胀会有助于焊盘金属的膨胀。在一些情况下，在膨胀金属上升到键合表面上方时，组合的金属膨胀会引起键合表面的局部分层。比如，膨胀金属可以将堆叠管芯的键合电介质表面分开。
附图说明
参考附图对具体实施方式进行阐述。在附图中，附图标记的一个或多个最左边数字标识该附图标记首次出现的附图。在不同附图中使用相同附图标记指示相似项或相同项。
为了进行讨论，图中所示的设备和系统被示为具有多个部件。如本文中所描述的，设备和/或系统的各种实现方式可以包括较少部件，并且仍然在本公开的范围内。可替代地，设备和/或系统的其他实现方式可以包括附加部件或所描述的部件的各种组合，并且仍在本公开的范围内。
图1A示出了具有键合焊盘和TSV的示例衬底的横截面。
图1B示出了图1A的示例衬底的俯视图。
图2示出了带有键合焊盘和TSV的两个示例经键合衬底的横截面、以及示例结果分层。
图3示出了根据一个实施例的带有相对于TSV偏移定位的键合焊盘的示例衬底的横截面。
图4示出了根据一个实施例的带有相对于TSV偏移定位的键合焊盘的示例衬底的横截面，该键合焊盘具有不平坦表面。
图5示出了根据一个实施例的带有相对于TSV偏移定位的键合焊盘和TSV上方设置的凹部的示例衬底的横截面。
图6至图14示出了根据一个实施例的带有相对于TSV偏移定位的键合焊盘的示例衬底的横截面，其图示了衬底的示例背侧过程。
图15示出了根据一个实施例的带有TSV和偏移键合焊盘的前到背键合的两个示例经键合衬底的横截面。
图16示出了根据一个实施例的带有示例TSV、偏移键合焊盘和应力凹部的前到背键合的两个示例经键合衬底的横截面。
图17示出了根据一个实施例的带有TSV、多个偏移键合焊盘和应力凹部的前到背键合的两个示例经键合衬底的横截面。
图18示出了根据一个实施例的带有TSV、偏移键合焊盘和应力凹部的背到背键合的两个示例键合衬底的横截面。
图19示出了根据一个实施例的带有TSV、偏移键合焊盘和应力凹部的前到前键合的两个示例键合衬底的横截面。
图20示出了根据各个实施例的用于对管芯进行热管理的示例TSV的图。
图21是示出了根据一个实施例的形成微电子组件，以减少或消除键合衬底的分层的示例过程的文本流程图。
发明内容
公开了代表性技术和设备，其包括用于制备各种微电子设备以进行键合(诸如无需粘合剂的直接键合)的过程步骤。在各种实施例中，可以采用技术来减轻由于金属膨胀而引起的分层的可能性，特别是当一个或两个要键合的器件的键合表面处存在TSV或TSV上方的键合焊盘时。例如，在一个实施例中，TSV可以部分地延伸通过器件的衬底，并且金属接触焊盘可以在键合表面处设置为相对于TSV偏移。比如，接触焊盘被设置为以使其不与TSV交叠。接触焊盘可以使用一个或多个导电迹线等电耦合到TSV。
在接触焊盘相对于TSV偏移定位的实施例中，焊盘的偏移避免了TSV的金属膨胀与焊盘的金属膨胀组合，从而可以减少或消除否则可能发生的分层。
在各种实现方式中，一种示例过程包括：将第一穿硅过孔(TSV)嵌入到具有第一键合表面的第一衬底中，其中第一TSV部分地延伸通过第一衬底，与第一键合表面正交并且不在第一键合表面处暴露。第一金属接触焊盘设置在第一键合表面处，相对于第一TSV偏移，不与第一TSV交叠，并且在第一键合表面下方部分地延伸到第一衬底中。第一金属接触焊盘使用一个或多个嵌入式导电迹线电耦合到第一TSV。
在各个示例中，基于第一金属接触焊盘的直径或表面积或用于第一金属接触焊盘的预测凹部，可以选择或形成接触焊盘。比如，在一个实施例中，该过程包括：基于估计来确定第一金属接触焊盘相对于第一键合表面的期望凹部，以允许第一金属接触焊盘的材料膨胀，并且当对第一金属接触焊盘进行平坦化时，选择或形成第一金属接触焊盘以具有可能导致期望凹部的周边形状。这可以包括：预测由于平坦化而可能在第一金属接触焊盘的表面中发生的凹陷量。在另一实施例中，该过程包括：基于预测来在第一金属接触焊盘的表面中形成期望凹部(在键合之前)。
在各个实施例中，该过程包括：通过选择第一金属接触焊盘并且使第一接触焊盘相对于TSV偏移来减少或消除经键合微电子部件的分层。
附加地或可替代地，可以对第一衬底的背侧进行处理以供键合。可以在第一衬底的背侧上沉积一个或多个预选材料绝缘层，以利于TSV的适当露出和平坦化，并且当要直接键合第一衬底的背侧时，形成电介质表面以供键合。
进一步地，第一TSV以及第一衬底内的其他TSV可以用于在第一衬底内和/或远离第一衬底引导或传递热量。在一些实现方式中，热传递TSV可以部分或全部延伸通过第一衬底的厚度，并且可以包括导热阻挡层。在这样的示例中，TSV周围正常使用的趋于隔热的阻挡层反而可以使用导热层替换。在各个实现方式中，一些TSV可以用于信号传递和热传递。
在一个实施例中，一种微电子组件包括第一衬底，该第一衬底包括带有具有第一预先确定的最大表面变化的平坦化形貌的第一键合表面。第一硅穿孔(TSV)嵌入在第一衬底中并且部分地延伸通过第一衬底。第一TSV与第一键合表面正交延伸并且不在第一键合表面处暴露。
第一金属接触焊盘设置在第一键合表面处并且电耦合到第一TSV。第一金属接触焊盘相对于第一TSV偏移设置，不与第一TSV交叠，并且在第一键合表面下方部分地延伸到第一衬底中。一个或多个嵌入式导电迹线将第一TSV电耦合到第一金属接触焊盘。
参考电气部件和电子部件以及各种载体对各种实现方式和布置进行了讨论。虽然提及了特定部件(即，管芯、晶片、集成电路(IC)芯片管芯、衬底等)，但这并不旨在是限制性的，并且为了便于讨论和说明方便。参考晶片、管芯、衬底等所讨论的技术和设备可应用于任何类型或数目的电子部件、电路(例如，集成电路(IC)、混合电路、ASICS、存储器设备、处理器等)、部件组、封装部件、结构(例如，晶片、面板、板、PCB等)等，其可以被耦合以彼此进行接口连接、并且与外部电路、系统、载体等进行接口连接。这些不同部件、电路、组、封装、结构等中的每个部件、电路、组、封装、结构等都可以统称为“微电子部件”。为了简单起见，除非另有说明，否则键合到另一部件的部件本文中被称为“管芯”。
该发明内容并不旨在给出完整描述。下文使用多个示例对实现方式进行更详细的解释。尽管本文中和下文对各种实现方式和示例进行了讨论，但是通过组合各个实现方式和示例的特征和元件，其他实现方式和示例是可能的。
具体实施方式
概述
参考图1A(其示出了横截面轮廓视图)和图1B(其示出了俯视图)，图案化的金属和氧化物层经常作为混合键合、或
Figure BDA0002909414900000071
表面层而被设置在管芯、晶片或其他衬底(以下称为“管芯102”)上。可以使用各种技术来形成代表性器件管芯102，以包括基部衬底104和一个或多个绝缘或电介质层106。基部衬底104可以由硅、锗、玻璃、石英、电介质表面、直接间隙半导体材料或层、或间接间隙半导体材料或层或其他合适材料组成。绝缘层106被沉积或形成在衬底104上方，并且可以由诸如氧化物、氮化物、氧氮化物、碳氧化物、碳化物、碳氮化物、金刚石、类金刚石材料、玻璃、陶瓷、玻璃-陶瓷等之类的无机电介质材料层组成。
器件晶片102的键合表面108可以包括导电特征，诸如接触焊盘110、迹线112、以及其他互连结构，这些导电特征例如被嵌入绝缘层106中，并且被布置为使如果期望，则来自相面对的器件的相应键合表面108的导电特征110可以在键合期间被配合和接合。接合的导电特征110可以在堆叠器件之间形成连续导电互连(用于信号、功率等)。
镶嵌工艺(damascene process)(或类似工艺)可以用于在绝缘层106中形成嵌入式导电特征110。导电特征110可以由金属(例如，铜等)或其他导电材料或材料的组合组成，并且包括结构、迹线、焊盘、图案等。在一些示例中，在沉积导电特征110的材料之前，可以在用于导电特征110的空腔中沉积阻挡层，使得阻挡层设置在导电特征110与绝缘层106之间。阻挡层可以由例如钽或另一导电材料组成，以防止或减少导电特征110的材料扩散到绝缘层106中。在形成导电特征110之后，可以对器件晶片102的包括绝缘层106和导电特征110在内的暴露表面进行平坦化(例如，经由CMP)，以形成平坦键合表面108。
形成键合表面108包括：修整表面108以满足电介质粗糙度规格和金属层(例如，铜等)凹部规格，以制备表面108以供直接键合。换句话说，键合表面108被形成为尽可能平坦光滑，其中表面拓扑变化非常小。诸如化学机械抛光(CMP)、干法蚀刻或湿法蚀刻等之类的各种传统工艺可以用于实现低表面粗糙度。这些工艺提供了导致可靠键合的平坦光滑表面108。
在双面管芯102的情况下，可以在管芯102的两侧上提供具有制备好的键合表面108的图案化金属和绝缘层106。绝缘层106通常高度平坦(粗糙度通常达到纳米级)，其中金属层(例如，嵌入式导电特征110)位于键合表面108处或正好凹陷到键合表面108下面。通常，绝缘层106的表面108下面的凹陷量由尺寸公差、规格或物理限制确定。键合表面108通常使用化学机械抛光(CMP)步骤和/或其他制备步骤来制备，以与另一管芯、晶片或其他衬底直接键合。
一些嵌入式导电特征或互连结构可以包括金属焊盘110或导电迹线112，其在所制备的表面108下方部分地延伸到电介质衬底106中。比如，一些图案化金属(例如，铜)特征110或112可以是约0.5微米至2微米厚。这些特征110或112的金属可以在退火期间随着金属的加热而膨胀。其他导电互连结构可以包括金属(例如，铜)穿硅过孔(TSV)114等，其在与键合表面108正交的情况下部分地延伸通过或完全延伸通过衬底102、并且包括大量金属。比如，依据衬底102的厚度，TSV 114可以延伸约50微米。TSV 114的金属当被加热时还可以膨胀。焊盘110和/或迹线112可以或不可以电耦合到TSV 114，如图1A所示。
参考图2，可以在不使用粘合剂的情况下，将管芯102直接键合到具有金属焊盘110、迹线112和/或TSV 114的其他管芯102。如果金属焊盘110位于TSV 114上方(与TSV 114交叠并且物理和电性地耦合到该TSV 114)，则TSV 114金属的膨胀可以有助于焊盘110金属的膨胀。在一些情况下，随着膨胀金属上升到键合表面108上方，组合的金属膨胀会在TSV114(或TSV 114/焊盘110的组合)的地点处导致键合表面的局部分层202。比如，经膨胀金属可以使堆叠管芯102的键合的电介质表面108分开。
示例实施例
参考图3至图5，在各种实施例中，可以采用技术来减轻由于金属膨胀而引起的分层的可能性。例如，在一个实施例中，接触焊盘110可以设置在键合表面108上，相对于TSV114偏移，并且不与TSV 114交叠。接触焊盘110可以嵌入在电介质层106中，部分地延伸到键合表面108下方的电介质层106中，并且使用迹线112等电耦合到TSV114。在一些实施例中，金属焊盘110的尺寸可以基于焊盘110的材料、其厚度以及CMP处理期间的预期凹部来选择。
在各个实现方式中，当对管芯102进行热退火并且TSV 114的金属和接触焊盘110膨胀时，将接触焊盘110相对于TSV 114偏移设置(例如，接触焊盘110未设置在TSV 114上方或不与TSV 114交叠)减小或消除了键合的管芯102的分层。在各个实现方式中，TSV 114不会(或不太可能)将其膨胀金属贡献给经偏移的焊盘110的膨胀金属。因而，焊盘110中的预先确定的凹部可以足以为焊盘110的材料膨胀提供空间。
在一个实施例中，通过如下的方式来选择或形成接触焊盘110的尺寸：基于接触焊盘110的材料的体积和接触焊盘110的材料的热膨胀系数(CTE)来估计接触焊盘110的材料当被加热到预选温度(～300°)时将膨胀的量、并且预测接触焊盘110的材料当被加热到预选温度时将膨胀的量。接触焊盘110与电介质层106的键合表面108一起被平坦化，其包括基于估计和预测接触焊盘110的材料在预先确定的温度下的膨胀，使接触焊盘110凹陷以相对于键合表面108具有预先确定的凹陷深度(或量)。
在一个实施例中，可以(经由酸蚀刻、等离子体氧化等)选择性地蚀刻接触焊盘110以提供期望凹陷深度(以容纳所预测的金属膨胀)。在另一示例中，如图4所示，可以选择、形成或处理焊盘110或对应TSV 114，以使其具有非均匀顶部表面而作为膨胀缓冲器。例如，参考图4，焊盘110的顶部表面可以被形成或选择性地蚀刻为圆化、半球形、凸形、凹形、不规则形、或其他不平坦形状，以允许用于材料膨胀的附加空间402。
基于对接触焊盘110的材料当被加热时将膨胀的量的预测，可以确定并形成附加空间402。在各个实现方式中，接触焊盘110的顶部表面可以在沉积期间被形成为非均匀，或在形成接触焊盘110之后，该接触焊盘110可以被蚀刻、研磨、抛光、或以其他方式使其非均匀。在一些情况下，在键合表面108的CMP期间，可以使焊盘110的顶部表面非均匀。
附加地或可替代地，金属焊盘110周围的电介质106可以被形成或成形，为允许焊盘110的金属膨胀留出空间。在一个示例中，CMP工艺可以用于对金属焊盘110周围的电介质106的表面108进行成形，或在其他示例中，可以使用其他工艺，以使焊盘110周围的电介质106包括凹部或其他间隙，该凹部或其他间隙为金属膨胀提供了空间。在一个实施例中，可以在制备键合表面108的同时，使电介质106凹陷(例如，使用CMP)。在实施例中，金属焊盘110和电介质106可以同时凹陷(但是以不同速率)。比如，该工艺可以在使金属焊盘110凹陷的同时，在金属焊盘110的边缘周围的电介质106中形成腐蚀。
在各个实施例中，焊盘110和/或TSV 114由铜、铜合金等构成。在另一实施例中，可以使焊盘110和/或TSV 114的材料不同，以控制金属膨胀和可能形成的分层。比如，在一些实施例中，焊盘110和/或TSV 114可以由不同的导电材料组成，这些材料的CTE可能较低。在一些实施例中，TSV 114可以由与接触焊盘110不同的导电材料(具有较低的CTE)组成。例如，TSV 114可以由钨、合金等组成。
在其他实施例中，可以使TSV 114的材料的体积发生变化，以控制金属膨胀和可能形成的分层。比如，在一些实施例中，当这在设计规格内允许时，可以使用具有预选的材料体积(例如，材料体积的较小)的TSV 114。TSV 114的体积的预先选择可以基于TSV 114的预测材料膨胀。
可替代地，TSV 114的顶部表面可以被布置为在键合表面108处暴露并且用作接触焊盘。这种布置可以避免金属焊盘110的膨胀与TSV 114的膨胀进行组合，从而最小化或消除分层。
在另一实现方式中，如图5所示，凹部502设置在键合表面108中并且通过绝缘层106的一部分，以为TSV 114在z方向上的材料膨胀提供应力消除。比如，可以通过蚀刻电介质层106来形成凹部502。在实现方式中，凹部502的至少一部分设置在TSV 114上方(例如，与之交叠)。例如，基于TSV 114的特定金属的体积，使用对TSV 114的膨胀的预测，凹部502可以例如根据TSV 114的体积而被调整。在一些情况下，凹部502的直径或面积大于TSV 114的直径或横截面积。
凹部502可以暴露或不暴露TSV 114。凹部502的深度可以延伸到TSV 114或迹线112的顶部(比如，如果期望与TSV 114或迹线112接触)，但是凹部502的深度通常更浅，并且TSV 114和/或迹线112仍然由绝缘层106的一部分覆盖。凹部502可以保持敞开或可以填充有诸如柔顺材料之类的材料。
在制备键合表面108之后(例如，通过CMP)，比如，在无需粘合剂的情况下，管芯102可以直接键合到具有金属焊盘110、迹线112和/或TSV 114的其他管芯102。在相面对的管芯102的配合接触焊盘110键合以形成单个导电互连时，TSV 114的材料和焊盘110的材料在加热退火期间膨胀。然而，由于TSV 114的膨胀金属不与接触焊盘110的膨胀金属结合(因为接触焊盘110偏离TSV 114)，所以金属膨胀不会引起键合表面的分层。
进一步地，如果接触焊盘110充分凹陷，则接触焊盘110的膨胀金属不会使堆叠管芯102的经键合电介质表面108分开(参见图15至图19)。当使用诸如CMP之类的表面制备工艺来制备管芯102的键合表面108时，由于接触焊盘110(比如，其可以包括铜)相对于电介质106(例如，其可以包括氧化物)的柔软性，所以键合表面108上的金属焊盘110可能相对于电介质106凹陷(有意地或无意地)。
在各个实施例中，基于所使用的表面制备技术(例如，所使用的化学组合、抛光装备的速度等)、电介质层106和金属焊盘110的材料、金属焊盘110的间隔或密度、以及金属焊盘110的尺寸(例如，面积或直径)，可以预测金属焊盘110的凹陷量。在实施例中，基于金属焊盘110的凹部预测和预期金属膨胀，可以选择金属焊盘110(例如，针对特定金属厚度)的面积或直径，以避免经键合的管芯102的分层。
在各个实施例中，基于金属焊盘110的凹陷预测和预期金属膨胀，可以定制或选择被定位为偏离TSV 114的接触焊盘110的形状和尺寸，以避免分层。
附加实施例
图6至图14图示了根据各个实施例的背侧管芯102处理的示例。在一些实现方式中，在管芯102被堆叠并且被直接键合而无需粘合剂的情况下，当制备背侧602以用于直接键合时，管芯102的背侧602可以接收与顶部侧键合表面108不同的制备。代替在管芯102的背侧602上形成电介质层106，可以以不同方式制备背侧602以减少过程步骤，降低制造成本或其他原因。
在一个实现方式中，制备背侧602，以使TSV 114暴露，以用作用于键合到导电焊盘、互连或其他导电键合表面的接触表面。该制备可以包括：沉积一个或多个绝缘材料层并且对(例如，经由CMP)绝缘材料进行平坦化以露出TSV 114。然而，在一些情况下，TSV 114的材料在加热退火期间的膨胀会导致绝缘材料和/或衬底104被损坏。
在一个实施例中，如图6至图14所示，可以在背侧602上沉积具有不同残余应力特点的一个或多个无机电介质材料层，以平衡管芯102的器件侧上的应力并且使单片化之后的管芯翘曲最小。可以对绝缘材料层进行平坦化，或者以其他方式被制备为管芯102的背侧602上的键合表面。
如图6所示，TSV 114被设置在管芯102内，横向于管芯102的键合表面108。电介质衬里和扩散阻挡604包围TSV 114，以防止TSV 114的金属(例如，铜)扩散到基部衬底104的材料(例如，硅)中。减薄并选择性地蚀刻基部衬底104以暴露TSV 114的底部端，其中衬里和扩散阻挡层604保持完整。在一个实施例中，如图6所示，另一扩散阻挡层606沉积在管芯102的背侧602的表面上。在一个示例中，扩散阻挡606包括诸如氮化物等之类的电介质。
在各个实施例中，具有不同残余应力特点的一个或多个电介质层然后沉积到管芯102的背侧602上，以防止当TSV 114的材料膨胀时，对管芯102的损坏。例如，包括诸如氧化物之类的第一低温电介质的第一层608可以沉积在背侧602上方，其包括沉积在扩散层606上方。图7示出了前侧键合表面108上形成有接触焊盘110的这种场景。
如图8所示，对背侧602(该背侧602包括一个或多个电介质层608)进行平坦化(例如，经由CMP)，以形成用于直接键合的平坦光滑键合表面。剩余电介质层608可以基于电介质层608的残余应力特点来辅助翘曲控制。
在一个实施例中，如图9至图10所示，接触焊盘1004(或其他导电结构)可以在管芯102的背侧602上耦合到TSV 114。如图9所示，在沉积第一低温氧化物应力层608(其在一些实现方式中还包括键合层)之后，可以在第一层608上方沉积第二电介质层902(其可以包括低温氧化物)。在两个氧化物层(608和902)之间不需要阻挡层或粘合层。在各个实现方式中，第一层608和第二层902由相似或相同的材料(厚度不同)组成。在其他实现方式中，第一层608和第二层902由不同的材料组成。在备选实现方式中，附加电介质层还可以沉积在第一层608和第二层902上方。
背侧602被图案化并敞开(例如，蚀刻等)，以用于沉积导电焊盘1004。如图9所示，氧化物层608和902中的开口904的形状可以与TSV 114的形状不同。(用于RDL层的开口最可能是线，而非圆)。
在一个实施例中，用于导电焊盘1004的开口904延伸通过第二层902并且部分(10nm至1000nm)延伸到第一层608中。阻挡层/粘合层1002(包括钛/氮化钛、钽/氮化钽等)可以沉积到开口904中(并且可以覆盖开口904的整个表面)，如图10所示。铜(或类似物)沉积/镀覆(例如，镶嵌工艺)填充开口904，该开口904被平坦化(例如，经由CMP)以移除多余铜、并且将所得导电焊盘1004的凹部设置为指定深度。此时，可以制备背侧602表面以用于键合。可替代地，根据需要，双镶嵌工艺可以用于形成一互连，诸如导电结构1004。
在另一实施例中，如图11所示，可以在背侧602的表面上方(例如，第二层902和导电焊盘1004上方)沉积可以包括氮化硅等的薄(大约10nm至500nm)粘合层1102，随后沉积第三电介质层1104(例如，氧化物)作为背侧602的键合层(例如，DBI层)。可以对第三电介质层1104(顶部层)的厚度和导电焊盘1004的厚度进行调整，以使薄管芯翘曲最小并且实现期望退火温度。在各个实现方式中，第一层608、第二层902和第三层1104由相似或相同的材料(厚度不同)组成。在其他实现方式中，第一层608、第二层902和/或第三层1104中的一个或多个层由不同的材料组成。在备选实现方式中，还可以在第一层608、第二层610和第三层1104上方沉积附加电介质层，以平衡器件侧上的应力并且使晶片翘曲最小。
如图12所示，可以对第三层1104进行图案化和蚀刻，以用于焊盘1204的沉积。在第三层1104中蚀刻开口之后，可以沉积扩散层/粘合层1202(例如，Ti/TiN)，以对开口覆盖衬里，之后使用导电材料(例如，铜)(例如，经由镶嵌工艺)填充开口，以形成焊盘1204。对焊盘1204和第三层1104进行平坦化(例如，使用CMP)，以制备用于直接键合的背侧602、并且使焊盘1204凹陷以满足规格。在一个备选实施例中，如图13所示，双镶嵌工艺可以用于添加焊盘1204作为过孔层1302的一部分。
在一个实现方式中，如图14所示，可以在TSV 114上方的背侧602上蚀刻凹部1402，作为在退火期间用于金属膨胀的应力消除部。凹部1402设置在第三层1104(或背侧602的另一最上层(other top-last layer))的表面中、并且贯穿第三层1104的一部分，以为TSV114在z方向上的材料膨胀提供应力消除部。在该实现方式中，凹部1402的至少一部分被设置在TSV 114上方(例如，与之交叠)。基于TSV114的特定金属的体积，使用TSV 114的材料膨胀的预测，可以例如根据TSV 114的体积来调节凹部1402。在一些情况下，凹部1402的直径或面积大于TSV 114的直径或横截面积。凹部1402可以保持敞开或可以填充有诸如柔顺材料之类的材料。
在其他实施例中，备选技术可以用于减少或消除由于金属特征膨胀而引起的分层，并且仍在本公开的范围内。
图15至图19示出了参考图6至图14而形成的、具有前侧108和背侧602的互连性的管芯102(以及类似结构)的示例堆叠布置。例如，图15示出了示例“前到背”管芯102的堆叠布置。这将第一管芯102的前侧的键合表面108键合到第二管芯102的背侧602的键合表面，其包括将第一管芯102的接触焊盘110键合到第二管芯102的接触焊盘1204。在一个示例中，如上文所讨论的，第一管芯102和第二管芯102的导电结构1004穿透到第一管芯102和第二管芯102的相应键合表面602下方的第二电介质层902和第一电介质层608(而不穿过第一电介质层608)中。
图16示出了另一示例“前到背”管芯102堆叠布置。在图16所示的实施例中，每个管芯102包括凹部1402，该凹部位于管芯102的背侧602处并且通过最顶部层(在该示例中，第三层1104)。如上文所讨论的，凹部1402在加热退火期间提供来自的TSV 114的膨胀材料的应力消除。在一个实现方式中，凹部1402可以填充有柔顺材料。在一个示例中，如上文所讨论的，第一管芯102和第二管芯102的导电结构1004穿透到第一管芯102和第二管芯102的相应键合表面602下方的第二电介质层902和第一电介质层608(而不穿过第一电介质层608)。
图17示出了另一示例“前到背”管芯102堆叠布置。在图17所示的实施例中，每个管芯102包括多个接触焊盘110(其可以通过一个或多个迹线112等而被耦合到相应TSV 114)、和多个接触焊盘1204(其可以通过导电结构1004等耦合到相应TSV 114)。第一管芯102和第二管芯102被堆叠，以使第一管芯102的多个接触焊盘110被键合到第二管芯102的多个接触焊盘1204。
在各种实现方式中，管芯102可以包括凹部1402，该凹部1402设置在相应TSV 114上方的背侧602上(如图17所示)，以在加热退火期间提供来自TSV 114的膨胀材料的应力消除。在一个实现方式中，凹部1402可以填充有柔顺材料。在一个示例中，如上文所讨论的，第一管芯102和第二管芯102的导电结构1004穿透到第一管芯102和第二管芯102的相应键合表面602下方的第二电介质层902和第一电介质层608(而不穿过第一电介质层608)。
图18示出了示例“背到背”管芯102堆叠布置。这将第一管芯102的背侧602的键合表面键合到第二管芯102的背侧602的键合表面，其包括将第一管芯102的接触焊盘1204键合到第二管芯102的接触焊盘1204。在一个示例中，第一管芯102和第二管芯102的导电结构1004穿透到第一管芯102和第二管芯102的相应键合表面602下方的第二电介质层902和第一电介质层608(而不穿过第一电介质层608)。
图19示出了示例“前到前”管芯102的堆叠布置。这将第一管芯102的前侧键合表面108键合到第二管芯102的前侧键合表面108，其包括将第一管芯102的一个或多个接触焊盘110键合到第二管芯102的一个或多个接触焊盘110。在所示的示例中，接触焊盘110通过一个或多个迹线112等电耦合到相应管芯102的TSV 114。在一个示例中，如上文所讨论的，第一管芯102和第二管芯102的导电结构1004穿透到第一管芯102和第二管芯102的相应键合表面602下方的第二电介质层902和第一电介质层608(而不穿过第一电介质层608)。
在各个实施例中，如图20所图示的，除了电信号之外或代替电信号，一组堆叠管芯102的TSV 114中的一个或多个TSV 114可以用于传导热。例如，在一些情况下，将散热器(或其他传热设备)附接到一组堆叠管芯102的管芯102上以减轻管芯102所生成的热量可能不切实际或不太可能。可以根据期望寻找其他技术以传递热量。
在各个实施例中，如图20所示，可以采用包括TSV 114的各种配置，该TSV 114部分地或全部地延伸通过管芯102的TSV，以将热量传导离开管芯102(或远离管芯102的发热部分)。一个管芯102的TSV 114可以与第二管芯102的TSV 114、接触焊盘110、迹线112等结合使用，以完成从一个管芯102到另一管芯102的热传递等。第一管芯102的TSV 114可以直接键合(例如，DBI)到第二管芯102的TSV 114、接触焊盘110、迹线112等，以实现高性能的导热性。
在一个实现方式中，TSV 114、接触焊盘110、迹线112等中的一些TSV 114、接触焊盘110、迹线112等是电浮置结果或“虚拟”结构，其可以用于热传递。这些结构可以根据需要将热量传导远离高功率芯片102，或传导到另一芯片102或衬底。虚拟接触焊盘110可以经由最后热TSV或中间热TSV 114而被耦合以用于热传导。
在各个实施例中，扩散阻挡层604(该扩散阻挡层604包围TSV114并且可以是热约束阻挡或热阻挡)可以被由具有一定导热性的不同材料制成的扩散阻挡(诸如金属阻挡或合金阻挡等)替换。
示例过程
图21图示了代表性过程2100，其用于制备各种微电子部件(例如，诸如管芯102)，这些部件用于诸如在无需粘合剂的情况下直接键合之类的键合，同时减少或消除由于嵌入式结构在键合表面处的金属膨胀而引起的分层的可能性。比如，由于TSV和接触焊盘的材料在加热退火期间会膨胀，所以键合表面处的穿硅过孔(TSV)可能导致分层，尤其是当耦合到接触焊盘时。该过程参考图1至图20。
描述过程的次序不旨在被解释为限制性的，并且过程中的任何数目的所描述的过程框可以以任何次序组合以实现该过程或备选过程。附加地，在没有背离本文中所描述的主题的精神和范围的情况下，可以从过程中删除各个框。更进一步地，可以在没有背离本文中所描述的主题的范围的情况下，以任何合适硬件、软件、固件或其组合来实现该过程。在备选实现方式中，其他技术可以各种组合包括在该过程中，并且仍在本公开的范围内。
在一个实现方式中，使用各种技术形成管芯、晶片或其他衬底(“衬底”)，以包括基部衬底和一个或多个电介质层。在该实现方式中，在框2102处，该过程2100包括：将第一穿硅过孔(TSV)(例如，诸如TSV 114)嵌入具有第一键合表面(例如，诸如键合表面108)的第一衬底中，第一TSV部分地延伸通过第一衬底，与第一键合表面正交并且未在第一键合表面处暴露。
在实现方式中，在框2104处，该过程包括：在第一键合表面处设置第一金属接触焊盘(例如，接触焊盘110)，该第一金属接触焊盘相对于第一TSV偏移、不与第一TSV交叠并且在第一键合表面下方部分地延伸到第一衬底中。在一个实现方式中，该过程包括：基于第一金属接触焊盘的材料的体积和第一金属接触焊盘的材料的CTE，预测第一金属接触焊盘的材料当被加热到预选温度时将膨胀的量；以及基于预测来选择第一金属接触焊盘。在一个示例中，选择包括：选择第一金属接触焊盘的直径或表面积。
在另一示例中，该过程包括：确定第一金属接触焊盘相对于第一键合表面的期望凹部，以允许第一金属接触焊盘的材料膨胀；以及，选择第一金属接触焊盘，以当第一金属接触焊盘被平坦化时具有可能导致期望凹部的周边形状。在一个实施例中，该过程包括：基于第一金属接触焊盘的直径或面积，预测由于平坦化而可能在第一金属接触焊盘的表面中发生的凹陷量；以及基于预测来选择第一金属接触焊盘。
在一个实现方式中，该过程包括：确定第一金属接触焊盘相对于第一键合表面的期望凹部，以允许第一金属接触焊盘的材料膨胀；在第一金属接触焊盘的表面中形成期望凹部。在一个示例中，该过程包括：将第一金属接触焊盘的表面形成为具有半球形拓扑或非均匀拓扑。
在框2106处，该过程包括：使用一个或多个嵌入式导电迹线(例如，诸如导电迹线112)，将第一金属接触焊盘电耦合到第一TSV。
在一个实现方式中，该过程包括：对第一键合表面进行平坦化，以具有用于直接键合的预先确定的最大表面变化；并且对第一金属接触焊盘进行平坦化，以相对于第一键合表面具有预先确定的凹部。
在一个实现方式中，该过程包括：在第一TSV上方的第一键合表面中形成凹部(例如，诸如凹部502)。在一个示例中，该过程包括：基于第一TSV的材料的体积和第一TSV的材料的热膨胀系数(CTE)，估计第一TSV的材料当被加热到预选温度时将膨胀的量；并且基于第一TSV的材料的体积和第一TSV的材料的热膨胀系数(CTE)，确定第一键合表面中的凹部的深度和面积。比如，该过程可以包括：在第一键合表面中形成凹部，以使其直径比第一TSV的直径大预先确定的量。
在一个实现方式中，该过程包括：在第一衬底的与绝缘层相对的第二表面上沉积一个或多个绝缘应力消除层，以及对一个或多个应力消除层进行平坦化，以形成具有第二预先确定的最大表面变化的第二键合表面。在一个示例中，该过程包括：在第一衬底的第二表面上沉积第一低温绝缘层，在第一低温绝缘层上方沉积第二低温绝缘层，以及在第二低温绝缘层上方沉积第三绝缘层，以形成第二键合表面。
在一个实现方式中，该过程包括：对第二低温绝缘层进行图案化；在第一TSV上方蚀刻开口，该开口延伸通过第二低温绝缘层并且部分通过第一低温绝缘层；在开口内沉积导电材料以形成导电焊盘，该导电焊盘电耦合到第一TSV；并且在第二低温绝缘层和导电焊盘上方沉积第三绝缘层。在一个示例中，该过程包括：在将导电材料沉积在开口内之前，将阻挡层沉积到开口的被暴露表面上。
在另一实现方式中，该过程包括：对第三绝缘层进行图案化；在导电焊盘上方蚀刻第二开口，该第二开口延伸通过第三绝缘层并且暴露导电焊盘；以及在第二开口内沉积导电材料以形成电耦合到导电焊盘的第二接触焊盘。
在一个实现方式中，该过程包括：在第一衬底的第二键合表面处或在第一衬底的第一键合表面处，使用直接电介质到电介质非粘合剂键合技术将第一衬底直接键合到第二衬底。
在一个备选实现方式中，该过程包括：经由第一TSV以及嵌入到第二衬底内并暴露在第二衬底的键合表面处的一个或多个导电结构，将热量从第一衬底传递到第二衬底。
在各种实施例中，与本文中所描述的过程步骤相比较，可以修改或消除一些过程步骤。
本文中所描述的技术、部件和设备不限于图1至图21的图示，并且在没有背离本公开的范围的情况下，可以应用于其他设计、类型、布置、以及构造，其包括与其他电气部件一起应用在内。在一些情况下，附加或备选部件、技术、序列或过程可以用于实现本文中所描述的技术。进一步地，可以以各种组合布置和/或组合部件和/或技术，同时产生的结果相似或近似相同。
结论
尽管已经以特定于结构特征和/或方法动作的语言对本公开的实现方式进行了描述，但是应当理解，实现方式不必限于所描述的特定特征或动作。相反，特定特征和动作被公开为实现示例设备和技术的代表性形式。

Claims (20)

1.一种形成微电子组件的方法，包括：
将第一穿硅过孔(TSV)提供到具有第一键合表面的第一衬底中，所述第一TSV在一方向上从所述第一键合表面延伸通过所述第一衬底的至少一部分；
在键合层中提供凹部，其中至少一个第一凹部在与所述第一键合表面正交的方向上与所述TSV对准，并且至少一个第二凹部在与所述第一键合表面正交的所述方向上偏移并且不与所述TSV交叠；以及
在所述第二凹部中设置第一金属接触焊盘，所述第一金属接触焊盘位于所述第一键合表面处或从所述第一键合表面稍微凹陷，所述第一金属接触焊盘使用一个或多个嵌入式导电迹线而被电耦合到所述第一TSV。
2.根据权利要求1所述的形成微电子组件的方法，其中所述迹线被提供为重分布层的一部分，并且所述重分布层的至少一部分位于所述第一TSV与所述第一凹部之间。
3.根据权利要求2所述的形成微电子组件的方法，其中所述第一凹部在键合过程期间补偿所述导电过孔的膨胀。
4.根据权利要求2所述的形成微电子组件的方法，还包括：在所述第一键合表面中形成所述凹部，以使所述凹部的直径比所述第一TSV的直径大预先确定的量。
5.根据权利要求1所述的形成微电子组件的方法，还包括：使所述第一金属接触焊盘的表面成形。
6.根据权利要求1所述的形成微电子组件的方法，还包括：从所述第一衬底移除材料，以从与所述第一键合表面相对的一侧暴露所述TSV。
7.根据权利要求1所述的形成微电子组件的方法，还包括：将所述第一衬底键合到第二衬底，所述第一凹部与位于所述第一衬底和所述第二衬底之间的键合界面相邻。
8.一种形成微电子组件的方法，包括：
形成第一衬底以具有基部层以及所述基部层上的绝缘层，所述绝缘层具有第一键合表面，第一穿硅过孔(TSV)在与所述第一键合表面正交的方向上至少部分地延伸通过所述第一衬底的所述基部层；
在所述第一键合表面中形成与所述第一TSV交叠的凹部，所述凹部被配置为在键合步骤期间补偿所述TSV的热膨胀；
在所述第一键合表面处设置第一金属接触焊盘，所述第一金属接触焊盘相对于所述第一TSV的位置偏移；以及
使用一个或多个嵌入式导电迹线将所述第一金属接触焊盘电耦合到所述第一TSV。
9.根据权利要求8所述的形成微电子组件的方法，还包括：对所述第一键合表面进行平坦化，以具有用于直接键合的预先确定的最大表面变化，并且对所述第一金属接触焊盘进行平坦化，以相对于所述第一键合表面具有预先确定的凹部。
10.根据权利要求8所述的形成微电子组件的方法，还包括：在所述第一衬底的与所述绝缘层相对的第二表面上沉积一个或多个无机电介质层，并且对所述一个或多个无机电介质层进行平坦化，以形成具有第二预先确定的最大表面变化的第二键合表面。
11.根据权利要求10所述的形成微电子组件的方法，其中所述沉积包括：在所述第一衬底的所述第二表面处沉积第一低温绝缘层，在所述第一低温绝缘层上沉积第二低温绝缘层，以及在所述第二低温绝缘层上沉积第三绝缘层，以形成所述第二键合表面。
12.根据权利要求11所述的形成微电子组件的方法，还包括：
对所述第二低温绝缘层进行图案化；
在所述第一TSV上蚀刻开口，所述开口延伸通过所述第二低温绝缘层并且部分地延伸通过所述第一低温绝缘层；以及
在所述开口内沉积导电材料以形成导电焊盘，所述导电焊盘被电耦合到所述第一TSV；
相对于第二键合层在所述导电材料中或在所述导电材料上方形成凹部。
13.根据权利要求12所述的形成微电子组件的方法，还包括：在将所述导电材料沉积在所述开口内之前，将粘合层/阻挡层沉积到所述开口的暴露表面上。
14.根据权利要求14所述的形成微电子组件的方法，还包括：在所述第一衬底的所述第二键合表面处，使用直接电介质到电介质、非粘合剂键合技术将所述第一衬底直接键合到第二衬底。
15.根据权利要求14所述的形成微电子组件的方法，还包括：在所述第一衬底的所述第一键合表面处，使用直接电介质到电介质、非粘合剂键合技术将所述第一衬底直接键合到第二衬底。
16.一种微电子组件，包括：
第一衬底，包括具有平坦化形貌的第一键合表面，所述平坦化形貌具有第一预先确定的最大表面变化；
第一穿硅过孔(TSV)，被嵌入在所述第一衬底中并且至少部分地延伸通过所述第一衬底，所述第一TSV与所述第一键合表面正交地延伸并且在所述第一键合表面处不被暴露；
第一金属接触焊盘，设置在所述第一键合表面处并且电耦合到所述第一TSV，所述第一金属接触焊盘被设置为相对于所述第一TSV偏移、不与所述第一TSV交叠，并且在所述第一键合表面下方部分地延伸到所述第一衬底中；以及
一个或多个嵌入式导电迹线，将所述第一TSV电耦合到所述第一金属接触焊盘。
17.根据权利要求16所述的微电子组件，还包括在所述第一键合表面中的、位于所述第一TSV上方的凹部。
18.根据权利要求16所述的微电子组件，还包括所述第一衬底的第二表面上的一个或多个电介质应力消除层，所述一个或多个电介质应力消除层被平坦化，以形成具有第二预先确定的最大表面变化的第二键合表面。
19.根据权利要求18所述的微电子组件，所述一个或多个应力消除层包括所述第一衬底的所述第二表面处的第一低温绝缘层、所述第一低温绝缘层上的第二低温绝缘层、以及所述第二低温绝缘层上的第三绝缘层，以形成所述第二键合表面。
20.根据权利要求16所述的微电子组件，还包括第二衬底，在所述第一衬底的所述第一键合表面处或在所述第一衬底的第二键合表面处，使用直接电介质到电介质、非粘合剂键合技术，将所述第二衬底直接键合到所述第一衬底。
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