TW202002111A - 用作襯墊的直通矽穿孔 - Google Patents

用作襯墊的直通矽穿孔 Download PDF

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Publication number
TW202002111A
TW202002111A TW108120530A TW108120530A TW202002111A TW 202002111 A TW202002111 A TW 202002111A TW 108120530 A TW108120530 A TW 108120530A TW 108120530 A TW108120530 A TW 108120530A TW 202002111 A TW202002111 A TW 202002111A
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Taiwan
Prior art keywords
substrate
conductive
tsv
bonding
microelectronic assembly
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TW108120530A
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English (en)
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桂蓮 高
李奉燮
蓋烏斯 吉爾曼 方騰二世
賽普里恩 艾米卡 烏佐
貝高森 哈巴
蘿拉 威爾 麥卡雷米
拉杰詡 卡特卡
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美商英帆薩斯邦德科技有限公司
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Publication of TW202002111A publication Critical patent/TW202002111A/zh

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Abstract

包括製程步驟之代表性技術及裝置可用於降低接合微電子基板歸因於接合界面處之金屬膨脹而脫層之可能性。例如，直通矽穿孔（TSV）可穿過該些微電子基板中之至少一者而安置。該TSV在該基板之該接合界面處經暴露且充當一接觸表面以供直接接合。

Description

用作襯墊的直通矽穿孔
以下描述係關於積體電路。更特定而言，以下描述係關於製造IC晶粒及晶圓。 優先權主張及相關申請案之交叉參考
本申請案主張2019年6月12日提交的美國非臨時申請案第16/439,360號及2018年6月13日提交的美國臨時申請案第62/684,505號之權益，該些美國非臨時申請案及美國臨時申請案以全文引用之方式併入本文中。
微電子元件常常包含諸如矽或砷化鎵之半導體材料的薄平板，通常被稱作半導體晶圓。晶圓可經形成為包括晶圓表面上及/或部分嵌入晶圓內之多個整合式晶片或晶粒。從晶圓分離之晶粒通常作為個別預封裝單元提供。在一些封裝設計中，晶粒經安裝至基板或晶片載體，該基板或晶片載體又安裝在諸如印刷電路板（printed circuit board；PCB）之電路面板上。舉例而言，許多晶粒經設置於適合於表面黏著的封裝中。
經封裝半導體晶粒亦可以「堆疊」配置來提供，其中一個封裝設置於例如電路板或其他載體上，且另一封裝經安裝在第一封裝之頂部上。該些配置可允許若干不同晶粒或裝置經安裝於電路板上之單個覆蓋面積內，且可藉由在封裝之間設置較短互連來進一步促成高速操作。通常，此互連距離可僅略大於晶粒自身之厚度。對於將在晶粒封裝之堆疊內達成的互連，用於機械及電性連接之互連結構可設置於每一晶粒封裝（除了最頂封裝以外）之兩側（例如，面）上。
此外，晶粒或晶圓可以三維配置堆疊作為各種微電子封裝方案之部分。此可包括在較大基底晶粒、裝置、晶圓、基板或類似者上堆疊一或多個晶粒、裝置及/或晶圓之層，以垂直或水平配置堆疊多個晶粒或晶圓，以及兩者之各種組合。
晶粒或晶圓可使用各種接合技術（包括直接介電質接合、非黏著性技術（諸如ZiBond®）或混合接合技術（諸如DBI®），二者均可購自英帆薩斯邦德科技有限公司（前Ziptronix有限公司）、Xperi公司）以堆疊配置接合。接合包括當兩個製備表面結合在一起時在環境條件下發生的自發性過程（參見例如美國專利第6,864,585及7,485,968號，該些專利全文併入本文中）。
接合晶粒或晶圓之各別配合表面常常包括嵌入式導電互連結構（其可為金屬）或其類似者。在一些實例中，接合表面經配置且對準使得來自各別表面之導電互連結構在接合期間連接。連接的互連結構在堆疊晶粒或晶圓之間形成連續導電互連（用於信號、功率等）。
對於實施堆疊式晶粒及晶圓配置可存在多種挑戰。當使用直接接合或混合接合技術來接合堆疊晶粒時，通常需要待接合之晶粒的表面極平坦、光滑且潔淨。例如，一般而言，該些表面應具有極低的表面拓樸變化（亦即，奈米尺度變化），使得該些表面可緊密配合以形成持久接合。
可形成雙側晶粒並準備進行堆疊及接合，其中晶粒之兩側將諸如利用多個晶粒與晶粒或晶粒與晶圓的應用而接合至其他基板或晶粒。製備晶粒之兩側包括：對兩個表面進行表面處理以符合介電質粗糙度規格及金屬層（例如銅等）凹部規格。舉例而言，接合表面處的導電互連結構可輕微凹進，略低於接合表面之絕緣材料。可藉由裝置或應用之尺寸公差、規格或實體限制來判定低於接合表面之凹進量。可使用化學機械拋光（chemical mechanical polishing；CMP）製程或其類似者來製備混合表面以與另一晶粒、晶圓或其他基板接合。
一般而言，當含有介電層及一或多個金屬特徵（例如，嵌入式導電互連結構）之組合的直接接合表面接合在一起時，介電質表面首先在較低溫度下接合，且特徵之金屬隨後膨脹，因為金屬在退火期間經加熱。金屬之膨脹可導致來自兩個接合表面之金屬結合成統一的導電結構（金屬與金屬的接合）。當基板及金屬兩者在退火期間經加熱時，金屬之熱膨脹係數（coefficient of thermal expansion；CTE）相對於基板之CTE通常指示在特定溫度下（例如，約300C）金屬比基板膨脹得更多。舉例而言，銅之CTE為16.7，而熔融矽石之CTE為0.55，且矽之CTE為2.56。
在一些狀況下，金屬相對於基板之較大膨脹對於堆疊晶粒或晶圓之直接接合可能成問題。若金屬襯墊定位在直通矽穿孔（through-silicon via；TSV）上方，則TSV金屬之膨脹可能促使襯墊金屬之膨脹。在一些狀況下，當膨脹的金屬上升至接合表面上方時，組合的金屬膨脹可能會引起接合表面之局域化脫層。舉例而言，膨脹金屬可將堆疊晶粒之接合的介電質表面分離。
揭示代表性技術及裝置，該代表性技術及裝置包括：用於製備用於接合，諸如在無黏著劑之情況下用於直接接合之各種微電子裝置的製程步驟。在各種具體實例中，技術可用於降低歸因於金屬膨脹而脫層之可能性，尤其當TSV或TSV上方之接合襯墊在一個或兩個裝置之接合表面處呈現待接合時。例如，在一個具體實例中，TSV可部分或完全地延伸穿過裝置之基板，且TSV之至少一個端部在裝置之接合表面處經暴露。例如，TSV之暴露端部經製備且用作接合表面或替代裝置之接合襯墊。
當使用諸如CMP之表面製備製程來製備基板之接合表面時，TSV之暴露金屬端部在接合表面處可相對於介電質凹進，歸因於TSV之材料相對於介電質之材料較軟。較大直徑TSV相較於較小直徑TSV可在更大程度上凹進（例如，較深凹部）。在此具體實例中，TSV之末端表面之凹部在加熱退火期間為TSV之金屬膨脹提供空間，這可減少或消除可另外出現之脫層。
在各種實施中，實例製程包括提供穿過具有第一接合表面之第一基板之導電穿孔。該導電穿孔自該第一接合表面延伸而至少部分地穿過該第一基板。該製程包括自與該第一接合表面相對之表面暴露該導電穿孔，且形成與在第二接合表面處或相對於第二接合表面凹進之導電穿孔的第二接合表面。
在各種具體實例中，該製程包括藉由選擇導電穿孔及使用導電穿孔之至少一個端部作為用於直接接合（例如，DBI）之接合接觸表面而減少或排除接合微電子構件之脫層。
另外或替代地，該第一基板之後側亦可經處理以供接合。預先選擇材料之一或多個絕緣層可沉積於該第一基板之後側上以在該第一基板之後側將直接接合時提供應力消除。
另外，導電穿孔，以及該第一基板內之其他導電穿孔可用於在該第一基板內引導或傳遞熱及/或引導或傳遞熱遠離該第一基板。在一些實施中，傳熱導電穿孔可部分或完全地延伸穿過該第一基板之厚度且可包括導熱障壁層。在此等實例中，替代地，傾向於隔熱的通常圍繞導電穿孔使用之障壁層可由導熱層替換。在各種實施中，一些導電穿孔可用於信號傳遞及傳熱。
在一具體實例中，微電子總成包含具有前側及後側之第一基板，其中該後側具有包含非導電接合層及導電穿孔之接合表面。第二基板具有前側及後側，且該前側包括非導電接合層及導電特徵。該第二基板之該前側直接接合至該第一基板之該後側使得導電襯墊與導電特徵接觸。導電穿孔之暴露端部包含適合於直接的金屬與金屬的接合而無需中間材料之接觸表面。
參考電性及電子構件及各種載體論述各種實施及配置。雖然提及特定構件（亦即，晶粒、晶圓、積體電路（IC）晶片晶粒、基板等），但此並不意欲為限制性的且係為了易於論述及便於說明。參考晶圓、晶粒、基板或其類似者論述之技術及裝置適用於任何類型或數目之電性構件、電路（例如積體電路（IC）、混合電路、ASIC、記憶體裝置、處理器等）、構件之群組、封裝構件、結構（例如晶圓、面板、板、PCB等）以及其類似者，其可經耦接以彼此介接，與外部電路、系統、載體以及其類似者介接。此等不同構件、電路、群組、封裝、結構及其類似者中之每一者可一般被稱作「微電子構件」。為簡單起見，除非另外指定，否則接合至另一構件之構件將在本文中被稱作「晶粒」。
此概述並不意欲給出完整描述。在下文使用複數個實例來更詳細地解釋實施。雖然在此處且在下文論述各種實施及實例，但其他實施及實例可藉由組合個別實施及實例之特徵及元件而成為可能。
概述
參看圖1A（展示橫截面剖面圖）及圖1B（展示俯視圖），圖案化金屬及氧化物層經頻繁設置於晶粒、晶圓或其他基板（下文中為「晶粒102」）上以作為混合接合或DBI® 表面層。代表性裝置晶粒102可使用各種技術形成，以包括基底基板104及一或多個絕緣或介電層106。基底基板104可包含矽、鍺、玻璃、石英、介電質表面、直接或間接能隙半導體材料或層或另一合適材料。絕緣層106沉積或形成於基板104上方，且可包含無機介電材料層，諸如氧化物、氮化物、氮氧化物、碳氧化物、碳化物、碳氮化物、金剛石、類金剛石材料、玻璃、陶瓷、玻璃陶瓷及其類似者。
裝置晶圓102之接合表面108可包括導電特徵，諸如接觸襯墊110、跡線112及其他互連結構，例如嵌入至絕緣層106中且經配置以使得來自相對裝置之各別接合表面108之導電特徵110可視需要在接合期間配合及結合。結合的導電特徵110可形成堆疊裝置之間的連續導電互連（用於信號、功率等）。
鑲嵌製程（或其類似者）可用以在絕緣層106中形成嵌入式導電特徵110。導電特徵110可包含金屬（例如，銅等）或其他導電材料或材料組合，且包括結構、跡線、襯墊、圖案等。在一些實例中，障壁層可在沉積導電特徵110之材料之前經沉積在用於導電特徵110之空腔中，使得障壁層安置於導電特徵110與絕緣層106之間。該障壁層可包含例如鉭或另一導電材料，以防止或縮減導電特徵110之材料擴散至絕緣層106中。在形成導電特徵110之後，可（例如經由CMP）使裝置晶圓102（其包括絕緣層106及導電特徵110）之經暴露表面平坦化以形成平坦接合表面108。
形成接合表面108包括加工表面108以符合介電質粗糙度規格及金屬層（例如銅等）凹部規格，以製備用於直接接合之表面108。換言之，接合表面108經形成為儘可能平坦且光滑的，且具有極小表面拓樸變化。各種習知製程（諸如化學機械拋光（CMP）、乾式或濕式蝕刻等）可用於實現低表面粗糙度。此等製程提供產生可靠接合之平坦光滑表面108。
在雙側晶粒102之狀況下，具有經製備接合表面108的圖案化金屬及絕緣層106可設置於晶粒102之兩側上。絕緣層106通常為高度平坦的（通常為nm級粗糙度），其中金屬層（例如，嵌入式導電特徵110）在接合表面108處或正好凹進至該接合表面下方。在絕緣層106之表面108下方凹進的量通常藉由尺寸公差、規格或實體限制判定。常常使用化學機械拋光（CMP）步驟及/或其他製備步驟來製備接合表面108以便與另一晶粒、晶圓或其他基板直接接合。
一些嵌入式導電特徵或互連結構可包含在經製備表面108下方部分地延伸至介電基板106中之金屬襯墊110或導電跡線112。舉例而言，一些圖案化金屬（例如，銅）特徵110或112可為約0.5至2微米厚。此等特徵110或112之金屬可在金屬在退火期間經加熱時膨脹。其他導電互連結構可包含金屬（例如，銅）直通矽穿孔（TSV）114或其類似者，其垂直於接合表面108延伸，部分或完全地延伸穿過基板102並且包括較大數量的金屬。舉例而言，TSV 114可取決於基板102之厚度而延伸約50微米。TSV 114之金屬亦可在加熱時膨脹。襯墊110及/或跡線112可或可不電耦接至TSV 114，如圖1A中所示。
參看圖2，晶粒102可直接接合，例如而無需黏著至具有金屬襯墊110、跡線112及/或TSV 114之其他晶粒102。若金屬襯墊110位於TSV 114上方（與TSV 114重疊及實體耦接且電耦接至該TSV），則TSV 114金屬之膨脹可促成襯墊110金屬之膨脹。在一些狀況下，組合的金屬膨脹可引起接合表面在TSV 114 （或TSV 114/襯墊110組合）之位置處的局域化脫層202，因為膨脹的金屬會上升至接合表面108上方。舉例而言，膨脹金屬可使堆疊晶粒102之接合的介電質表面108分離。 例示性具體實例
參看圖3A至圖6，在各種具體實例中，技術可用於降低歸因於金屬膨脹而脫層之可能性。例如，在一個具體實例中，如圖3A及圖3B中所示，TSV 114可延伸穿過晶粒102之基底層104，且延伸穿過一或多個絕緣層106到達至少一個接合表面108。TSV 114之一端部302 （或兩端部302）可在晶粒102之（多個）接合表面108處經暴露且用作接觸表面以供直接接合（例如，DBI）。換言之，TSV之接觸表面302可在接合表面處經由介電層106暴露，經製備（例如，平坦化等等），及替代直接接合襯墊使用（代替接觸襯墊110）。
參考圖4，在各種實施中，當晶粒102經加熱退火且TSV 114及接觸襯墊110之金屬膨脹時，使用TSV 114之末端表面302作為接合表面可減少或消除接合晶粒102之脫層。在該實施中，可基於TSV 114之體積考慮TSV 114之金屬膨脹。因此，TSV 114之末端表面302中之預定凹進「d」（例如如圖5中所示）可足以為TSV 114之材料膨脹提供空間。
在各種具體實例中，用作直接接合接觸結構之TSV 114可具有比安置在晶粒102內其他地方之其他TSV 114大或小一預先選擇量之直徑。在一具體實例中，藉由基於TSV 114之材料體積及TSV 114之材料之熱膨脹係數（CTE）而估計TSV 114之材料在加熱至預先選擇溫度（約300°）時將膨脹之量且預測TSV 114之材料在加熱至該預先選擇溫度時將膨脹之量而選擇或形成TSV 114之大小。
參看圖5，在一具體實例中，TSV 114之端部302與介電層106之接合表面108一起經平坦化，包括基於TSV 114材料在預定溫度下之膨脹使TSV 114之端部302相對於接合表面108凹進以具有預定凹進深度（「d」）。換言之，基於TSV 114之材料之體積及TSV 114之材料之熱膨脹係數（CTE）而判定凹進深度。
在一個具體實例中，TSV 114之端部302可選擇性地經蝕刻（經由酸蝕刻、電漿氧化等等）以提供所要凹進深度「d」（以適應經預測金屬膨脹）。在另一實例中，如在圖6處所示，對應TSV 114之端部302可經選擇、形成或處理以具有不平坦的頂部表面作為膨脹緩衝區。例如，參看圖6，TSV 114之末端表面302可形成或選擇性地經蝕刻為圓形、半球形、凸形、凹形、不規則形，或以其他方式為非平坦的以實現用於材料膨脹之額外空間602。
可基於TSV 114之材料在加熱時將膨脹之量判定及形成額外空間602。在各種實施中，TSV 114之末端表面302可在沉積期間形成為不平坦的，或可在形成TSV 114之後經蝕刻、研磨、拋光或以其他方式變得不平坦。在一些狀況下，TSV 114之末端表面302可在接合表面108之CMP期間變得不平坦。
另外或替代地，圍繞TSV 114之在接合表面108處之介電質106可經形成或塑形以實現供TSV 114之金屬膨脹之空間。在一個實例中，CMP製程可用於塑形圍繞TSV 114之介電質106之表面108，或在其他實例中，可使用其他製程，使得圍繞TSV 114之介電質106包括為金屬膨脹提供空間之凹部或其他間隙。在一具體實例中，當製備接合表面108時，介電質106可凹進（例如，運用CMP）。在該具體實例中，TSV 114及介電質106可同時凹進（但以不同速率）。例如，該製程可在使金屬TSV 114凹進時圍繞TSV 114之邊緣形成介電質106中之腐蝕。
在各種具體實例中，TSV 114由銅、銅合金或其類似者構成。在另一具體實例中，TSV 114之材料可不同以控制金屬膨脹及可能的所得脫層。舉例而言，在一些具體實例中，TSV 114可包含可能具有較低CTE之不同導電材料。在一些具體實例中，TSV 114可包含不同於接觸襯墊110之導電材料（具有較低CTE）。舉例而言，TSV 114可包含鎢、合金或其類似者。
在其他具體實例中，TSV 114之材料的體積可不同以控制金屬膨脹及產生分層之可能性。舉例而言，在一些具體實例中，具有預先選擇材料體積（例如，較小材料體積）之TSV 114可在設計規格允許時使用。 TSV 114之體積之預選可基於TSV 114之預期材料膨脹。
返回參看圖4，在（例如藉由CMP）製備接合表面108之後，晶粒102可例如直接接合，而無需黏著至具有金屬襯墊110、跡線112及/或TSV 114之其他晶粒102。當相對晶粒102之配合TSV 114接合以形成單個導電互連件時，TSV 114之材料在加熱退火期間膨脹。然而，當如所論述提供充足預定凹部時金屬膨脹不會引起接合表面之脫層，由於TSV 114之膨脹金屬不會超出由TSV 114之末端表面302處之凹部提供的空間。
例如，若TSV 114之末端表面302充分凹進，則TSV 114之膨脹金屬填充（多個）凹部而無需使堆疊晶粒102之接合介電質表面108分離。當使用諸如CMP之表面製備製程製備晶粒102之接合表面108時，在接合表面108處暴露之TSV 114可相對於介電質106變得凹進（有意地或無意地），歸因於TSV 114 （其可包含例如銅）相對於介電質106 （其可包含例如氧化物）之柔軟度。
在各種具體實例中，可基於所使用表面製備技術（例如，所使用化學組合、拋光裝備之速度等等）、介電層106及TSV 114之材料、TSV 114 （及金屬襯墊110）之間隔或密度，及TSV 114之大小（例如，面積或直徑）預測TSV 114之凹進量。在該些具體實例中，TSV 114之面積或直徑可基於TSV 114之所要凹部及預期金屬膨脹而選擇（例如，針對特定材料）以免接合晶粒102發生脫層。例如，在一些狀況下，可在需要增大之凹進時選擇較大直徑TSV 114。此技術可減少或排除脫層，以及在接合表面108處引起介電質106與金屬結構（例如，TSV 114）之可靠機械耦接及接合金屬結構之可靠電性連續性。 額外具體實例
圖7至圖13說明根據各種具體實例之後側晶粒102處理之實例。在一些實施中，在晶粒102經堆疊且在無黏著劑之情況下直接接合的情況下，當晶粒102之後側702經製備以供直接接合時，該後側702可接收與頂側接合表面108不同之製備。代替在晶粒102之後側702上形成介電層106，後側702可以不同方式製備以縮減製程步驟，縮減製造成本，或用於其他原因。
在一個實施中，後側702經製備使得TSV 114被暴露，以用作用於接合至導電襯墊、互連件或其他導電接合表面之接觸表面302。製備可包括沉積絕緣材料之薄層及平坦化（例如經由CMP）後側702 （其可包括平坦化絕緣材料及/或基底基板104）以顯露TSV 114。然而，在一些狀況下，TSV 114之材料在加熱退火期間之膨脹可致使絕緣材料及/或基板104受損。
在一具體實例中，如圖7至圖13中所示，一或多個材料層可沉積於後側702上作為應力消除件以防止或消除對基板104及晶粒102之損壞。材料層可經平坦化並以其他方式製備成晶粒102之後側702上之接合表面。
如圖7處所示，TSV 114橫向於晶粒102之接合表面108安置於晶粒102內。TSV 114最初可延伸超出晶粒102之後側702之表面。擴散障壁及氧化物內襯704環繞TSV 114以防止TSV 114之金屬（例如，銅）擴散至基底基板104之材料（例如，矽）中。在一具體實例中，如圖7處所示，另一擴散障壁706沉積於晶粒102之後側702之表面上。在一實例中，擴散障壁706包含介電質，諸如氮化物或其類似者。
在各種具體實例中，一或多個絕緣層接著沉積於晶粒102之後側702上以防止在TSV 114之材料膨脹時對晶粒102造成損壞。例如，包含諸如氧化物之第一低溫介電質之第一層708可沉積於後側702上方，包括沉積於擴散層706上方。第一氧化物層708可包含低溫氧化物接合層。例如，圖7展示此情境，且包括TSV 114上方前側接合表面108上所形成之接觸襯墊110。
如圖8處所示，包括該一或多個絕緣層708之後側702經平坦化（例如經由CMP）以形成用於直接接合之平坦光滑的接合表面。剩餘介電層708可輔助翹曲控制，從而與晶粒102之前側平衡。藉由平坦化暴露TSV 114，包括TSV 114之顯露接觸表面302。
值得注意地，當使用一些類型之低溫氧化物（例如，矽氧烷等等）時，氧化物剛性可較低且TSV 114在平坦化期間可較易於斷裂。一旦經平坦化，氧化物就較為穩定。當使用其他類型的低溫氧化物（例如，TEOS等等）時，氧化物可較佳地支撐TSV 114，但氧化物亦可鬆弛，從而使得圍繞TSV 114之區域比接合表面高（約1至10 nm），這會引起直接接合（例如，DBI）問題。作為對此問題之解決方案，在TSV 114頂部上添加DBI接合層（例如層708），如圖7中所示。
類似於或等同於晶粒102之第二晶粒802亦在圖8處以虛線展示。圖8之說明展示前後直接接合配置（而無需黏著劑）之實例，其中第二晶粒802在第二晶粒802之前側108處接合至第一晶粒102之後側702 （介電質與介電質的接合）。如所示，在此配置中，在第一晶粒102之後側702處顯露之TSV 114之表面302接合至第二晶粒802處之導電襯墊110 （金屬與金屬的接合）。在替代具體實例中，晶粒102及802可面對面或背對背接合。
在一具體實例中，如圖9至圖10處所示，多個層可添加至後側702以在TSV 114處減小金屬膨脹應力且形成用於晶粒102之後側702接合表面。如圖9處所示，在第一低溫氧化物層708 （其在一些實施中亦包含接合層）之沉積之後，第二介電層902 （其可包含低溫氧化物）可沉積於第一層708上方。兩個氧化物層（708及902）之間無需障壁或黏著層。在各種實施中，第一層708及第二層902包含類似或相同材料（呈不同厚度）。在其他實施中，第一層708及第二層902包含不同材料。第二氧化物層902可具有與第一層708類似或不同的殘餘應力特性（例如，第一層708可具有壓縮性且第二層902可具有拉伸性，或反之亦然，或層708及902兩者均可具有具備類似或不同值之壓縮性或拉伸性）。在替代實施中，額外絕緣層亦可沉積於第一層708及第二層902上方。
如圖10處所示，該些層708及902經平坦化（例如，CMP），從而顯露TSV 114及末端表面302，其可替代接合襯墊起作用。在一實施中，第二層902之部分可保留於晶粒102上以用於翹曲控制。
在一些具體實例中，如圖11中所示，後側702處之末端表面302可形成為具有不平坦或非平坦表面拓樸結構。例如，末端表面302可經選擇、形成或處理為具有不平坦的表面拓樸結構以作為膨脹緩衝區。例如，參看圖11，TSV 114之末端表面302可形成或選擇性地經蝕刻為圓形、半球形、凸形、凹形、不規則形，或以其他方式為非平坦的以實現用於材料膨脹之額外空間1102。
可基於對TSV 114之材料在加熱時將膨脹之量之預測判定及形成額外空間1102。在各種實施中，TSV 114之末端表面302在沉積期間可形成為不平坦的，或可在形成TSV 114之後經蝕刻、研磨、拋光或以其他方式變得不平坦。在一些狀況下，TSV 114之末端表面302可在後側702接合表面之CMP期間變得不平坦。
圖12至圖13說明根據各種具體實例的當將偏移接觸襯墊110安置於前側108上時處理晶粒102之後側702之實例。如圖12及圖13中所示，偏移接觸襯墊110可使用一或多條跡線112或其類似者耦接至TSV 114。如上文所論述，一或多個氧化物應力層（諸如層708）可在使擴散障壁層706沉積於後側702上方之後沉積於後側702上。應力層708亦可包含直接接合層，在其為後側702上之最終層時。
如圖13中所示，層708經平坦化以形成接合表面且顯露具有光滑的接觸表面302之TSV 114。在替代具體實例中，多個應力層在後側702處可經沉積及平坦化以為直接接合做準備。
在其他具體實例中，替代技術可用於縮減或消除歸因於金屬特徵膨脹造成之脫層，且保持在本發明之範圍內。
在各種具體實例中，如圖14處所說明，除了電信號之外或代替電信號，一組堆疊晶粒102之TSV 114中之一或多者亦可用於傳導熱。舉例而言，在一些狀況下，將散熱片（或其他熱傳遞裝置）附接至一組堆疊晶粒102中之晶粒102以減少由晶粒102生成的熱可為不可行的或不可能的。在此類狀況下，可尋找其他技術以視需要傳遞熱。
在具體實例中，如圖14處所展示，TSV 114（包括部分或完全地延伸穿過晶粒102之TSV 114）之各種組態可用於將熱遠離晶粒102傳導（或遠離晶粒102之熱生成部分傳導）。一個晶粒102之TSV 114可結合第二晶粒102之TSV 114、接觸襯墊110、跡線112以及其類似者一起使用以完成自一個晶粒102至另一晶粒102之熱傳遞等等。第一晶粒102之TSV 114可直接接合（例如，DBI）至第二晶粒102之TSV 114、接觸襯墊110、跡線112以及其類似者，以用於高效能導熱性。
在一實施中，TSV 114、接觸襯墊110、跡線112以及其類似者中之一些為電性浮置或「虛設」結構，其可用於熱傳遞。此等結構可視需要將熱自高功率晶粒102傳導離開至另一晶粒102。虛設接觸襯墊110可耦接至最末穿孔或中間穿孔熱TSV 114以用於熱傳導。
在具體實例中，環繞TSV 114且可限熱或為熱障壁之擴散障壁層704可由具有一定導熱性之不同材料的擴散障壁（諸如金屬或合金障壁或其類似者）替換。 例示性製程
圖15說明代表性製程1500，其用於製備各種微電子構件（諸如晶粒102）同時減少或消除歸因於嵌入式結構在接合表面處之金屬膨脹而脫層之可能性，該些微電子構件用於接合，諸如用於在不具有黏著劑之情況下直接接合。舉例而言，接合表面處之直通矽穿孔（TSV）可引起脫層，尤其當耦接至接觸襯墊時，此係因為TSV及接觸襯墊之材料在經加熱退火期間膨脹。該製程指代圖1至圖14。
描述製程之次序並不意欲被解釋為限制性的，且可按任何次序組合製程中之任何數目個所描述製程區塊以實施製程或替代性製程。另外，可在不脫離本文中所描述之主題之精神及範圍的情況下自製程刪除個別區塊。此外，在不脫離本文中所描述之主題之範圍的情況下，製程可以任何合適之硬體、軟體、韌體或其組合實施。在替代實施中，其他技術可以各種組合形式包括於製程中，且保持在本發明之範圍內。
在各種實施中，晶粒、晶圓或其他基板（「基板」）使用各種技術形成以包括基底基板及一或多個介電層。在一實施中，在區塊1502處，製程1500包括提供穿過具有第一接合表面（諸如接合表面108）之第一基板之導電穿孔（諸如TSV 114），該導電穿孔至少部分地自該第一接合表面延伸穿過該第一基板。在一實施中，該第一穿孔垂直於第一接合表面至少部分地延伸穿過該第一基板。在一個實例中，該第一穿孔延伸穿過該第一基板到達該第一基板之一個或兩個表面。
在區塊1504處，該製程包括自與該第一接合表面相對之表面暴露該導電穿孔。在一實施中，該製程包括在導電穿孔之暴露端部中形成在第二接合表面下方延伸預定深度之凹部。例如，該凹部補償導電穿孔在接合製程期間之膨脹。
在一個實例中，該製程包括形成該導電穿孔之暴露端部使得該導電穿孔與該第二接合表面之間存在傾斜間隙。在各個實例中，不平坦的拓樸結構形成供穿孔金屬在加熱退火期間膨脹的空間。
在區塊1506處，該製程包括形成第二接合表面，其中導電穿孔在該第二接合表面處或相對於該第二接合表面凹進。
在一實施中，該製程包括提供第二基板及在無中間黏著劑之情況下將該第一基板之該第二接合表面直接接合至該第二基板。在一實施中，該製程包括在該第一基板之接合表面處使用直接介電質與介電質的非黏著性接合技術將該第一基板直接接合至該第二基板。
在一實施中，該第二基板進一步包含至少部分地延伸穿過該第二基板之導電穿孔。在另一實施中，該第二基板進一步包含該第二基板之導電穿孔上方之襯墊，該襯墊與該第一基板之導電穿孔接觸。在一具體實例中，該第一基板之該導電穿孔與該第二基板之該導電穿孔實質上對準。
在一替代實施中，該導電穿孔經組態以自該第一基板移除熱。
在各種具體實例中，相較於本文中所描述之製程步驟，可修改或排除一些製程步驟。
本文中所描述之技術、構件及裝置不限於圖1至圖15之說明，且可在不脫離本發明之範圍的情況下應用於包括其他電性構件之其他設計、類型、配置及構造。在一些狀況下，額外或替代構件、技術、序列或製程可用於實施本文中所描述之技術。另外，構件及/或技術可以各種組合形式配置及/或組合，同時產生類似或大致相同之結果。 結論
儘管已以特定針對於結構特徵及/或方法行動之語言描述本發明之實施，但應理解，實施不一定限於所描述特定特徵或行動。確切而言，將特定特徵及行動揭示為實施實例裝置及技術之代表性形式。
102‧‧‧晶粒/堆疊晶粒/第一晶粒 104‧‧‧基底基板/基板 106‧‧‧絕緣層/介電層 108‧‧‧接合表面 110‧‧‧導電特徵/接觸襯墊 112‧‧‧跡線 114‧‧‧直通矽穿孔/TSV 202‧‧‧局域化脫層 302‧‧‧端部/末端表面 602‧‧‧額外空間 702‧‧‧後側 704‧‧‧擴散障壁層 706‧‧‧擴散障壁層/擴散障壁 708‧‧‧層/第一層 802‧‧‧晶粒/第二晶粒 902‧‧‧層/第二層 1102‧‧‧額外空間 1500‧‧‧製程 1502‧‧‧區塊 1504‧‧‧區塊 1506‧‧‧區塊
參考隨附圖式闡述詳細描述。在該些圖中，元件符號之最左側數字識別首次出現該元件符號之圖。在不同圖中使用同一元件符號指示類似或相同物件。
對此論述，在圖式中所說明之裝置及系統展示為具有大量構件。如本文中所描述，裝置及/或系統之各種實施可包括更少構件且保持在本發明之範圍內。替代地，裝置及/或系統之其他實施可包括額外構件或所描述構件之各種組合，且保持在本發明之範圍內。
圖1A展示具有接合襯墊及TSV之實例基板的橫截面。
圖1B展示圖1A之實例基板的俯視圖。
圖2展示具有接合襯墊及TSV之兩個實例接合基板及實例所得脫層之橫截面。
圖3A展示根據一具體實例的將TSV之至少一個端部作為接合表面之實例基板之橫截面。
圖3B展示根據一具體實例之圖3A之實例基板的俯視圖。
圖4展示根據一具體實例的將TSV之至少一個端部作為接合表面之兩個實例接合基板之橫截面。
圖5展示根據一具體實例的將TSV之至少一個端部作為接合表面之兩個實例基板之橫截面。
圖6展示根據一具體實例的將TSV之至少一個端部作為接合表面之兩個實例基板之橫截面，該些接合表面具有不平坦的表面。
圖7至圖13展示根據一具體實例的將TSV之至少一個端部作為接合表面之實例基板之橫截面，從而說明基板之實例後側製程。
圖14展示根據各種具體實例之用於晶粒之熱管理的實例TSV之圖。
圖15為根據一具體實例之文本流程圖，其說明形成微電子總成以縮減或消除接合基板之脫層的實例製程。
102‧‧‧晶粒/堆疊晶粒/第一晶粒
104‧‧‧基底基板/基板
106‧‧‧絕緣層/介電層
108‧‧‧接合表面
110‧‧‧導電特徵/接觸襯墊
112‧‧‧跡線
114‧‧‧直通矽穿孔/TSV

Claims (19)

  1. 一種形成微電子總成之方法，其包含： 提供穿過具有第一接合表面之第一基板之導電穿孔，該導電穿孔自該第一接合表面延伸而至少部分地穿過該第一基板； 自與該第一接合表面相對之表面暴露該導電穿孔； 形成第二接合表面，其中該導電穿孔相對於該第二接合表面凹進。
  2. 如請求項1所述之形成微電子總成之方法，其中形成接合表面包含形成非導電部分且對該非導電表面進行拋光以使該導電穿孔之所暴露端部凹進。
  3. 如請求項2所述之形成微電子總成之方法，其中該凹部補償該導電穿孔在接合製程期間之膨脹。
  4. 如請求項1所述之形成微電子總成之方法，其進一步包含： 提供第二基板； 將該第一基板之該第二接合表面直接接合至該第二基板而無需中間黏著劑。
  5. 如請求項4所述之形成微電子總成之方法，其中該第二基板進一步包含至少部分地延伸穿過該第二基板之導電穿孔。
  6. 如請求項5所述之形成微電子總成之方法，其中該第二基板進一步包含該導電穿孔上方之襯墊，該襯墊與該第一基板之該導電穿孔接觸。
  7. 如請求項5所述之形成微電子總成之方法，其中該第一基板之該導電穿孔與該第二基板之該導電穿孔實質上對準。
  8. 如請求項1所述之形成微電子總成之方法，其進一步包含形成該導電穿孔之該暴露端部使得該導電穿孔與該第二接合表面之間存在傾斜間隙。
  9. 一種形成微電子總成之方法，其包含： 提供具有前側及後側之第一基板，該後側具有包含非導電接合層及自該非導電接合層凹進之暴露導電穿孔之接合表面； 提供具有前側及後側之第二基板，該前側包括非導電接合層及暴露襯墊； 藉由使該第一基板與該第二基板之該非導電接合層接觸而將該第二基板之該前側耦接至該第一基板之該後側；以及 經由熱處理步驟將該暴露襯墊耦接至該暴露導電穿孔。
  10. 如請求項9所述之形成微電子總成之方法，其中該襯墊在耦接之前凹進於該第二基板之該非導電接合層下方以適應該襯墊及該導電穿孔之熱膨脹。
  11. 如請求項9所述之形成微電子總成之方法，其中該第一基板之該非導電接合層包含擴散障壁及該擴散層上之絕緣體，該絕緣體激活為接合表面。
  12. 一種形成微電子總成之方法，其包含： 提供具有後側表面之第一基板，該後側表面包含非導電接合層及暴露導電穿孔； 提供具有後側表面之第二基板，該後側表面包含非導電接合層及暴露導電穿孔； 藉由使該第一基板與該第二基板之該非導電接合層接觸而將該第二基板耦接至該第一基板；以及 耦接該第一基板及該第二基板之該暴露導電穿孔。
  13. 如請求項12所述之形成微電子總成之方法，其進一步包含經由該導電穿孔將熱自該第一基板傳遞至該第二基板。
  14. 如請求項12所述之形成微電子總成之方法，其中該穿孔經組態以將電信號攜載至該第一基板或該第二基板中之電性裝置或自該電性裝置攜載該電信號。
  15. 一種微電子總成，其包含： 第一基板，其具有包含非導電接合層及導電穿孔之接合表面，該導電穿孔與該第一基板電絕緣； 第二基板，其包括非導電接合層及導電特徵，該導電特徵延伸至該第二基板中且與該第二基板電絕緣； 該第二基板直接接合至該第一基板使得該導電穿孔與該導電特徵接觸以形成信號路徑。
  16. 如請求項15所述之微電子總成，其中該導電特徵為耦接至該第二基板內之至少另一導電特徵之導電襯墊。
  17. 如請求項15所述之微電子總成，其中該導電特徵為至少部分地延伸穿過該第二基板之導電穿孔。
  18. 如請求項15所述之微電子總成，其中該導電特徵包括導電襯墊及導電穿孔，該導電襯墊自該導電穿孔偏移。
  19. 如請求項15所述之微電子總成，其進一步包含在該第一基板之該後側處之一或多個介電應力消除層。
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