WO2023010259A1 - 芯片堆叠结构及其制作方法、芯片封装结构、电子设备 - Google Patents
芯片堆叠结构及其制作方法、芯片封装结构、电子设备 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Definitions
- the above manufacturing method further includes: A third rewiring layer is formed above the first functional layer; the third rewiring layer covers the first TSV and is electrically connected to the first TSV. In the case where the third rewiring layer is electrically connected to the first functional layer, the third rewiring layer is formed to realize the electrical connection between the first functional layer and the first TSV.
- the material of the first dielectric layer is usually one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc., silicon nitride, silicon oxide, nitrogen
- the coefficient of thermal expansion of silicon oxide and silicon carbide is close to that of the silicon substrate, so the present application can also avoid the stress matching problem caused by the filling material.
- the third rewiring layer 201 may be electrically connected to the first functional layer 2002 of the first chip 200 , or may not be electrically connected to the first functional layer 2002 .
- FIG. 9 illustrates an example in which the third rewiring layer 201 is electrically connected to the first functional layer 2002 of the first chip 200 .
- the above-mentioned carrier board 100a is a carrier chip.
- a bonding layer 1001a may be formed on the substrate side of the carrier chip.
- the carrier chip and the first chip 200 are bonded back to face;
- a bonding layer 1001a is formed on one side of the functional layer of the carrier chip.
- the carrier chip and the first chip 200 are bonded face to face.
- FIG. 12 illustrates an example in which the carrier board 100 a is a carrier chip, and the carrier chip and the first chip 200 are bonded face to face.
- step S14 is an optional step, and in some examples, when the first TSV 2003 formed in step S11 penetrates through the first substrate 2001 , step S14 can be omitted. In the case that the first TSV 2003 formed in step S11 does not penetrate the first substrate 2001 , step S14 needs to be performed.
- step S14 further includes: as shown in FIG. 2001 forms a first insulating barrier layer 204 on the side away from the first functional layer 2002 , and the first insulating barrier layer 204 is used to protect the first substrate 2001 .
- step S29 reference may be made to the above step S19, which will not be repeated here.
- the materials of the electroplating pillars 2009, the seed layer 2009b and the first conductive barrier layer 2007 can be referred to above, and will not be repeated here.
- the first sub-bonding metal block 208 may be directly electrically connected to the first TSV 2003 , or may be electrically connected to the first TSV 2003 through other structures.
- the above-mentioned first sub-dielectric layer 205 includes a plurality of first hybrid bonding vias 206, and the first sub-bonding metal block 208 is connected to the first via through the first hybrid bonding vias 206.
- the TSV 2003 is electrically connected.
- the first hybrid bonding vias 206 can ensure that except some of the first sub-bonding metal blocks 208 are electrically connected to the first TSV 2003 , other first sub-bonding metal blocks 208 are not electrically connected to the circuit structure. In this way, the plurality of first sub-bonding metal blocks 208 can be evenly distributed.
- the chip stack structure 10 includes a third chip 400, as shown in FIG.
- the through hole 3004 is electrically connected to the first rewiring layer 301 ; the diameter of the second through silicon hole 3004 near the second functional layer 3002 is larger than the diameter near the second substrate 3001 .
- the third chip 400 includes a third substrate 4001 and a third functional layer 4002 disposed on the third substrate 4001 .
- the second TSV 3004 The projection on a chip 200 has an overlapping area with the first TSV 2003; or as shown in FIG. 31 , the projection of the second TSV 3004 on the first chip 200 has no overlapping area with the first TSV 2003 .
- the first chip 200 includes but not limited to the first substrate 2001 , the first functional layer 2002 and the first through-silicon vias 2003 , other structures of the first chip 200 can be referred to above, and will not be repeated here.
- the second chip 300 includes but is not limited to a second substrate 3001 and a second functional layer 3002 , other structures of the second chip 300 can be referred to above, and will not be repeated here.
- the specific structures of the first dielectric layer 310 and the first bonding metal block 320 in the chip stack structure 10 and other structures of the chip stack structure 10 can be referred to above, and will not be repeated here.
- the chip stack structure 10 includes but is not limited to the first chip 200 and the second chip 300, and may also include other chips.
- the structure of other chips and their interconnection with the upper and lower chips can refer to the above-mentioned first chip 200, the second chip.
- the second chip 300 and the third chip 400 are not detailed here.
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (31)
- 一种芯片堆叠结构,其特征在于,包括:第一芯片,所述第一芯片包括第一衬底、设置在所述第一衬底上的第一功能层以及穿透所述第一衬底和所述第一功能层的第一硅通孔;所述第一硅通孔靠近所述第一功能层位置处的直径大于靠近所述第一衬底位置处的直径;第二芯片,所述第二芯片包括第二衬底和设置在所述第二衬底上的第二功能层;设置在所述第二功能层远离所述第二衬底一侧的第一重新布线层;设置在所述第一衬底和所述第一重新布线层之间的第一电介质层以及设置在所述第一电介质层内的多个第一键合金属块;至少部分所述第一键合金属块分别与所述第一硅通孔和所述第一重新布线层电连接;其中,所述第一芯片和所述第二芯片通过所述第一电介质层和所述第一键合金属块键合在一起。
- 根据权利要求1所述的芯片堆叠结构,其特征在于,所述第一硅通孔包括电镀柱以及包裹所述电镀柱侧面的第一导电阻挡层,且所述电镀柱远离所述第二芯片的表面未设置所述第一导电阻挡层。
- 根据权利要求2所述的芯片堆叠结构,其特征在于,所述电镀柱靠近所述第二芯片的表面未设置所述第一导电阻挡层。
- 根据权利要求2或3所述的芯片堆叠结构,其特征在于,所述第一导电阻挡层的材料包括钛、氮化钛、钽或氮化坦中的一种或多种。
- 根据权利要求1-4任一项所述的芯片堆叠结构,其特征在于,所述第一键合金属块包括相互键合的第一子键合金属块和第二子键合金属块;所述第一子键合金属块靠近所述第一硅通孔,所述第二子键合金属块靠近所述第一重新布线层。
- 根据权利要求5所述的芯片堆叠结构,其特征在于,所述第一电介质层包括相互键合的第一子电介质层和第二子电介质层;所述第一子电介质层靠近所述第一衬底,所述第二子电介质层靠近所述第一重新布线层;所述第一子键合金属块设置于所述第一子电介质层内,且露出于所述第一子电介质层远离所述第一衬底的表面;所述第二子键合金属块设置于所述第二子电介质层内,且露出于所述第二子电介质层远离所述第一重新布线层的表面。
- 根据权利要求6所述的芯片堆叠结构,其特征在于,所述第一子电介质层包括多个与所述第一硅通孔一一对应的第一混合键合通孔,所述第一子键合金属块通过所述第一混合键合通孔与所述第一硅通孔电连接;和/或,所述第二子电介质层包括多个第二混合键合通孔,所述第二子键合金属块通过所述第二混合键合通孔与所述第一重新布线层电连接。
- 根据权利要求1-7任一项所述的芯片堆叠结构,其特征在于,所述芯片堆叠结构还包括设置在所述第一衬底和所述第一电介质层之间的第二重新布线层;所述第二重新布线层分别与所述第一硅通孔和所述第一键合金属块电连接。
- 根据权利要求8所述的芯片堆叠结构,其特征在于,所述第一键合金属块在所述第一芯片上的投影与所述第一硅通孔具有重叠区域;或者,所述第一键合金属块在所述第一芯片上的投影与所述第一硅通孔无重叠区域。
- 根据权利要求1-9任一项所述的芯片堆叠结构,其特征在于,所述芯片堆叠结构还包括设置在所述第一衬底和所述第一电介质层之间的第一绝缘阻挡层,所述第一绝缘阻挡层包括多个镂空区域,所述第一键合金属块通过所述第一绝缘阻挡层上的所述镂空区域与所述第一硅通孔电连接。
- 根据权利要求1-10任一项所述的芯片堆叠结构,其特征在于,所述芯片堆叠结构还包括设置在所述第一功能层远离所述第一衬底一侧的第三重新布线层;所述第三重新布线层与所述第一硅通孔电连接。
- 根据权利要求1-11任一项所述的芯片堆叠结构,其特征在于,所述第二芯片还包括穿透所述第二衬底和所述第二功能层的第二硅通孔;所述第二硅通孔与所述第一重新布线层电连接;所述第二硅通孔靠近所述第二功能层位置处的直径大于靠近所述第二衬底位置处的直径;所述芯片堆叠结构还包括:第三芯片;所述第三芯片包括第三衬底和设置在所述第三衬底上的第三功能层;设置在所述第三功能层远离所述第三衬底一侧的第四重新布线层;设置在所述第二衬底和所述第四重新布线层之间的第二电介质层以及设置在所述第二电介质层内的多个第二键合金属块;至少部分所述第二键合金属块分别与所述第二硅通孔和所述第四重新布线层电连接。
- 根据权利要求12所述的芯片堆叠结构,其特征在于,所述第二键合金属块包括相互键合的第三子键合金属块和第四子键合金属块;所述第三子键合金属块靠近所述第二硅通孔,所述第四子键合金属块靠近所述第四重新布线层。
- 根据权利要求13所述的芯片堆叠结构,其特征在于,所述第二电介质层包括层叠设置的第三子电介质层和第四子电介质层;所述第三子电介质层靠近所述第二衬底,所述第四子电介质层靠近所述第四重新布线层;所述第三子键合金属块设置于所述第三子电介质层内,且露出于所述第三子电介质层远离所述第二衬底的表面;所述第四子键合金属块设置于所述第四子电介质层内,且露出于所述第四子电介质层远离所述第四重新布线层的表面。
- 根据权利要求12-14任一项所述的芯片堆叠结构,其特征在于,所述第二硅通孔在所述第一芯片上的投影与所述第一硅通孔具有重叠区域;或者,所述第二硅通孔在所述第一芯片上的投影与所述第一硅通孔无重叠区域。
- 一种芯片堆叠结构,其特征在于,包括:第一芯片,所述第一芯片包括第一衬底、设置在所述第一衬底上的第一功能层以及穿透所述第一衬底和所述第一功能层的第一硅通孔;第二芯片,所述第二芯片包括第二衬底和设置在所述第二衬底上的第二功能层;设置在所述第二功能层远离所述第二衬底一侧的第一重新布线层;设置在所述第一衬底和所述第一重新布线层之间的第一电介质层以及设置在所述第一电介质层内的多个第一键合金属块;至少部分所述第一键合金属块分别与所述第一硅通孔和所述第一重新布线层电连接;其中,所述第一芯片和所述第二芯片通过所述第一电介质层和所述第一键合金属块键合在一起;所述第一硅通孔包括电镀柱以及包裹所述电镀柱侧面的第一导电阻挡 层;所述电镀柱远离所述第二芯片的表面未设置所述第一导电阻挡层。
- 根据权利要求16所述的芯片堆叠结构,其特征在于,所述电镀柱靠近所述第二芯片的表面未设置所述第一导电阻挡层。
- 根据权利要求16或17所述的芯片堆叠结构,其特征在于,所述第一导电阻挡层的材料包括钛、氮化钛、钽或氮化坦中的一种或多种。
- 根据权利要求16-18任一项所述的芯片堆叠结构,其特征在于,所述第一硅通孔靠近所述第一功能层位置处的直径大于或等于靠近所述第一衬底位置处的直径。
- 一种芯片封装结构,其特征在于,包括封装基板以及如权利要求1-19任一项所述的芯片堆叠结构;所述芯片堆叠结构和所述封装基板电连接。
- 一种电子设备,其特征在于,包括印刷电路板和如权利要求20所述的芯片封装结构;所述芯片封装结构与所述印刷电路板电连接。
- 一种芯片堆叠结构的制作方法,其特征在于,包括:从第一芯片的第一功能层一侧在所述第一芯片上形成第一硅通孔,其中,所述第一芯片包括第一衬底以及设置在所述第一衬底上的所述第一功能层;将载板与所述第一芯片键合;其中,所述第一功能层相对于所述第一衬底靠近所述载板;在第二芯片的第二功能层上形成第一重新布线层,其中,所述第二芯片包括第二衬底和设置在所述第二衬底上的所述第二功能层;将所述第一芯片和所述第二芯片键合,其中,在所述第一衬底和所述第一重新布线层之间形成第一电介质层以及位于所述第一电介质层内的多个第一键合金属块,至少部分所述第一键合金属块分别与所述第一硅通孔和所述第一重新布线层电连接。
- 根据权利要求22所述的制作方法,其特征在于,所述第一硅通孔未穿透所述第一衬底;所述将载板与所述第一芯片键合之后,所述将第一芯片和第二芯片键合,其中,在所述第一衬底和所述第一重新布线层之间形成第一电介质层以及位于所述第一电介质层内的多个第一键合金属块之前,所述制作方法还包括:从所述第一衬底远离所述第一功能层的一侧,对所述第一衬底进行减薄以露出所述第一硅通孔。
- 根据权利要求22或23所述的制作方法,其特征在于,在所述第一衬底和所述第一重新布线层之间形成第一电介质层以及位于所述第一电介质层内的多个第一键合金属块,包括:在所述第一衬底上形成第一子电介质层和多个第一子键合金属块;所述第一子键合金属块设置于所述第一子电介质层内,且露出于所述第一子电介质层远离所述第一衬底的表面;至少部分所述第一子键合金属块与所述第一硅通孔电连接;在所述第一重新布线层上形成第二子电介质层和多个第二子键合金属块;所述第二子键合金属块设置于所述第二子电介质层内,且露出于所述第二子电介质层远离所述第二衬底的表面;至少部分所述第二子键合金属块与所述第一重新布线层电连接;其中,所述第一电介质层包括所述第一子电介质层和所述第二子电介质层;所述第一键合金属块包括所述第一子键合金属块和所述第二子键合金属块。
- 根据权利要求24所述的制作方法,其特征在于,所述第一子电介质层包括多个与所述第一硅通孔一一对应的第一混合键合通孔,所述第一子键合金属块通过所述第一混合键合通孔与所述第一硅通孔电连接;和/或,所述第二子电介质层包括多个第二混合键合通孔,所述第二子键合金属块通过所述第二混合键合通孔与所述第一重新布线层电连接。
- 根据权利要求22-25任一项所述的制作方法,其特征在于,所述将所述载板与所述第一芯片键合之后,所述将第一芯片和第二芯片键合,其中,在所述第一衬底和所述第一重新布线层之间形成第一电介质层以及位于所述第一电介质层内的多个第一键合金属块之前,所述制作方法还包括:在所述第一衬底上形成第二重新布线层;所述第二重新布线层与所述第一硅通孔电连接。
- 根据权利要求22-26任一项所述的制作方法,其特征在于,所述将载板与所述第一芯片键合之后,所述将第一芯片和第二芯片键合,其中,在所述第一衬底和所述第一重新布线层之间形成第一电介质层以及位于所述第一电介质层内的多个第一键合金属块之前,所述制作方法还包括:在所述第一衬底远离所述第一功能层的一侧形成第一绝缘阻挡层。
- 根据权利要求22-27任一项所述的制作方法,其特征在于,所述从第一芯片的第一功能层一侧在所述第一芯片上形成第一硅通孔之后,所述将载板与所述第一芯片键合之前,所述制作方法还包括:在所述第一功能层的上方形成第三重新布线层;所述第三重新布线层覆盖所述第一硅通孔,且与所述第一硅通孔电连接。
- 根据权利要求22-28任一项所述的制作方法,其特征在于,所述在第二芯片的第二功能层上形成第一重新布线层之前,所述制作方法还包括:从所述第二芯片的所述第二功能层一侧形成第二硅通孔;所述将第一芯片和第二芯片键合,其中,在所述第一衬底和所述第一重新布线层之间形成第一电介质层以及位于所述第一电介质层内的多个第一键合金属块之后,所述制作方法还包括:在第三芯片的第三功能层上形成第四重新布线层,其中,所述第三芯片包括第三衬底和设置在所述第三衬底上的第三功能层;将所述第二芯片和所述第三芯片键合,其中,在所述第二衬底和所述第四重新布线层之间形成第二电介质层以及位于所述第二电介质层内的多个第二键合金属块,至少部分所述第二键合金属块分别与所述第二硅通孔和所述第四重新布线层电连接。
- 根据权利要求29所述的制作方法,其特征在于,在所述第二衬底和所述第四重新布线层之间形成第二电介质层以及位于所述第二电介质层内的多个第二键合金属块,包括:在所述第二衬底上形成第三子电介质层和多个第三子键合金属块;所述第三子键合金属块设置于所述第三子电介质层内,且露出于所述第三子电介质层远离所述第二衬底的表面;至少部分所述第三子键合金属块与所述第二硅通孔电连接;在所述第四重新布线层上形成第四子电介质层和多个第四子键合金属块;所述第四子键合金属块设置于所述第四子电介质层内,且露出于所述第四子电介质层远离所述第三衬底的表面;至少部分所述第四子键合金属块与所述第四重新布线层电连接;其中,所述第二电介质层包括第三子电介质层和第四子电介质层;所述第二键合金属块包括第三子键合金属块和第四子键合金属块。
- 根据权利要求29或30所述的制作方法,其特征在于,所述第二硅通孔未穿透所述第二衬底;将所述第一芯片和所述第二芯片键合,其中,在所述第一衬底和所述第一重新布线层之间形成第一电介质层以及位于所述第一电介质层内的多个第一键合金属块之后,将所述第二芯片和所述第三芯片键合,其中,在所述第二衬底和所述第四重新布线层之间形成第二电介质层以及位于所述第二电介质层内的多个第二键合金属块之前,所述制作方法还包括:从所述第二衬底远离所述第二功能层的一侧,对所述第二衬底进行减薄以露出所述第二硅通孔。
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