CN107078161A - 电子电路 - Google Patents

电子电路 Download PDF

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Publication number
CN107078161A
CN107078161A CN201580052318.7A CN201580052318A CN107078161A CN 107078161 A CN107078161 A CN 107078161A CN 201580052318 A CN201580052318 A CN 201580052318A CN 107078161 A CN107078161 A CN 107078161A
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China
Prior art keywords
fet
detection
master
source
main
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CN201580052318.7A
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English (en)
Inventor
M·艾曼·谢比卜
文杰·张
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Vishay Siliconix Inc
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Vishay Siliconix Inc
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Application filed by Vishay Siliconix Inc filed Critical Vishay Siliconix Inc
Priority to CN202211194090.3A priority Critical patent/CN115483211A/zh
Publication of CN107078161A publication Critical patent/CN107078161A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/145—Indicating the presence of current or voltage
    • G01R19/15—Indicating the presence of current
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7815—Vertical DMOS transistors, i.e. VDMOS transistors with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell

Abstract

垂直沟槽MOSFET中的垂直检测器件。根据本发明的实施例，电子电路包括：配置为切换至少1安培电流的垂直沟槽金属氧化物半导体场效应晶体管以及配置为提供MOSFET的漏极到源极电流的指示的电流检测场效应晶体管。电流检测FET的电流检测比为至少15000并且可以大于29000。

Description

电子电路
相关申请
本申请要求Shibib和Zhang于2014年8月19日提交的、申请号为62/039,335、代理人卷号为VISH-8823.pro、题为“电荷平衡分离栅沟槽技术中的高变比电流检测MOSFET(High Ratio Current Sense MOSFET structure in a Charge Balanced Split GateTrench Technology)”的美国临时专利申请的优先权，在此其全部内容通过引用并入本文。
本申请涉及Bobde等人于2012年4月20日提交的共同未决、共同拥有的申请号为13/460,567、题为“混合分离栅半导体(Hybrid Split Gate Semiconductor)”的美国专利申请，在此其全部内容通过引用并入本文。
技术领域
本技术的实施例涉及集成电路设计和制造领域。更具体地，本技术的实施例涉及用于垂直沟槽MOSFET中的垂直检测器件的系统和方法。
背景技术
在最近的电源设计和实现中测量电源中的电流是重要的考虑因素。电流检测功能可以用于故障检测和/或保护，用于电流模式控制的电压调节和用于电流控制以及其他用途。这些年来，各种系统已被用于测量电源中的电流，包括：例如，分立电阻器(discreteresistor)、使用印刷电路板迹线(trace)固有的电阻、使用集成电路引线框架(leadframe)固有的电阻、使用电感器(inductor)、使用包括线圈(coil)、变压器(transformer)和霍尔效应传感器(Hall effect sensor)的磁传感器件(magnetic sensing device)，以及使用功率金属氧化物半导体场效应晶体管(MOSFET)的漏源电阻(drain-sourceresistance)。
用于测量电源中的电流的主要系统之一使用被称为或简称为“检测-FET(sense-FET)”的专用场效应晶体管(FET)。通常，检测-FET是小的FET，其与主功率FET分离，主功率FET在本文中称为“主-FET(main-FET)”。通常，检测-FET配置为产生对应于主-FET中的电流的电压。“电流检测比”(CSR)是检测-FET的实现方式的品质因数。电流检测比是主-FET中的电流与检测-FET中的电流之比，例如，Imain/Isense。通常较高的电流检测比是期望的，使得电流检测的范围扩大到了主-FET中的电流的数十倍以上。然而，由于例如检测-FET结构和主-FET结构之间的复杂关系，增加CSR是一个挑战。
尚未发现设计和实现检测-FET的常规方法可适用于分离栅电荷平衡(Split GateCharge Balanced，SGCB)沟槽MOSFET。分离栅器件包括在沟槽中的具有不同电压的多层多晶硅，并且分离栅器件具有特殊的结构和布局以建立适当的电荷平衡。例如，沟槽间隔开一定距离以建立电荷平衡，而且，器件中的任何有源体结(active body junction)都必须由建立电荷平衡的多晶硅屏蔽(polysilicon shield)适当地包围。
发明内容
因此，需要用于垂直沟槽金属氧化物半导体场效应晶体管(MOSFET)中的垂直检测器件的系统和方法。还需要用于与主-FET成一体的垂直沟槽MOSFET中的垂直检测器件的系统和方法。进一步需要的是用于垂直沟槽MOSFET中的电流检测MOSFET的系统和方法，包括在检测-FET和主-FET之间的隔离区域，所述隔离区域保持主-FET中的电荷平衡。还需要检测二极管以检测主-FET的温度和/或栅极电压。还需要用于垂直沟槽MOSFET中的垂直检测器件的系统和方法，其与现有的集成电路设计、制造和测试的系统和方法兼容和互补。本技术的实施例提供这些优点。
根据本技术的实施例，电子电路包括配置为控制至少1安培的电流的垂直沟槽金属氧化物半导体场效应晶体管和配置为提供MOSFET的漏极到源极电流的指示(indication)的电流检测场效应晶体管。在一些实施例中，电流检测FET的电流检测比至少为15000并且可以大于29000。
根据本技术的另一实施例，功率半导体器件包括主垂直沟槽金属氧化物半导体场效应晶体管(主-MOSFET)。主-MOSFET包括多个平行的主沟槽，其中所述主沟槽包括耦合到主-MOSFET的栅极的第一电极和在主沟槽之间的多个主台面，其中所述主台面包括主-MOSFET的主源极和主体。功率半导体器件还包括电流检测场效应晶体管(检测-FET)。检测-FET包括多个检测-FET沟槽，其中每个所述检测-FET沟槽包括所述主沟槽之一的部分和源极-FET沟槽之间的多个源极-FET台面，其中所述源极-FET台面包括与所述主-MOSFET的主源极电隔离的检测-FET源极。
根据本技术的另一实施例，半导体器件包括：主-FET，包括主-FET源区和电流检测FET(检测-FET)，该电流检测FET(检测-FET)配置为产生对应于主-FET的漏源电流的电压。检测-FET的栅极和漏极与主-FET的栅极和漏极耦合。检测-FET包括在第一水平维度上形成的多个第一沟槽，所述第一沟槽配置为将检测-FET源区与主-FET源区隔离。每个所述沟槽包括在垂直维度上的导体和电介质的多个交替层。半导体器件还包括位于检测-FET源区和主FET源区之间的在垂直水平维度上的至少一个第二沟槽，并且配置为将检测-FET源区与主-FET源区隔离，以及将检测-FET源区和主-FET源区分隔的缓冲区。
根据本技术的另一实施例，功率半导体器件包括：配置为控制漏源电流的垂直沟槽主MOSFET(主-FET)，配置为产生对应于漏源电流的电压的垂直沟槽电流检测FET(检测-FET)，以及配置为将主-FET与检测-FET隔离的隔离沟槽。隔离沟槽与主-FET的多个沟槽成角度形成并与其交叉。
根据本技术的另一实施例，功率半导体器件包括衬底和形成在衬底中的分离栅垂直沟槽主MOSFET(主-FET)，其配置为控制漏源电流。主-FET包括设置在衬底表面上的主-FET源极金属，所述主-FET源极金属配置为将多个主-FET源区彼此耦合并且耦合到多个主-FET源极端子。功率半导体器件还包括形成在衬底中的垂直沟槽电流检测FET(检测-FET)，所述垂直沟槽电流检测FET配置为产生对应于漏源电流的电压。检测-FET至少在三侧上被主-FET源极金属包围。衬底可以包括外延生长材料。
根据本技术的另一实施例，功率半导体器件包括衬底和形成在衬底中的分离栅垂直沟槽主MOSFET(主-FET)，该分离栅垂直沟槽主MOSFET配置为控制漏源电流。功率半导体器件还包括形成在衬底中的垂直沟槽电流检测FET(检测-FET)，该垂直沟槽电流检测FET配置为产生对应于漏源电流的电压。检测-FET和主-FET包括公共的栅极端子和漏极端子。检测-FET可以包括形成主-FET的沟槽的部分。衬底可以包括外延生长材料。
附图简要说明
并入本说明书中并且构成本说明书的一部分的附图示出了本技术的实施例，并且与描述一起用于解释本技术的原理。除非另有说明，否则附图未按比例绘制。
图1A示出了根据本技术的实施例的、功率半导体器件中的示例性电流检测MOSFET的俯视图。
图1B示出了根据本技术的实施例的、用于功率半导体器件的示例性原理符号图(schematic symbol)。
图2示出了根据本技术的实施例的、功率半导体器件的部分的示例性放大俯视图。
图3示出了根据本技术的实施例的、功率半导体器件的部分的示例性横截面图。
图4示出了根据本技术的实施例的、功率半导体器件的部分的示例性横截面图。
图5示出了在根据本技术的实施例构建的原型器件(prototype device)上进行的实验测量的曲线图。
图6示出了根据本技术的实施例的、用于在垂直沟槽MOSFET中构建电流检测MOSFET的示例性工艺流程图。
图7A示出了根据本技术的实施例的、功率半导体器件中的示例性检测二极管的俯视图。
图7B示出了根据本技术的实施例的、用于功率半导体器件的示例性原理符号图。
图8示出了根据本技术的实施例的、功率半导体器件的部分的示例性横截面图。
图9示出了根据本技术的实施例的、作为栅极电压的函数的示例性检测二极管的示例性特性(characteristic)。
图10A示出了根据本技术的实施例的、功率半导体器件中的示例性电流检测MOSFET(检测-FET)和示例性检测二极管的俯视图。
图10B示出了根据本技术的实施例的用于功率半导体器件的示例性原理符号图。
具体实施方式
现在将详细地参考本技术的各个实施例，其示例在附图中示出。虽然本技术将结合这些实施例来描述，但是应当理解，它们不旨在将技术限制为这些实施例。相反，本技术旨在覆盖可以包括在由所附权利要求限定的技术的精神和范围内的替代、修改和等同物。此外，在本技术的以下详细描述中，阐述了许多具体细节，以便提供本技术的彻底理解。然而，本领域普通技术人员应该认识到，可以在没有这些具体细节的情况下实践本技术。在其他情况下，没有详细描述公知的方法、过程、部件和电路，以免不必要地混淆本技术的各个方面。
符号和术语
附图没有按比例绘制，并且在附图中可以仅示出部分结构以及形成那些结构的各个层。此外，制造工艺和操作可以与本文讨论的工艺和操作一起执行；也就是说，在本文示出和描述的操作之前、之间和/或之后可能有多个工艺操作。重要的是，根据本技术的实施例可以结合这些其他(可能是常规的)过程和操作来实现，而不会明显地扰乱它们。一般来说，根据本技术的实施例可以替换和/或补充常规工艺的部分，而不显著影响外围工艺和操作。
术语“MOSFET”通常理解为与术语绝缘栅场效应晶体管(IGFET)同义，因为许多最近的MOSFET包括非金属栅极和/或非氧化物栅极绝缘体(non-oxide gate insulator)。如本文所使用的，术语“MOSFET”不一定暗指或要求包括金属栅极和/或氧化物栅极绝缘体的FET。相反，术语“MOSFET”包括通常称为或简称为MOSFET的器件。
如本文所使用的，字母“n”是指n型掺杂剂以及字母“p”是指p型掺杂剂。加号“+”或减号“-”分别用于表示相对高或相对低浓度的这种掺杂剂。
术语“沟道(channel)”在本文中以接受的方式使用。也就是说，电流在FET内的沟道中从源极连接(source connection)移动到漏极连接(drain connection)。沟道可以由n型或p型半导体材料制成；因此，FET被指定为n沟道或p沟道器件。在n沟道器件，更具体地n沟道垂直MOSFET的上下文中讨论了一些附图，。然而，根据本技术的实施例不限于此。也就是说，本文所述的特征可以用于p沟道器件中。通过用p型掺杂剂和材料代替相应的n型掺杂剂和材料，n沟道器件的讨论可以容易地映射到p沟道器件，反之亦然。
术语“沟槽”在半导体领域内已经获得了两种不同的但是相关的含义。通常，当提及工艺(例如蚀刻)时，术语沟槽用于表示或指代材料的空隙(void)，例如孔(hole)或沟(ditch)。通常，这种孔的长度远大于其宽度或深度。然而，当提及半导体结构或器件时，术语沟槽用于表示或指代布置在衬底的主表面下方的固体垂直排列结构(solidvertically-alignedstructure)，其具有与衬底的成分不同的复杂成分，以及通常与场效应晶体管(FET)的沟道相邻。该结构包括例如FET的栅极。因此，沟槽半导体器件通常包括不是沟槽的台面(mesa)结构，以及两个相邻结构“沟槽”的部分，例如一半。
应当理解，尽管通常被称为“沟槽”的半导体结构可以通过蚀刻沟槽然后填充沟槽来形成，但是本文关于本技术的实施例的结构术语的使用并不暗指并且不限于这样的处理。
垂直沟槽MOSFET中的垂直检测器件
电荷平衡分离栅垂直沟槽金属氧化物半导体场效应晶体管(MOSFET)通常包括沟槽，所述沟槽延伸到在重掺杂衬底的顶部上生长的一个或更多外延层中。沟槽被蚀刻足够深，通常几微米，以能够容纳几层氧化物和多晶硅。最靠近沟槽底部的下层的多晶硅(“多晶硅1(poly 1)”)通常与源极电势相关，并且是建立电荷平衡条件的重要部分，对于给定的击穿电压其导致期望的低“导通(on)”电阻。上层的多晶硅(“多晶硅2(poly 2)”)通常用作器件的栅极。两个层都在沟槽内，并且通过不同厚度的电介质层(例如，二氧化硅)与外延区隔离。
根据本技术的实施例，在称为“主-FET”的相对较大的分离栅MOSFET的顶部体附近建立相对小的检测-FET。检测-FET应该能够在检测-FET中传送电流，该电流是通过主-FET的电流的一小部分。例如，检测-FET应该被表征为具有大的电流检测比(CSR)。
一般来说，电流检测比(CSR)可以是器件几何形状和温度两者的特性。例如，检测-FET和主-FET的部分之间的温度差可能在操作期间有害地改变CSR。
根据本技术的实施例，检测-FET可以位于主-FET的区域中，其中检测-FET可以检测管芯(die)的高温。检测-FET可以在至少三侧面由主-FET的部分所包围。根据本技术的实施例，例如共享公共检测-FET源极的多个检测-FET可以位于整个主-FET的多个位置。例如，这样的多个位置可以改善对应于跨大管芯的热分布的电流检测。
图1A示出了根据本技术的实施例的、功率半导体器件100中的示例性电流检测MOSFET(检测-FET)160的俯视图。功率半导体器件100的主要功能是用作功率MOSFET，例如用于控制通过功率MOSFET的漏源电流(drain source current)。功率半导体器件100包括大面积的主-FET 150。例如，主-FET 150包括多个沟槽，所述沟槽包括栅极和屏蔽电极(shield electrode)，以及位于包括源极和体区(body region)的沟槽之间的台面。主-FET150包括耦合到栅极端子140(例如，接合焊盘)的栅极。主-FET 150包括耦合到主-FET源极端子130的源极。主-FET150的漏极在图1A的平面之外，例如在其下方。
根据本技术的实施例，功率半导体器件100包括形成在主-FET 150的区域内的检测-FET 160。应当理解，主-FET150的管芯面积远远大于检测-FET160的管芯面积。检测-FET160的栅极和漏极与主-FET 150的栅极和漏极共用(in common)，例如平行(in parallel)。检测-FET 160的源极耦合到检测源极端子(sense source terminal)110，例如接合焊盘。检测-FET输出对应于主-FET 150中的电流的电压。在一些实施例中，节点开尔文(nodeKelvin)可耦合到端子120，以使用功率半导体器件100的管芯。电压开尔文(voltageKelvin)也可以或者可选地由功率半导体器件100的管芯上的电路(未示出)使用，例如，为了过流保护(over-current protection)而关断主-FET 150。
图1B示出了根据本技术的实施例的、功率半导体器件100的示例性原理符号图。
图2示出了根据本技术的实施例的、围绕并包括检测-FET 160的功率半导体器件100的部分的示例性放大俯视图。功率半导体器件100包括多个主沟槽210，在图2中水平示出。大多数主沟槽210被主-FET 150使用。
根据本技术的实施例，功率半导体器件100包括四个隔离沟槽221、222、223和224。隔离沟槽221-224是用于将检测-FET 160与主-FET 150隔离的一组隔离结构的一部分。根据本技术的实施例，隔离沟槽221-224垂直于主沟槽210。检测-FET160包括检测-FET源极230。检测-FET源极230由两个隔离沟槽(隔离沟槽222和223)，以及两个主沟槽210(主沟槽210A和210B)的部分界定。检测-FET源极金属240覆盖并耦合检测-FET源极230。检测-FET源极金属240与隔离沟槽222和224重叠。在一些实施例中，例如，检测-FET源极金属240可以延伸离开图2的顶部，以耦合到检测源极端子110(图1A)。根据本技术的其它实施例，主-FET150的源极可以以不同的方式耦合，例如，离开图2的平面。在这种情况下，根据本技术的实施例，表面隔离区250将形成围绕检测-FET 160(图1)的方形环。
根据本技术的实施例，表面隔离区250形成在检测-FET 160的外部。在图2的示例性实施例中，表面隔离区250通常为“U”形。表面隔离区250形成在隔离沟槽221和222之间、隔离沟槽223和224之间以及主沟槽210B和210C之间。一般来说，为了保持电荷平衡，多个主沟槽220的部分应当用于将检测-FET 160与主-FET 150隔离。表面隔离区250的台面中的P型材料保持浮置(floating)。表面隔离区250的表面可以用绝缘体覆盖，例如硼磷硅酸盐玻璃(BPSG)。
在表面隔离区250之外，例如在图2的视图中的表面隔离区250的左、右和下方，是主-FET150的区域。例如，在主沟槽210之间的台面中的p型材料耦合到主-FET源极端子130(图1)，并且这些区域覆盖有主-FET源极金属(未示出)。
图3示出了根据本技术的实施例的、功率半导体器件100的部分的示例性横截面图。图3对应于图2的截面AA。图3的视图沿着台面，例如在主沟槽210(图2)之间，切割检测-FET 160(图1A)的有源区(active region)。功率半导体器件100包括形成在N+衬底(未示出)上的外延层310，例如N-。金属漏极接触(未示出)通常形成在衬底的底部上。隔离沟槽221、222、223和224形成在外延层310中。如图所示，隔离沟槽221、222、223和224垂直于主沟槽210。然而，隔离沟槽221-224和主沟槽210之间的各种角度(例如，从大约40度至90度)非常适合于根据本技术的实施例。
主沟槽210在图3的平面之上和之下。隔离沟槽221-224应该比漏极-体PN结更深，并且可以与主沟槽210具有大约相同的深度。这样的深度在检测-FET 160的源极和主-FET150的源极之间建立物理屏障(physical barrier)。因此，根据本技术的实施例，体注入可以在没有掩膜的情况下执行，因此使得制造工艺更具成本效益。
在每个沟槽221-224内，存在由氧化物(例如二氧化硅)隔开的两个多晶硅电极，多晶硅1(350)和多晶硅2(340)。顶部电极多晶硅2(340)耦合到栅极端子，并且底部电极多晶硅1(35)耦合到源极端子。功率半导体器件100另外包括体注入330，例如P+掺杂，通常在外延层310的表面下方的某深度处。隔离沟槽221和222之间以及隔离沟槽223和224之间的注入区360保持浮置，以在检测-FET的体区370和电隔离的主-FET的体区380之间形成缓冲区，从而采用分离两个体区370和380的最小距离改善两个FET的电隔离。
隔离沟槽221和222之间以及隔离沟槽223和224之间的区域是表面隔离区250(图2)的一部分。表面隔离区250覆盖有绝缘体，例如，硼磷硅酸盐玻璃(BPSG)320。在BPSG 320下方通常有低温氧化物(LTO)层312。BPSG 320将检测-FET源极金属240和主-FET源极金属彼此隔离以及与浮置体注入(floating body implant)360隔离。
检测-FET源极金属240将检测FET 160(未示出)的源极和检测-FET体370耦合到功率半导体器件100的检测-FET源极端子，例如检测-FET源极端子110(图1A)。
图4示出了根据本技术的实施例的、功率半导体器件100的部分的示例性横截面图。图4对应于图2的截面BB。图4的视图是穿过检测-FET 160(图1A)的有源区并垂直于主沟槽210观察的。若干主沟槽210的部分，例如，表面隔离区250和BPSG 320下方的部分，用作隔离沟槽440。顶部电极多晶硅2(340)耦合到栅电极，底部电极多晶硅1(350)耦合到主-FET的源极。不同主沟槽210的部分用作沟槽430以形成检测-FET 160。应当理解，为了清楚起见，图4仅示出了作为检测-FET 160的一部分的两个沟槽。在检测-FET160中通常有更多的沟槽430。
检测-FET 160包括检测-FET源极410，其通常是在外延层310的顶部处或附近的N+注入。检测-FET 160还包括检测-FET源极-体接触420。图4中还示出了检测-FET源极金属延伸部450，例如用于将检测-FET源极金属延伸部路由到检测-FET源极接触，例如图1A的检测-FET源极端子110。
图5示出了在根据本技术的实施例构建的原型器件(prototype device)上进行的实验测量的曲线图500。曲线图500示出了电流检测比(CSR)，例如，在左侧横坐标(leftabscissa)上的Imain/Isense之比，跨越主-FET的漏源电流Ids(也称为Imain)，其从2安培(amps)到50安培(纵坐标)。该比至少为2.99×104，例如在2安培时，并且可以高至3.1×104，例如在50安培时。相比之下，在此时申请人已知的常规技术下的最高声称的CSR约为1.2×103。
图5的曲线图500还示出了在右侧横坐标上的整个主电流范围上的百分比失配(mismatch)。该失配描述了Imain/Isense之比的精确度。该失配非常小，例如在从2安培到50安培的Ids范围内的+/-0.33％范围内。因此，原型(prototype)非常精确地表示主-FET的Ids。
根据本技术的实施例，与自身产生相应的垂直沟槽MOSFET所需的工艺步骤和掩膜层相比，可以在垂直沟槽MOSFET中形成电流检测MOSFET，而不需要额外的工艺步骤或额外的掩膜层。例如，可以利用形成图2的主沟槽210的相同工艺步骤和掩膜形成垂直隔离沟槽，例如图2的隔离沟槽221-224。应当理解，根据本技术和现有技术的实施例之间的若干掩膜将是不同的，该若干掩膜包括例如沟槽掩膜和金属化掩膜(metallization mask)。例如，根据本技术的实施例，用于形成FET沟槽(例如，主沟槽210(图2)和垂直隔离沟槽，例如隔离沟槽221-224(图2))的单一掩膜(single mask)是新颖且独特的。然而，掩膜的工艺和数量可以相同。
图6示出了根据本技术的实施例的、用于在垂直沟槽MOSFET(例如，图1A的功率半导体器件100)中构建电流检测MOSFET的示例性工艺流程图600。在605中，用硬掩膜将多个沟槽蚀刻到例如通常几微米的深度。沟槽包括例如主沟槽例如主沟槽210(图2)，以及与主沟槽以一定角度形成的隔离沟槽例如隔离沟槽221-224。主沟槽和隔离沟槽可以被蚀刻到大约相同的深度，但这不是必须的。
在另一实施例中，使垂直沟槽略宽于主沟槽210，如此当蚀刻(在相同的工艺步骤)两个沟槽时，垂直沟槽比主沟槽稍深。
在610中，在沟槽内部生长热氧化物，然后沉积氧化物。在615中，将第一多晶硅(例如图3的多晶硅1(350))沉积在沟槽内部。第一多晶硅可以掺杂有高浓度的磷。在620中，使第一多晶硅凹陷回(recess back)到所需深度，通常大约1微米。在625中，在第一多晶硅之上和上方生长或沉积第二氧化物层。在630中，执行选择性氧化物蚀刻，以蚀刻生长栅极氧化物的有源区。
在635中，沉积第二多晶硅，例如图3的多晶硅2(340)。在640中，使第二多晶硅凹陷在有源区中，以允许沉积的氧化物层通过填充和回蚀刻工艺填充沟槽的顶部。体(body)和源极注入应相继地(consecutively)引入。在645中，在接触被蚀刻至硅(第一多晶硅和第二多晶硅)之前，氮化硅层和掺杂的氧化物层用于覆盖表面。
在650中，沉积并蚀刻金属层以形成栅极接触和源极接触。应当理解，根据本技术的实施例的源极金属图案不同于常规垂直MOSFET，例如，以适应新的检测-FET的分离的检测源极(sense source)。此外，在检测-FET周围的隔离区中没有源极金属。
在655中，在金属化(metallization)上沉积氧化物和氮化物的钝化层并蚀刻。在660中，沉积形成背面漏极接触的金属层。
根据本技术的实施例，可以在靠近称为“主-FET”的相对较大的分离栅MOSFET的顶部体处建立检测二极管(sense diode)。在一些实施例中，这样的检测二极管可以用于指示主-FET的温度。主-FET的温度可以用于许多用途，例如，响应于超温(over-temperature)条件而关闭器件。在一些实施例中，检测二极管也可以用于测量主-FET的栅极电压。当主-FET的栅极端子未暴露时，例如在封装过的高性能器件(high function device)中，诸如驱动器MOS(“DrMOS”)器件，可能需要测量主-FET的栅极电压。
图7A示出了根据本技术的实施例的、功率半导体器件700中的示例性检测二极管720的俯视图。功率半导体器件700的主要功能是用作功率MOSFET，例如，以控制通过功率MOSFET的漏源电流。功率半导体器件700包括大面积的主-FET 750。例如，主-FET150包括多个沟槽，该沟槽包括栅极和屏蔽电极，以及位于包括源极和体区的沟槽之间的台面。主-FET750包括栅极，该栅极耦合到栅极端子740，例如接合焊盘。主-FET 750包括耦合到主-FET源极端子730的源极。MOSFET 750的漏极在图7A的平面之外，例如在其下方。主-FET750、主源极730和栅极740的功能和结构大体上等同于如图1A所示的器件100的类似的结构。
根据本技术的实施例，功率半导体器件100包括形成在主-FET 750的区域内的检测二极管720。应当理解，主-FET 750的管芯面积远远大于检测二极管720的管芯面积。检测二极管720的阴极端子与图7A的平面之外的主-FET 750的漏极端子共用。检测二极管720的阳极端子耦合到阳极端子710，例如接合焊盘。
图7B示出了根据本技术的实施例的、用于功率半导体器件700的示例性原理符号图。
应当理解，检测二极管720在结构上非常类似于图1A、图2、图3和图4的检测-FET160。隔离检测二极管720的隔离沟槽等同于隔离检测-FET160的隔离沟槽。检测-FET 160和检测二极管720之间的主要差异是检测二极管720可以没有源极注入410和源极-体接触420(图4)，并且沟槽内的两个多晶硅层的连接不同。
图8示出了根据本技术的实施例的、功率半导体器件700的部分的示例性横截面图。图8大体上等同于图4的横截面图。通过检测二极管720(图7A)的有源区、垂直于主-FET750的主沟槽观察而获得图8的视图。若干主沟槽的部分，例如，表面隔离区和BPSG 825以下的部分，用作隔离沟槽840。顶部电极多晶硅2(842)耦合到栅电极，以及底部电极多晶硅1(841)耦合到主-FET的源极。不同主沟槽的部分用作沟槽830以形成检测二极管820。应当理解，为了清楚起见，图8仅示出了作为检测二极管720的一部分的两个沟槽。在检测二极管720内通常可以有更多的沟槽830。
检测二极管720包括检测二极管阳极870。可选地，检测二极管720可以包括检测二极管阳极接触851，类似于MOSFET的源极-体接触，例如图4的检测-FET源极-体接触420。图8中还示出了检测-FET源极金属延伸部850，例如用于将检测-FET源极金属延伸部路由到检测-FET源极接触，例如，图7A的检测-FET阳极接触710。
根据本技术的实施例，检测二极管720可以用于检测器件的温度，例如，主-FET750的温度，和/或用于指示栅极740的电压。
根据本技术的实施例，为了测量温度，第一场板多晶硅1(841)应当电耦合到检测二极管720的阳极，检测二极管720具有不同于主-FET750(或检测-FET，如果存在)的源极的单独的端子。第二场板多晶硅2(842)使用栅极结构，并且应该电耦合到阳极(不是耦合到主-FET 750的栅极端子740)。二极管的阴极侧与主-FET 750(和检测-FET，如果存在)的漏极共用。在该实施例中，二极管不受主-FET 750栅极电压的影响，并且表现出良好的二极管特性，其可以作为用于温度检测的温度的函数被校准。因此，垂直沟槽MOSFET内的垂直MOS二极管的这种新颖的结构可以用于经由公知的方法来检测器件的温度。
根据本技术的实施例，为了指示栅极电压，第二场板多晶硅2(842)应电耦合到主-FET 750的栅极端子。在该实施例中，检测二极管720的特性作为栅极电压的函数而变化。例如，如果第二场板多晶硅2(842)电耦合到栅极端子，则检测二极管720的电流电压关系取决于栅极端子电压。在该实施例中，检测二极管720的电流-电压特性可以用于通过将给定电流下的检测二极管720电压校准为栅极电压来指示给定温度下的栅极电压。如果没有栅极端子暴露于外部，例如，如在驱动器-MOS(“DrMOS”)封装的情况下，这可能是有用的。下面的图9示出了作为栅极电压的函数的、检测二极管720的示例性特性，以便于确定栅极电压。
图9示出根据本技术的实施例的、作为栅极电压的函数的示例性检测二极管720的示例性特性900。特性900可以用于基于二极管电流和阳极电压来确定栅极电压。在这里可以看到的检测二极管720的电流-电压特性的调制取决于施加到第二场板多晶硅2(842)(如图8所示的)的栅极电压。当Vgs＝0伏特时，沟道关闭，并且检测二极管720以“纯二极管模式”工作。随着Vgs增加，检测二极管720由寄生MOSFET调制。例如，当Vgs＝5伏特时，沟道导通，并且沟道电流支配(dominate)特性。在这种操作模式中检测二极管720可以基本上通过将流过二极管的电流(例如，在1μa的漏源电流下)校准到下面的表1来“检测栅极电压”，表1如下：
V diode@1μa＝0.62V＝>Vgs＝0V
Vdiode@lμa＝0.51V＝>Vgs＝2.5V
Vdiode@lμa＝0.39V＝>Vgs＝5V
Vdiode@1μa＝0.24V＝>Vgs＝10V
表1
应当理解，根据本技术的实施例很好地适合于检测-FET(例如，图1A的检测-FET160)和检测二极管(例如，图7A的检测二极管720)的形成和使用。
图10A示出了根据本技术的实施例的、功率半导体器件1000中的示例性电流检测MOSFET(检测-FET)160和示例性检测二极管720的俯视图。功率半导体器件1000的主要功能是用作功率MOSFET，例如以控制通过功率MOSFET的漏源电流。功率半导体器件1000包括大面积的主-FET1050。例如，主-FET 1050包括多个沟槽，该沟槽包括栅极和屏蔽电极，以及在包括源极和体区的沟槽之间的台面。主-FET 1050包括耦合到栅极端子140(例如，接合焊盘)的栅极。主-FET1050包括耦合到主-FET源极端子130的源极。MOSFET 1050的漏极在图1A的平面之外，例如在其下方。
根据本技术的实施例，功率半导体器件1000包括形成在主-FET 1050的区域内的检测-FET 160。应当理解，主-FET 1050的管芯面积比检测-FET160的管芯面积大得多。检测-FET 160的栅极和漏极与主-FET 1050的栅极和漏极共用(in common)，例如平行(inparallel)。检测-FET 160的源极耦合到检测源极端子110，例如接合焊盘。检测-FET输出与主-FET 1050中的电流相对应的电压。在一些实施例中，节点开尔文(node Kelvin)可以耦合到端子120，以使用功率半导体器件100的管芯。电压开尔文(voltage Kelvin)也可或可替代地由功率半导体器件1000的管芯上的电路(未示出)使用，例如，以为了过流保护而关断主-FET 1050。
根据本技术的实施例，功率半导体器件1000还包括在主-FET1050区域内形成的检测二极管720。应当理解，主-FET 1050的管芯面积远远大于检测二极管720的管芯面积。检测二极管720的阴极与主-FET 1050的漏极共用。检测二极管720的阳极耦合到阳极端子，例如接合焊盘710。如前所述，检测二极管720可以用于测量器件的温度和/或栅极电压。可以预见包括至少两个检测二极管的功率MOSFET器件，并且其被认为在本技术的范围内。例如，多个检测二极管可以配置为测量MOSFET的不同区域中的温度。在另一实施例中，至少一个检测二极管可以配置为结合配置为测量温度的一个或多个检测二极管来指示栅极电压。
类似地，可以预见包括至少两个检测-FET的功率MOSFET器件，并且其被认为在本技术的范围内。例如，由于功率MOSFET的大管芯上的温度和制造工艺变化，MOSFET内的电流可能分布不均匀。因此，可能有利的是经由多个检测-FET在整个这种器件中的不同位置处测量电流。作为由本技术的实施例提供的新的高电流检测比的有益结果，可以以这种方式观察到电流的小变化。
图10B示出了根据本技术的实施例的、用于功率半导体器件1000的示例性原理符号图。
应当理解，不需要额外的掩膜或制造工艺步骤来形成检测-FET 160和/或检测二极管720。检测-FET 160和检测二极管720两者都利用与主-FET共同的结构(例如沟槽和多晶硅层)用于其功能，并且进一步利用与主-FET共同的结构(例如沟槽和BPSG)用于隔离。因此，与沟槽MOSFET相比，可以在没有额外制造成本的情况下实现检测-FET 160和/或检测二极管720的有益效果。
根据本技术的实施例非常适合于各种沟槽MOSFET，包括例如单栅沟槽MOSFET(single gate trench MOSFET)，分离栅电荷平衡沟槽MOSFET(split gate chargebalanced trench MOSFET)，混合分离栅MOSFET(Hybrid Split Gate MOSFET)，例如，如在Bobde等人于2012年4月20日提交的题为“混合分离栅半导体(Hybrid Split GateSemiconductor)”的共同未决、共同拥有的申请号为13/460,567的美国申请专利中所公开的，在此其全部内容通过引用并入本文，以及双沟槽MOSFET，例如，如K.P.Gan，Y.C.Liang，G.Samudra，S.M.Xu，L.Yong于2001年在IEEE电力电子学专家会议(IEEE PowerElectronics Specialist Conference)上发表的出版物“Poly Flanked VDMOS(PFVDMOS)：用于超结器件的优秀技术(A Superior Technology for Superjunction Devices)”中所述。
根据本技术的实施例提供用于垂直沟槽MOSFET中的电流检测金属氧化物半导体场效应晶体管(MOSFET)的系统和方法。另外，根据本技术的实施例提供用于与主-FET一体的垂直沟槽MOSFET中的电流检测MOSFET的系统和方法。此外，根据本技术的实施例提供用于与主FET一体的垂直沟槽MOSFET中的电流检测MOSFET的系统和方法。根据本技术的另外的实施例提供用于检测二极管检测主-FET的温度和/或栅极电压的系统和方法。此外，根据本技术的实施例提供用于垂直沟槽MOSFET中的电流检测MOSFET和/或检测二极管的系统和方法的系统和方法，其与现有的集成电路设计、制造和测试的系统和方法兼容和互补。
因此描述了本发明的多个实施例。尽管已经在特定实施例中描述了本发明，但是应当理解，本发明不应被解释为受这些实施例的限制，而是根据下面的权利要求来解释。
优选地包括本文所描述的所有元件、部件和步骤。应当理解，对于本领域技术人员显而易见的是，这些元件、部件和步骤中的任何一个可以被其它元件、部件和步骤替代或者一起删除。
概念
本文公开了至少以下概念：
概念1.一种电子电路，包括：
垂直沟槽金属氧化物半导体场效应晶体管(MOSFET)，配置为控制至少1安培的电流；以及
电流检测FET，配置为提供电信号作为所述MOSFET的漏极到源极电流的指示，
其中，所述电流检测FET的电流检测比大于15000。
概念2.根据概念1所述的电子电路，其中，所述电流检测FET的所述电流检测比大于20000。
概念3.根据概念1或2所述的电子电路，其中，所述电流检测FET的所述电流检测比大于29000。
概念4.根据概念1至3所述的电子电路，其中，所述检测-FET设置在所述MOSFET内。
概念5.根据概念1至4所述的电子电路，其中，所述检测-FET与所述MOSFET物理地共享沟槽。
概念6.根据概念1至5所述的电子电路，其中，所述MOSFET包括沟槽，并且其中所述沟槽包括彼此电隔离的至少两个电极。
概念7.根据概念1至6所述的电子电路，其中，所述MOSFET的栅极和漏极电耦合到所述电流检测FET的栅极和漏极。
概念8.一种功率半导体器件，包括：
主垂直沟槽金属氧化物半导体场效应晶体管(主-MOSFET)，包括：
多个平行的主沟槽，其中所述主沟槽包括耦合到所述主-MOSFET的栅极的第一电极；以及
在所述主沟槽之间的多个主台面，其中所述主台面包括所述主MOSFET的主源极和主体；以及电流检测场效应晶体管(检测-FET)，包括：
多个检测-FET沟槽，其中所述检测-FET沟槽的每一个包括所述主沟槽之一的部分；以及
在所述源极-FET沟槽之间的多个源极-FET台面和体台面，其中所述源极-FET台面包括检测-FET源极，所述检测-FET源极与所述主-MOSFET的所述主源极电隔离。
概念9.根据概念8所述的功率半导体器件，其中，每个所述多个平行主沟槽还包括耦合到所述主-MOSFET的所述主源极的主栅极电极。
概念10.根据概念9所述的功率半导体器件，其中，所述源极-FET沟槽包括耦合到所述主-MOSFET的所述栅极的第一电极和与所述主栅极电极电隔离的第二电极。
概念11.根据概念8至10所述的功率半导体器件，其中，所述主MOSFET的各部分在至少三侧上围绕所述电流检测FET。
概念12.根据概念11所述的功率半导体器件，还包括没有表面金属化的表面隔离区，其在所述至少三侧上位于所述电流检测-FET和所述主-MOSFET之间。
概念13.根据概念12所述的功率半导体器件，其中所述表面隔离区的各部分形成在与所述平行主沟槽交叉的隔离沟槽之间。
概念14.根据概念8-13所述的功率半导体器件，还包括：
与所述平行主沟槽交叉的至少两个第一隔离沟槽。
概念15.根据概念14所述的功率半导体器件，还包括：
多个第二隔离沟槽，形成在所述检测-FET的有源区的外部，其中所述第二隔离沟槽的每一个包括所述主沟槽之一的部分。
概念16.一种半导体器件，包括：
主-FET，所述主-FET包括主-FET源区；
电流检测FET(检测-FET)，配置为产生对应于所述主-FET的漏源电流的信号，其中所述检测-FET的栅极和漏极耦合到所述主-FET的栅极和漏极，所述检测-FET包括：
形成在第一水平维度上的多个第一沟槽，配置为将检测-FET源区与所述主-FET源区隔离，
其中所述沟槽的每一个包括在垂直维度上的导体和电介质的多个交替层；以及
在垂直水平维度(perpendicular horizontal dimension)上的至少一个第二沟槽，位于所述检测-FET源区和所述主-FET源区之间并且配置为将所述检测-FET源区与所述主-FET源区隔离；以及缓冲区，其分离检测-FET源区和所述主-FET源区。
概念17.根据概念16所述的半导体器件，其中，所述缓冲区包括比所述第一沟槽和第二沟槽的深度浅的PN结，其中所述缓冲层形成浮置结，
其中所述浮置结的第一侧耦合到所述主-FET的所述漏极，并且所述浮置结的第二侧与所述半导体器件的任何区域隔离，并且其中
所述浮置结的所述第二侧由两个垂直沟槽界定，每个沟槽包括由绝缘体层包围的至少一层导电材料。
概念18.根据概念16或17所述的半导体器件，其中所述沟槽向所述主-FET提供电荷平衡。
概念19.根据概念16至18所述的半导体器件，其中所述沟槽包括两个独立的导电层，所述导电层包括掺杂的多晶硅材料，并且所述两个独立的导电层通过氧化物层彼此隔离。
概念20.根据概念16至19所述的半导体器件，包括至少两个电流检测器件。
概念21.根据概念20所述的半导体器件，其中所述至少两个电流检测器件各自包括检测-FET源区，并且其中所述至少两个检测-FET源区由主-FET源区分隔开。
概念22.根据概念19至21所述的半导体器件，其中所述主-FET的沟槽中的底部导电层耦合到所述主-FET源极，并且所述检测-FET的沟槽中的底部导电层耦合到所述检测-FET源极。
概念23.一种功率半导体器件，包括：
垂直沟槽主MOSFET(主-FET)，配置为控制漏源电流；
垂直沟槽电流检测FET(检测-FET)，配置为产生对应于所述漏源电流的电压；以及
隔离沟槽，配置为将所述主-FET与所述检测-FET隔离，
其中所述隔离沟槽与所述主-FET的多个沟槽成角度形成并与其交叉。
概念24.根据概念23所述的功率半导体器件，其中，所述主-FET的垂直沟槽包括彼此电隔离的至少两个垂直排列的电极。
概念25.根据概念24所述的功率半导体器件，其中，所述电极中的较低者耦合到所述主-FET的源极。
概念26.根据概念24或25所述的功率半导体器件，其中，所述电极中的较高者耦合到所述主-FET的栅极。
概念27.根据概念23至26所述的功率半导体器件，其中，所述角度大于40度。
概念28.根据概念23至27所述的功率半导体器件，其中，所述角度大致为90度。
概念29.根据概念23至28所述的功率半导体器件，其中，所述检测-FET和所述主-FET包括公共的栅极端子和漏极端子。
概念30.根据概念24所述的功率半导体器件，其中，所述主-FET的所述电极的较高者连接到所述主-FET栅极，并且所述检测-FET的上部电极连接到隔离的检测-FET栅极。
概念31.根据概念23至30所述的功率半导体器件，其中，所述检测-FET和所述主-FET包括公共的漏极端子、但是分离的源极端子和栅极端子。
概念32.一种功率半导体器件，包括：
衬底；
分离栅垂直沟槽主MOSFET(主-FET)，形成在所述衬底中，配置为控制漏源电流，
其中所述主-FET包括设置在所述衬底的表面上的主-FET源极金属，所述主-FET源极金属配置为将多个主-FET源区彼此耦合并耦合到多个主-FET源极端子；以及
垂直沟槽电流检测FET(检测-FET)，形成在所述衬底中，配置为产生对应于所述漏源电流的信号，
其中所述检测-FET在至少三侧上被所述主-FET源极金属包围。
概念33.根据概念32所述的功率半导体器件，还包括设置在所述衬底的表面上的检测-FET源极金属，所述检测-FET源极金属配置为将至少一个检测-FET源区耦合到至少一个检测-FET源极端子。
概念34.根据概念33所述的功率半导体器件，其中所述检测-FET源极金属通过在所述主-FET源极金属的水平面处缺乏金属的表面隔离区与所述主-FET源极金属电隔离。
概念35.根据概念34所述的功率半导体器件，包括沉积在所述表面隔离区中的所述衬底表面上的绝缘体。
概念36.根据概念35所述的功率半导体器件，其中，所述绝缘体包括硼磷硅酸盐玻璃。
概念37.根据概念32至36所述的功率半导体器件，包括彼此物理分离的至少两个垂直沟槽电流检测FET。
概念38.根据概念32至37所述的功率半导体器件，其中，所述检测-FET和所述主-FET包括公共的栅极端子和漏极端子。
概念39.一种功率半导体器件，包括：
主垂直沟槽金属氧化物半导体场效应晶体管(主-MOSFET)，包括：
多个平行的主沟槽，其中所述主沟槽包括耦合到所述主-MOSFET的栅极的第一电极；以及
在所述主沟槽之间的多个主台面，其中所述主台面包括所述主MOSFET的主源极和主体；以及检测二极管，包括：
多个检测二极管沟槽，其中所述检测二极管沟槽的每一个包括所述主沟槽之一的部分；以及
在所述源极-FET沟槽之间的多个检测二极管台面，其中所述检测二极管台面包括与所述主-MOSFET的所述主源极电隔离的检测二极管阳极。
概念40.一种半导体器件，包括：
主-FET，包括主-FET源区；
检测二极管，配置为产生对应于所述主-FET的温度的信号，所述检测二极管包括：
在第一水平维度上形成的多个第一沟槽，其配置为将检测二极管阳极区域与所述主-FET源区隔离，
其中所述沟槽的每一个包括在垂直维度上的导体和电介质的多个交替层；以及
在垂直水平维度上的至少一个第二沟槽，所述第二沟槽位于所述检测二极管阳极区域和所述主-FET源区之间，并且配置为将所述检测二极管阳极区域与所述主-FET源区隔离；以及
缓冲区，其分隔检测二极管阳极区域和所述主-FET源区。
概念41.一种电子电路，包括：
配置为切换至少1安培的电流的垂直沟槽金属氧化物半导体场效应晶体管以及配置为提供MOSFET的漏极到源极电流的指示的电流检测场效应晶体管。电流检测FET的电流检测比为至少15000并且可以大于29000。

Claims (40)

1.一种电子电路，包括：
垂直沟槽金属氧化物半导体场效应晶体管(MOSFET)，配置为控制至少1安培的电流；以及
电流检测FET，配置为提供电信号作为所述MOSFET的漏极到源极电流的指示，
其中，所述电流检测FET的电流检测比大于15000。
2.根据权利要求1所述的电子电路，其中所述电流检测FET的所述电流检测比大于20000。
3.根据权利要求1所述的电子电路，其中所述电流检测FET的所述电流检测比大于29000。
4.根据权利要求1所述的电子电路，其中所述检测-FET设置在所述MOSFET内。
5.根据权利要求1所述的电子电路，其中所述检测-FET与所述MOSFET物理地共享沟槽。
6.根据权利要求1所述的电子电路，其中所述MOSFET包括沟槽，并且其中所述沟槽包括彼此电隔离的至少两个电极。
7.根据权利要求1所述的电子电路，其中所述MOSFET的栅极和漏极电耦合到所述电流检测FET的栅极和漏极。
8.一种功率半导体器件，包括：
主垂直沟槽金属氧化物半导体场效应晶体管(主-MOSFET)，包括：
多个平行的主沟槽，其中所述主沟槽包括耦合到所述主-MOSFET的栅极的第一电极；以及
在所述主沟槽之间的多个主台面，其中所述主台面包括所述主MOSFET的主源极和主体；以及
电流检测场效应晶体管(检测-FET)，包括：
多个检测-FET沟槽，其中所述检测-FET沟槽中的每一个包括所述主沟槽之一的部分；以及
在所述源极-FET沟槽之间的多个源极-FET台面和体台面，其中所述源极-FET台面包括检测-FET源极，所述检测-FET源极与所述主-MOSFET的所述主源极电隔离。
9.根据权利要求8所述的功率半导体器件，其中所述多个平行的主沟槽中的每一个还包括耦合到所述主-MOSFET的所述主源极的主栅极电极。
10.根据权利要求9所述的功率半导体器件，其中所述源极-FET沟槽包括耦合到所述主-MOSFET的所述栅极的第一电极和与所述主栅极电极电隔离的第二电极。
11.根据权利要求8所述的功率半导体器件，其中所述主MOSFET的部分在至少三侧上围绕所述电流检测FET。
12.根据权利要求11所述的功率半导体器件，还包括没有表面金属化的表面隔离区，其在所述至少三侧上位于所述电流检测-FET和所述主-MOSFET之间。
13.根据权利要求12所述的功率半导体器件，其中所述表面隔离区的部分形成在与所述平行主沟槽交叉的隔离沟槽之间。
14.根据权利要求8所述的功率半导体器件，还包括：
与所述平行主沟槽交叉的至少两个第一隔离沟槽。
15.根据权利要求14所述的功率半导体器件，还包括：
多个第二隔离沟槽，形成在所述检测-FET的有源区的外部，其中所述第二隔离沟槽中的每一个包括所述主沟槽之一的部分。
16.一种半导体器件，包括：
主-FET，所述主-FET包括主-FET源区；
电流检测FET(检测-FET)，配置为产生对应于所述主-FET的漏源电流的信号，其中所述检测-FET的栅极和漏极耦合到所述主-FET的栅极和漏极，所述检测-FET包括：
形成在第一水平维度上的多个第一沟槽，配置为将检测-FET源区与所述主-FET源区隔离，
其中所述沟槽中的每一个包括在垂直维度上的导体和电介质的多个交替层；以及
在垂直水平维度上的至少一个第二沟槽，位于所述检测-FET源区和所述主-FET源区之间并且配置为将所述检测-FET源区与所述主-FET源区隔离；以及
缓冲区，其分离检测-FET源区和所述主-FET源区。
17.根据权利要求16所述的半导体器件，其中所述缓冲区包括比所述第一沟槽和第二沟槽的深度浅的PN结，其中所述缓冲层形成浮置结，
其中所述浮置结的第一侧耦合到所述主-FET的所述漏极，并且所述浮置结的第二侧与所述半导体器件的任何区域隔离，并且其中
所述浮置结的所述第二侧由两个垂直沟槽界定，每个沟槽包括由绝缘体层包围的至少一层导电材料。
18.根据权利要求16所述的半导体器件，其中所述沟槽向所述主-FET提供电荷平衡。
19.根据权利要求16所述的半导体器件，其中所述沟槽包括两个独立的导电层，所述导电层包括掺杂的多晶硅材料，并且所述两个独立的导电层通过氧化物层彼此隔离。
20.根据权利要求16所述的半导体器件，包括至少两个电流检测器件。
21.根据权利要求20所述的半导体器件，其中所述至少两个电流检测器件各自包括检测-FET源区，并且其中所述至少两个检测-FET源区由主-FET源区分隔开。
22.根据权利要求19所述的半导体器件，其中所述主-FET的沟槽中的底部导电层耦合到所述主-FET源极，并且所述检测-FET的沟槽中的底部导电层耦合到所述检测-FET源极。
23.一种功率半导体器件，包括：
垂直沟槽主MOSFET(主-FET)，配置为控制漏源电流；
垂直沟槽电流检测FET(检测-FET)，配置为产生对应于所述漏源电流的电压；以及
隔离沟槽，配置为将所述主-FET与所述检测-FET隔离，
其中所述隔离沟槽与所述主-FET的多个沟槽成角度形成并与其交叉。
24.根据权利要求23所述的功率半导体器件，其中所述主-FET的垂直沟槽包括彼此电隔离的至少两个垂直排列的电极。
25.根据权利要求24所述的功率半导体器件，其中所述电极中的较低者耦合到所述主-FET的源极。
26.根据权利要求24所述的功率半导体器件，其中所述电极中的较高者耦合到所述主-FET的栅极。
27.根据权利要求23所述的功率半导体器件，其中所述角度大于40度。
28.根据权利要求23所述的功率半导体器件，其中所述角度大致为90度。
29.根据权利要求23所述的功率半导体器件，其中所述检测-FET和所述主-FET包括公共的栅极端子和漏极端子。
30.根据权利要求24所述的功率半导体器件，其中所述主-FET的所述电极的较高者连接到所述主-FET栅极，并且所述检测-FET的上部电极连接到隔离的检测-FET栅极。
31.根据权利要求23所述的功率半导体器件，其中所述检测-FET和所述主-FET包括公共的漏极端子、但是分离的源极端子和栅极端子。
32.一种功率半导体器件，包括：
衬底；
分离栅垂直沟槽主MOSFET(主-FET)，形成在所述衬底中，配置为控制漏源电流，
其中所述主-FET包括设置在所述衬底的表面上的主-FET源极金属，所述主-FET源极金属配置为将多个主-FET源区彼此耦合并耦合到多个主-FET源极端子；以及
垂直沟槽电流检测FET(检测-FET)，形成在所述衬底中，配置为产生对应于所述漏源电流的信号，
其中所述检测-FET在至少三侧上被所述主-FET源极金属包围。
33.根据权利要求32所述的功率半导体器件，还包括设置在所述衬底的表面上的检测-FET源极金属，所述检测-FET源极金属配置为将至少一个检测-FET源区耦合到至少一个检测-FET源极端子。
34.根据权利要求33所述的功率半导体器件，其中所述检测-FET源极金属通过在所述主-FET源极金属的水平面处缺乏金属的表面隔离区与所述主-FET源极金属电隔离。
35.根据权利要求34所述的功率半导体器件，包括沉积在所述表面隔离区中的所述衬底的表面上的绝缘体。
36.根据权利要求35所述的功率半导体器件，其中所述绝缘体包括硼磷硅酸盐玻璃。
37.根据权利要求32所述的功率半导体器件，包括彼此物理分离的至少两个垂直沟槽电流检测FET。
38.根据权利要求32所述的功率半导体器件，其中所述检测-FET和所述主-FET包括公共的栅极端子和漏极端子。
39.一种功率半导体器件，包括：
主垂直沟槽金属氧化物半导体场效应晶体管(主-MOSFET)，包括：
多个平行的主沟槽，其中所述主沟槽包括耦合到所述主-MOSFET的栅极的第一电极；以及
在所述主沟槽之间的多个主台面，其中所述主台面包括所述主MOSFET的主源极和主体；以及
检测二极管，包括：
多个检测二极管沟槽，其中所述检测二极管沟槽中的每一个包括所述主沟槽之一的部分；以及
在所述源极-FET沟槽之间的多个检测二极管台面，其中所述检测二极管台面包括与所述主-MOSFET的所述主源极电隔离的检测二极管阳极。
40.一种半导体器件，包括：
主-FET，包括主-FET源区；
检测二极管，配置为产生对应于所述主-FET的温度的信号，所述检测二极管包括：
在第一水平维度上形成的多个第一沟槽，其配置为将检测二极管阳极区域与所述主-FET源区隔离，
其中所述沟槽中的每一个包括在垂直维度上的导体和电介质的多个交替层；以及
在垂直水平维度上的至少一个第二沟槽，所述第二沟槽位于所述检测二极管阳极区域和所述主-FET源区之间，并且配置为将所述检测二极管阳极区域与所述主-FET源区隔离；以及
缓冲区，其分隔检测二极管阳极区域和所述主-FET源区。
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