JP4945055B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP4945055B2 JP4945055B2 JP2003286142A JP2003286142A JP4945055B2 JP 4945055 B2 JP4945055 B2 JP 4945055B2 JP 2003286142 A JP2003286142 A JP 2003286142A JP 2003286142 A JP2003286142 A JP 2003286142A JP 4945055 B2 JP4945055 B2 JP 4945055B2
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- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Description
MISFETを有し、
半導体基板の主面に形成された第1導電型の第1半導体層と、
前記第1半導体層上に形成され、前記第1導電型とは逆の第2導電型の第2半導体層と、
前記半導体基板の主面に形成され、少なくとも底部の一部が前記第1半導体層と接し、深さが1μm以下である複数の第1溝部と、
前記第1溝部の側壁および底面に形成された第1絶縁膜と、
前記第1絶縁膜上に形成され、前記第1溝部を埋め込む第1導電体と、
前記第1溝部に隣接して前記第2半導体層内に形成され、前記第1導電型を有する第3半導体層と、
隣り合う前記第1溝部間の前記第2半導体層内に形成された前記第2導電型の第4半導体層と、
前記第3半導体層および前記第4半導体層と電気的に接続する第1電極とを有し、
前記第1半導体層および前記第3半導体層は、前記MISFETのソースまたはドレインを形成し、前記第2半導体層は、前記MISFETのチャネル形成領域を形成し、
前記第2半導体層内の前記第3半導体層の下部に前記第2半導体層より不純物濃度が高い前記第2導電型の第5半導体層が形成されている。
(a)半導体基板の主面に第1導電型の第1半導体層を形成する工程と、
(b)前記半導体基板に前記第1導電型とは逆の第2導電型の不純物を導入して、前記第1半導体層上に前記第2導電型の第2半導体層を形成する工程と、
(c)前記半導体基板の主面に複数の第1溝部を形成する工程と、
(d)前記第1溝部内に第1絶縁膜を形成する工程と、
(e)前記第1絶縁膜の存在下で前記第1溝部内に第1導電体を埋め込み、ゲート電極を形成する工程と、
(f)前記半導体基板に前記第1導電型の不純物を導入して、前記第2半導体層上に前記第1溝部と隣接する前記第1導電型の第3半導体層を形成する工程と、
(g)前記半導体基板に前記第1導電型とは逆の前記第2導電型の不純物を導入して、前記第2半導体層内の前記第3半導体層の下部に前記第2導電型の第5半導体層を形成する工程と、
(h)隣り合う前記ゲート電極間に配置されるように、前記半導体基板の主面に前記第3半導体層を貫通する複数の第2溝部を形成する工程と、
(i)前記第2溝部の底部から前記半導体基板に前記第2導電型の不純物を導入し、前記第2半導体層内にて前記第2溝部の底部を覆うように前記第2導電型の第4半導体層を形成する工程と、
(j)前記第2溝部を埋め込み、前記第3半導体層および前記第4半導体層と電気的に接続する第1電極を形成する工程とを含み、
前記第1溝部は、少なくとも底部の一部が前記第1半導体層と接し、深さが1μm以下となるように形成し、
前記第5半導体層は、前記第2半導体層より不純物濃度が高くなるように形成し、
前記第1半導体層および前記第3半導体層が前記MISFETのソースまたはドレインとなり、前記第2半導体層が前記MISFETのチャネル形成領域となる前記MISFETを形成するものである。
本実施の形態1の半導体装置は、たとえばnチャネル型のトレンチゲート型パワーMISFETを有するものである。このような本実施の形態1の半導体装置について図1〜図25を用いて製造工程に従って説明する。
次に、本実施の形態2の半導体装置について説明する。
次に、本実施の形態3の半導体装置について説明する。
1A n+型単結晶シリコン基板
1B n-型単結晶シリコン層(第1半導体層)
3 酸化シリコン膜
5 p型ウエル
7 溝(第1溝部)
9 熱酸化膜(第1絶縁膜)
10 ゲート電極(第1導電体)
10A 多結晶シリコン層
10B シリサイド層(シリコン化合物膜)
10C 窒化タングステン層(金属膜)
10D タングステン層(金属膜)
11 多結晶シリコンパターン
12 酸化シリコン膜
13 p-型半導体領域(第2半導体層)
13A n-型半導体領域(第6半導体層)
14 p型半導体領域(第5半導体層)
15 n+型半導体領域(第3半導体層)
16 絶縁膜
17 コンタクト溝(第2溝部)
18 コンタクト溝
20 p+型半導体領域(第4半導体層)
21 ゲート配線(第2電極、第1部)
21A ゲートフィンガー部(第2電極、第2部)
22 ソースパッド(第1電極)
101 n+型単結晶シリコン基板
102 n-型単結晶シリコン層
103 溝
104 ゲート絶縁膜
105 ゲート部
106 ソース電極
107 絶縁膜
108 溝
109 p-型半導体領域
110 p+型半導体領域
111 n+型半導体領域
CHP チップ領域
DEP 空乏層
GELE ゲート電極
GP ゲートパッド
L1、L2、L3 配線
NEPI n-型単結晶シリコン層
NSEM n+型半導体領域
OF オリエンテーションフラット
PBOD p-型半導体領域
QH High−sideMISFET
QL Low−sideMISFET
W1 第1のウエハ
Claims (13)
- MISFETを有する半導体装置であって、
半導体基板の主面に形成された第1導電型の第1半導体層と、
前記第1半導体層上に形成され、前記第1導電型とは逆の第2導電型の第2半導体層と、
前記半導体基板の主面に形成され、少なくとも底部の一部が前記第1半導体層と接し、深さが1μm以下である複数の第1溝部と、
前記第1溝部の側壁および底面に形成された第1絶縁膜と、
前記第1絶縁膜上に形成され、前記第1溝部を埋め込む第1導電体と、
前記第1溝部に隣接して前記第2半導体層内に形成され、前記第1導電型を有する第3半導体層と、
隣り合う前記第1溝部間の前記第2半導体層内に形成された前記第2導電型の第4半導体層と、
前記第3半導体層および前記第4半導体層と電気的に接続する第1電極とを有し、
前記第1半導体層および前記第3半導体層は、前記MISFETのソースまたはドレインを形成し、前記第2半導体層は、前記MISFETのチャネル形成領域を形成し、
前記第2半導体層内の前記第3半導体層の下部に前記第2半導体層より不純物濃度が高い前記第2導電型の第5半導体層が形成され、
前記第5半導体層はパンチスルーストッパー層を構成し、
前記第2半導体層はチャネル層を構成し、
前記第5半導体層は不純物濃度が一定部を有し、
前記第2半導体層は不純物濃度が深さ方向に減少する傾斜部を有し、
前記第1半導体層はドレイン領域を構成し、
前記第3半導体層はソース領域を構成し、
隣り合う前記第1溝部間にて前記半導体基板の主面から前記第3半導体層を貫通する第2溝部が形成され、
前記第4半導体層は前記第2溝部の底部を覆うように形成され、
前記第1電極は前記第2溝部を埋め込むように形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記MISFETはトレンチゲート型パワーMISFETであることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1導電体と電気的に接続され、前記第1導電体より抵抗率の低い第2導電体から形成された第2電極を有することを特徴とする半導体装置。 - 請求項3記載の半導体装置において、
前記MISFETは前記半導体基板のチップ領域に形成され、
前記第2電極は、前記チップ領域の周辺に沿って形成された第1部と、前記第1部より内側の前記チップ領域に延在する第2部とを有することを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1溝部の深さは、前記第2半導体層の深さの1.1倍以下であることを特徴とする半導体装置。 - 請求項5記載の半導体装置において、
前記第1溝部の前記第2半導体層からのはみ出し量は0.1μm以下であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1溝部の下部に前記第1溝部と接する前記第1導電型の第6半導体層が形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記MISFETのしきい値電圧は2V以下であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記MISFETはDC/DCコンバータのスイッチング素子として用いられることを特徴とする半導体装置。 - MISFETを有する半導体装置の製造方法であって、
(a)半導体基板の主面に第1導電型の第1半導体層を形成する工程、
(b)前記半導体基板の主面に複数の第1溝部を形成する工程、
(c)前記第1溝部内に第1絶縁膜を形成する工程、
(d)前記第1絶縁膜の存在下で前記第1溝部内に第1導電体を埋め込み、ゲート電極を形成する工程、
(e)前記(a)〜(d)工程後に、前記半導体基板に前記第1導電型とは逆の第2導電型の不純物を導入して、前記第1半導体層上に前記第2導電型の第2半導体層を形成する工程、
(f)前記(e)工程後に、前記半導体基板に熱処理を施す工程、
(g)前記(f)工程後に、前記半導体基板に前記第1導電型の不純物を導入し、前記第2半導体層上に前記第1溝部と隣接する前記第1導電型の第3半導体層を形成する工程、
(h)前記(f)工程後に、前記半導体基板に前記第1導電型とは逆の前記第2導電型の不純物を導入して、前記第2半導体層内の前記第3半導体層の下部に前記第2導電型の第5半導体層を形成する工程、
(i)前記(g)工程後および前記(h)工程後に、前記半導体基板に熱処理を施す工程、
(j)隣り合う前記ゲート電極間に配置されるように、前記半導体基板の主面に前記第3半導体層を貫通する複数の第2溝部を形成する工程、
(k)前記第2溝部の底部から前記半導体基板に前記第2導電型の不純物を導入し、前記第2半導体層内にて前記第2溝部の底部を覆うように前記第2導電型の第4半導体層を形成する工程、
(l)前記第2溝部を埋め込み、前記第3半導体層および前記第4半導体層と電気的に接続する第1電極を形成する工程、
を含み、
前記第1溝部は、少なくとも底部の一部が前記第1半導体層と接し、深さが1μm以下となるように形成し、
前記第5半導体層は、前記第2半導体層より不純物濃度が高くなるように形成し、
前記第1半導体層および前記第3半導体層が前記MISFETのソースまたはドレインとなり、前記第2半導体層が前記MISFETのチャネル形成領域となる前記MISFETを形成し、
前記第5半導体層はパンチスルーストッパー層を構成し、
前記第5半導体層は不純物濃度が一定部を有し、
前記第2半導体層は不純物濃度が深さ方向に減少する傾斜部を有することを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記半導体基板は、(100)面の法線からオリエンテーションフラットまたはノッチの形成されている方向に第1の角度だけ傾けた直線を法線とする結晶面を主面とすることを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記(b)工程は、前記第1溝部の底部から前記第1導電型の不純物を導入し、前記第1溝部の下部に前記第1溝部と接する前記第1導電型の第6半導体層を形成する工程を含むことを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記MISFETはトレンチゲート型パワーMISFETであることを特徴とする半導体装置の製造方法。
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Families Citing this family (64)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4860122B2 (ja) * | 2004-06-25 | 2012-01-25 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2006049341A (ja) | 2004-07-30 | 2006-02-16 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US8283723B2 (en) * | 2005-02-11 | 2012-10-09 | Alpha & Omega Semiconductor Limited | MOS device with low injection diode |
US7453119B2 (en) * | 2005-02-11 | 2008-11-18 | Alphs & Omega Semiconductor, Ltd. | Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact |
US8362547B2 (en) * | 2005-02-11 | 2013-01-29 | Alpha & Omega Semiconductor Limited | MOS device with Schottky barrier controlling layer |
US7285822B2 (en) * | 2005-02-11 | 2007-10-23 | Alpha & Omega Semiconductor, Inc. | Power MOS device |
US8093651B2 (en) * | 2005-02-11 | 2012-01-10 | Alpha & Omega Semiconductor Limited | MOS device with integrated schottky diode in active region contact trench |
US7948029B2 (en) | 2005-02-11 | 2011-05-24 | Alpha And Omega Semiconductor Incorporated | MOS device with varying trench depth |
US7786531B2 (en) * | 2005-03-18 | 2010-08-31 | Alpha & Omega Semiconductor Ltd. | MOSFET with a second poly and an inter-poly dielectric layer over gate for synchronous rectification |
JP4955222B2 (ja) | 2005-05-20 | 2012-06-20 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2008159916A (ja) | 2006-12-25 | 2008-07-10 | Sanyo Electric Co Ltd | 半導体装置 |
KR100824205B1 (ko) * | 2006-12-26 | 2008-04-21 | 매그나칩 반도체 유한회사 | Dmos 트랜지스터 및 그 제조방법 |
KR100777593B1 (ko) * | 2006-12-27 | 2007-11-16 | 동부일렉트로닉스 주식회사 | 트랜치 게이트 모스 소자 및 그 제조 방법 |
US8575687B2 (en) * | 2007-05-30 | 2013-11-05 | Rohm Co., Ltd. | Semiconductor switch device |
JP5285874B2 (ja) * | 2007-07-03 | 2013-09-11 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR100970282B1 (ko) * | 2007-11-19 | 2010-07-15 | 매그나칩 반도체 유한회사 | 트렌치 mosfet 및 그 제조방법 |
CN101465376B (zh) * | 2007-12-21 | 2012-07-04 | 万国半导体股份有限公司 | 具有低注入二极管的mos器件 |
US7977737B2 (en) * | 2008-03-06 | 2011-07-12 | Infineon Technologies Austria Ag | Semiconductor device having additional capacitance to inherent gate-drain or inherent drain-source capacitance |
JP5819064B2 (ja) * | 2008-05-20 | 2015-11-18 | ローム株式会社 | 半導体装置 |
JP5239548B2 (ja) * | 2008-06-25 | 2013-07-17 | 富士通セミコンダクター株式会社 | 半導体装置及び半導体装置の製造方法 |
JP5297104B2 (ja) | 2008-07-01 | 2013-09-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8193579B2 (en) * | 2008-07-29 | 2012-06-05 | Rohm Co., Ltd. | Trench type semiconductor device and fabrication method for the same |
US8362552B2 (en) * | 2008-12-23 | 2013-01-29 | Alpha And Omega Semiconductor Incorporated | MOSFET device with reduced breakdown voltage |
CN101710586B (zh) * | 2009-01-09 | 2011-12-28 | 深超光电(深圳)有限公司 | 提高开口率的储存电容及其制作方法 |
US8168497B2 (en) * | 2009-06-01 | 2012-05-01 | Sensor Electronic Technology, Inc. | Low-resistance electrode design |
US8846473B2 (en) * | 2009-06-01 | 2014-09-30 | Sensor Electronic Technology, Inc. | Low-resistance electrode design |
JP2011009352A (ja) | 2009-06-24 | 2011-01-13 | Renesas Electronics Corp | 半導体装置およびその製造方法ならびにそれを用いた電源装置 |
US8058674B2 (en) * | 2009-10-07 | 2011-11-15 | Moxtek, Inc. | Alternate 4-terminal JFET geometry to reduce gate to source capacitance |
US9425305B2 (en) | 2009-10-20 | 2016-08-23 | Vishay-Siliconix | Structures of and methods of fabricating split gate MIS devices |
US9419129B2 (en) | 2009-10-21 | 2016-08-16 | Vishay-Siliconix | Split gate semiconductor device with curved gate oxide profile |
JP5736394B2 (ja) * | 2010-03-02 | 2015-06-17 | ヴィシェイ−シリコニックス | 半導体装置の構造及びその製造方法 |
JP5662865B2 (ja) * | 2010-05-19 | 2015-02-04 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US9653597B2 (en) | 2010-05-20 | 2017-05-16 | Infineon Technologies Americas Corp. | Method for fabricating a shallow and narrow trench FET and related structures |
JP5616720B2 (ja) * | 2010-08-30 | 2014-10-29 | セイコーインスツル株式会社 | 半導体装置およびその製造方法 |
JP5674530B2 (ja) | 2010-09-10 | 2015-02-25 | ルネサスエレクトロニクス株式会社 | 半導体装置の制御装置 |
JP5638340B2 (ja) * | 2010-10-20 | 2014-12-10 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5574923B2 (ja) * | 2010-11-10 | 2014-08-20 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP5694119B2 (ja) * | 2010-11-25 | 2015-04-01 | 三菱電機株式会社 | 炭化珪素半導体装置 |
US20120175699A1 (en) * | 2011-01-06 | 2012-07-12 | Force Mos Technology Co., Ltd. | Trench mosfet with super pinch-off regions and self-aligned trenched contact |
CN102184945A (zh) * | 2011-05-03 | 2011-09-14 | 成都芯源系统有限公司 | 一种槽栅型mosfet器件 |
WO2012158977A2 (en) | 2011-05-18 | 2012-11-22 | Vishay-Siliconix | Semiconductor device |
JP5677222B2 (ja) | 2011-07-25 | 2015-02-25 | 三菱電機株式会社 | 炭化珪素半導体装置 |
JP6290526B2 (ja) * | 2011-08-24 | 2018-03-07 | ローム株式会社 | 半導体装置およびその製造方法 |
US8368192B1 (en) * | 2011-09-16 | 2013-02-05 | Powertech Technology, Inc. | Multi-chip memory package with a small substrate |
US8716787B2 (en) * | 2012-03-27 | 2014-05-06 | Super Group Semiconductor Co., Ltd. | Power semiconductor device and fabrication method thereof |
US9000497B2 (en) * | 2012-09-14 | 2015-04-07 | Renesas Electronics Corporation | Trench MOSFET having an independent coupled element in a trench |
US9105713B2 (en) | 2012-11-09 | 2015-08-11 | Infineon Technologies Austria Ag | Semiconductor device with metal-filled groove in polysilicon gate electrode |
JP5876008B2 (ja) * | 2013-06-03 | 2016-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
TWI487115B (zh) * | 2013-06-07 | 2015-06-01 | Sinopower Semiconductor Inc | 溝渠式功率元件及其製造方法 |
US20150118810A1 (en) * | 2013-10-24 | 2015-04-30 | Madhur Bobde | Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path |
CN105745758B (zh) * | 2013-11-29 | 2019-05-10 | Abb瑞士股份有限公司 | 绝缘栅双极晶体管 |
US9773863B2 (en) * | 2014-05-14 | 2017-09-26 | Infineon Technologies Austria Ag | VDMOS having a non-depletable extension zone formed between an active area and side surface of semiconductor body |
US10468479B2 (en) | 2014-05-14 | 2019-11-05 | Infineon Technologies Austria Ag | VDMOS having a drift zone with a compensation structure |
WO2016028943A1 (en) | 2014-08-19 | 2016-02-25 | Vishay-Siliconix | Electronic circuit |
TWI581425B (zh) | 2015-11-24 | 2017-05-01 | Macroblock Inc | And a power semiconductor device having an edge terminal structure having a gradation concentration |
DE102016101801B4 (de) * | 2016-02-02 | 2021-01-14 | Infineon Technologies Ag | Lastanschluss eines leistungshalbleiterbauelements, leistungshalbleitermodul damit und herstellungsverfahren dafür |
DE102019101326A1 (de) * | 2018-01-19 | 2019-07-25 | Infineon Technologies Ag | Halbleitervorrichtung, die erste und zweite Kontaktschichten enthält, und Herstellungsverfahren |
JP6994991B2 (ja) * | 2018-03-16 | 2022-02-04 | 株式会社 日立パワーデバイス | 半導体装置、パワーモジュールおよび電力変換装置 |
JP7272071B2 (ja) * | 2019-04-04 | 2023-05-12 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
US11217541B2 (en) | 2019-05-08 | 2022-01-04 | Vishay-Siliconix, LLC | Transistors with electrically active chip seal ring and methods of manufacture |
US11218144B2 (en) | 2019-09-12 | 2022-01-04 | Vishay-Siliconix, LLC | Semiconductor device with multiple independent gates |
JP7120192B2 (ja) * | 2019-09-17 | 2022-08-17 | 株式会社デンソー | 半導体装置 |
TWI739252B (zh) * | 2019-12-25 | 2021-09-11 | 杰力科技股份有限公司 | 溝槽式mosfet元件及其製造方法 |
US11685609B2 (en) * | 2020-11-27 | 2023-06-27 | Terry Michael Brown, SR. | Split drive sprocket assembly |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60186068A (ja) * | 1985-01-31 | 1985-09-21 | Hitachi Ltd | 絶縁ゲート電界効果トランジスタ |
US5282018A (en) * | 1991-01-09 | 1994-01-25 | Kabushiki Kaisha Toshiba | Power semiconductor device having gate structure in trench |
JPH0653514A (ja) * | 1992-08-03 | 1994-02-25 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置の製造方法 |
JP3167457B2 (ja) * | 1992-10-22 | 2001-05-21 | 株式会社東芝 | 半導体装置 |
GB9313843D0 (en) * | 1993-07-05 | 1993-08-18 | Philips Electronics Uk Ltd | A semiconductor device comprising an insulated gate field effect transistor |
WO1998012741A1 (en) * | 1996-09-18 | 1998-03-26 | Advanced Micro Devices, Inc. | Short channel non-self aligned vmos field effect transistor |
US6084264A (en) * | 1998-11-25 | 2000-07-04 | Siliconix Incorporated | Trench MOSFET having improved breakdown and on-resistance characteristics |
ATE457084T1 (de) * | 1998-12-18 | 2010-02-15 | Infineon Technologies Ag | Feldeffekt-transistoranordnung mit einer grabenförmigen gate-elektrode und einer zusätzlichen hochdotierten schicht im bodygebiet |
JP2000269487A (ja) * | 1999-03-15 | 2000-09-29 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2000269518A (ja) * | 1999-03-18 | 2000-09-29 | Toshiba Corp | 電力用半導体素子及び半導体層の形成方法 |
US20010001494A1 (en) | 1999-04-01 | 2001-05-24 | Christopher B. Kocon | Power trench mos-gated device and process for forming same |
US6348712B1 (en) * | 1999-10-27 | 2002-02-19 | Siliconix Incorporated | High density trench-gated power MOSFET |
JP3884206B2 (ja) * | 2000-01-20 | 2007-02-21 | 株式会社東芝 | 半導体装置 |
JP4179491B2 (ja) * | 2000-04-25 | 2008-11-12 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法、ならびにその特性評価方法 |
JP4150496B2 (ja) * | 2000-12-28 | 2008-09-17 | 株式会社日立製作所 | 半導体装置及びその製造方法 |
JP3531613B2 (ja) * | 2001-02-06 | 2004-05-31 | 株式会社デンソー | トレンチゲート型半導体装置及びその製造方法 |
JP2002270825A (ja) * | 2001-03-08 | 2002-09-20 | Hitachi Ltd | 電界効果トランジスタ及び半導体装置の製造方法 |
JP4025063B2 (ja) * | 2001-12-06 | 2007-12-19 | 株式会社ルネサステクノロジ | 半導体装置 |
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US20090212358A1 (en) | 2009-08-27 |
US20070120194A1 (en) | 2007-05-31 |
US20050029584A1 (en) | 2005-02-10 |
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US7981747B2 (en) | 2011-07-19 |
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