JP5638340B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5638340B2 JP5638340B2 JP2010235632A JP2010235632A JP5638340B2 JP 5638340 B2 JP5638340 B2 JP 5638340B2 JP 2010235632 A JP2010235632 A JP 2010235632A JP 2010235632 A JP2010235632 A JP 2010235632A JP 5638340 B2 JP5638340 B2 JP 5638340B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- conductivity type
- embedded
- semiconductor device
- type impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 121
- 239000010410 layer Substances 0.000 claims description 155
- 239000012535 impurity Substances 0.000 claims description 108
- 239000000758 substrate Substances 0.000 claims description 16
- 239000002344 surface layer Substances 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 description 20
- 230000015556 catabolic process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0869—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
前記半導体基板上に形成された第1導電型の半導体層と、
前記半導体層の表層に形成された第2導電型不純物層と、
前記第2導電型不純物層の表層のうち縁を除いた領域に形成された第1導電型不純物層と、
平面視で前記第1導電型不純物層が内側に凹むことにより形成されたゲートコンタクト領域と、
前記第2導電型不純物層のうち前記第1導電型不純物層が形成されていない領域上に、絶縁層を介して少なくとも一部が形成され、前記第1導電型不純物層を囲んでおり、平面視で前記ゲートコンタクト領域と重なる部分が内側に突出している上部ゲート電極と、
前記半導体層のうち前記第1導電型不純物層が形成されている領域に形成され、前記第2導電型不純物層より深く前記半導体層に埋め込まれており、第1の方向に沿って互いに平行に延伸しており、両端がそれぞれ前記第1導電型不純物層からはみ出すことにより前記上部ゲート電極に接続している複数の第1埋込ゲート電極と、
前記上部ゲート電極と重なる位置で、前記半導体層に、前記第1埋込ゲート電極と同じ深さに埋め込まれており、前記複数の第1埋込ゲート電極の端部を互いに接続する接続用埋込電極と、
前記第1導電型不純物層より深く、かつ前記第2導電型不純物層の底部より浅く前記半導体層に埋め込まれており、前記複数の第1埋込ゲート電極の相互間に位置しているソースコンタクトと、
を備え、
平面視で、
前記ゲートコンタクト領域に位置する前記上部ゲート電極と重なる方向に延伸している前記複数の第1埋込ゲート電極の少なくとも一部は、端部が前記ゲートコンタクト領域の縁上に位置しており、当該端部が第1の前記接続用埋込電極によって互いに接続されており、
前記第1の接続用埋込電極は、端部が前記第1の接続用埋込電極によって互いに接続されている前記複数の第1埋込ゲート電極の隣に位置する前記第1埋込ゲート電極であるコンタクト側第1埋込ゲート電極には、接続していない半導体装置が提供される。
図1は、第1の実施形態に係る半導体装置の構成を示す平面図である。図2は、図1に示した半導体装置が有する第2導電型不純物層120及び外周不純物層122のレイアウトを示す平面図である。図3は図1及び図2において点線で示した領域αにおける埋込ゲート電極140のレイアウトを示す平面拡大図である。図4は、図3のA−A´断面図である。
図9は、第2の実施形態にかかる半導体装置の構成を示す平面拡大図であり、第1の実施形態における図3に対応している。図10は図9のA−A´断面図である。本実施形態にかかる半導体装置は、以下の点を除いて第1の実施形態にかかる半導体装置と同様の構成である。
図11は、第3の実施形態にかかる半導体装置の平面図であり、第1の実施形態における図1に対応している。本実施形態にかかる半導体装置は、ゲートコンタクト領域102が半導体装置の角部に位置している点を除いて、第1又は第2の実施形態にかかる半導体装置と同様の構成である。なお図11では、第1の実施形態と同様の場合を示している。
本実施形態によっても、第1又は第2の実施形態と同様の効果を得ることができる。また、最終製品へのパッケージングに際して、リードフレーム(図のチップ上方に位置)からゲートパッドへの接続に要するワイヤ長も短くなる。
図12は、第4の実施形態にかかる半導体装置の構成を示す平面拡大図であり、第1の実施形態における図3に対応している。本実施形態に係る半導体装置は、以下の点を除いて、第1〜第3の実施形態のいずれかと同様である。なお図12では、第1の実施形態と同様の場合を示している。
図13は、第5の実施形態にかかる半導体装置の断面図であり、第1の実施形態における図4に相当している。図14は、図13に示した半導体装置の平面拡大図である。本実施形態にかかる半導体装置は、複数の第2導電型埋込層124を備えている点を除いて、第1〜第4の実施形態のいずれかと同様である。
図15は、第6の実施形態にかかる半導体装置の構成を示す断面図であり、第1の実施形態における図4に相当している。本実施形態にかかる半導体装置は、第1導電型の半導体基板100の代わりに第2導電型の半導体基板101が用いられている点を除いて、第1〜第5の実施形態のいずれかと同様の構成である。すなわち本実施形態にかかる半導体装置は、IGBT(Insulated Gate Bipolar Transistor)として機能する。
本実施形態によっても、第1〜第5の実施形態と同様の効果を得ることができる。
101 半導体基板
102 ゲートコンタクト領域
110 半導体層
120 第2導電型不純物層
122 外周不純物層
124 第2導電型埋込層
130 ゲート絶縁膜
140 埋込ゲート電極
141 接続用埋込電極
142 埋込ゲート電極
143 接続用埋込電極
144 埋込ゲート電極
145 埋込ゲート電極
150 第1導電型不純物層
160 上部ゲート電極
162 絶縁層
170 導電膜
200 層間絶縁膜
220 ソースコンタクト
222 ソースコンタクト
224 ソースコンタクト
310 ゲート電極
320 ソース電極
330 ドレイン電極
Claims (7)
- 半導体基板と、
前記半導体基板上に形成された第1導電型の半導体層と、
前記半導体層の表層に形成された第2導電型不純物層と、
前記第2導電型不純物層の表層のうち縁を除いた領域に形成された第1導電型不純物層、
平面視で前記第1導電型不純物層が内側に凹むことにより形成されたゲートコンタクト領域と、
前記第2導電型不純物層のうち前記第1導電型不純物層が形成されていない領域上に、絶縁層を介して少なくとも一部が形成され、前記第1導電型不純物層を囲んでおり、平面視で前記ゲートコンタクト領域と重なる部分が内側に突出している上部ゲート電極と、
前記半導体層のうち前記第1導電型不純物層が形成されている領域に形成され、前記第2導電型不純物層より深く前記半導体層に埋め込まれており、第1の方向に沿って互いに平行に延伸しており、両端がそれぞれ前記第1導電型不純物層からはみ出すことにより前記上部ゲート電極に接続している複数の第1埋込ゲート電極と、
前記上部ゲート電極と重なる位置で、前記半導体層に、前記第1埋込ゲート電極と同じ深さに埋め込まれており、前記複数の第1埋込ゲート電極の端部を互いに接続する接続用埋込電極と、
前記第1導電型不純物層より深く、かつ前記第2導電型不純物層の底部より浅く前記半導体層に埋め込まれており、前記複数の第1埋込ゲート電極の相互間に位置しているソースコンタクトと、
を備え、
平面視で、
前記ゲートコンタクト領域に位置する前記上部ゲート電極と重なる方向に延伸している前記複数の第1埋込ゲート電極の少なくとも一部は、端部が前記ゲートコンタクト領域の縁上に位置しており、当該端部が第1の前記接続用埋込電極によって互いに接続されており、
前記第1の接続用埋込電極は、端部が前記第1の接続用埋込電極によって互いに接続されている前記複数の第1埋込ゲート電極の隣に位置する前記第1埋込ゲート電極であるコンタクト側第1埋込ゲート電極には、接続していない半導体装置。 - 請求項1に記載の半導体装置において、
平面視で、前記上部ゲート電極のうち前記ゲートコンタクト領域に位置する部分の横を通る方向に延伸する前記第1埋込ゲート電極であるコンタクト側第1埋込ゲート電極は、端部が、前記第1の方向において第1の前記接続用埋込電極と同じ位置に位置しており、かつ前記第1の接続用埋込電極に接続されている半導体装置。 - 請求項2に記載の半導体装置において、
前記ゲートコンタクト領域から離れる方向において前記コンタクト側第1埋込ゲート電極の隣に位置する前記第1埋込ゲート電極である隣接第1埋込ゲート電極は、前記ゲートコンタクト領域と重なる領域まで延在しており、
前記上部ゲート電極のうち前記ゲートコンタクト領域に位置する部分と、前記隣接第1埋込ゲート電極の間には、前記ソースコンタクトが形成されている半導体装置。 - 請求項1〜3のいずれか一項に記載の半導体装置において、
前記第1の方向に直交する方向に延伸しており、前記複数の第1埋込ゲート電極をそれぞれ隣の前記第1埋込ゲート電極に接続する第2埋込ゲート電極を備える半導体装置。 - 請求項1〜4のいずれか一項に記載の半導体装置において、
前記半導体層に形成され、上端が前記第2導電型不純物層に接続し、互いに離間して配置された複数の第2導電型埋込層を備える半導体装置。 - 請求項1〜5のいずれか一項に記載の半導体装置において、
前記半導体基板は第1導電型である半導体装置。 - 請求項1〜5のいずれか一項に記載の半導体装置において、
前記半導体基板は第2導電型である半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010235632A JP5638340B2 (ja) | 2010-10-20 | 2010-10-20 | 半導体装置 |
US13/244,445 US8643103B2 (en) | 2010-10-20 | 2011-09-24 | Semiconductor device including gate contact region and protruding gate electrode |
CN201110318482.1A CN102456741B (zh) | 2010-10-20 | 2011-10-19 | 半导体器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010235632A JP5638340B2 (ja) | 2010-10-20 | 2010-10-20 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012089701A JP2012089701A (ja) | 2012-05-10 |
JP5638340B2 true JP5638340B2 (ja) | 2014-12-10 |
Family
ID=45972271
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010235632A Expired - Fee Related JP5638340B2 (ja) | 2010-10-20 | 2010-10-20 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8643103B2 (ja) |
JP (1) | JP5638340B2 (ja) |
CN (1) | CN102456741B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9818827B2 (en) * | 2015-04-08 | 2017-11-14 | Infineon Technologies Austria Ag | Field plate trench semiconductor device with planar gate |
US10665713B2 (en) * | 2017-09-28 | 2020-05-26 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001217419A (ja) | 2000-02-03 | 2001-08-10 | Denso Corp | 半導体装置 |
JP4945055B2 (ja) * | 2003-08-04 | 2012-06-06 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2005072185A (ja) * | 2003-08-22 | 2005-03-17 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP4791015B2 (ja) * | 2004-09-29 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | 縦型mosfet |
US7851349B2 (en) * | 2005-09-26 | 2010-12-14 | Infineon Technologies Austria Ag | Method for producing a connection electrode for two semiconductor zones arranged one above another |
JP2008160039A (ja) * | 2006-12-26 | 2008-07-10 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP5210564B2 (ja) | 2007-07-27 | 2013-06-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20100123193A1 (en) * | 2008-11-14 | 2010-05-20 | Burke Peter A | Semiconductor component and method of manufacture |
-
2010
- 2010-10-20 JP JP2010235632A patent/JP5638340B2/ja not_active Expired - Fee Related
-
2011
- 2011-09-24 US US13/244,445 patent/US8643103B2/en active Active
- 2011-10-19 CN CN201110318482.1A patent/CN102456741B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN102456741B (zh) | 2016-03-23 |
CN102456741A (zh) | 2012-05-16 |
US20120098060A1 (en) | 2012-04-26 |
JP2012089701A (ja) | 2012-05-10 |
US8643103B2 (en) | 2014-02-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6320545B2 (ja) | 半導体装置 | |
US8441046B2 (en) | Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances | |
JP5048273B2 (ja) | 絶縁ゲート型半導体装置 | |
JP4935160B2 (ja) | 炭化珪素半導体装置およびその製造方法 | |
JP3721172B2 (ja) | 半導体装置 | |
JP3979258B2 (ja) | Mis半導体装置およびその製造方法 | |
US10686062B2 (en) | Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances | |
JP6415749B2 (ja) | 炭化珪素半導体装置 | |
US8217454B2 (en) | Semiconductor device | |
JP2011171552A (ja) | 半導体装置およびその製造方法 | |
US20140103416A1 (en) | Semiconductor device having esd protection structure and associated method for manufacturing | |
JP2017041573A (ja) | 半導体装置およびその製造方法 | |
KR101450437B1 (ko) | Ldmos 소자와 그 제조 방법 | |
JP5432750B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP5432751B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2011086746A (ja) | 半導体装置 | |
JP4966351B2 (ja) | 半導体装置 | |
JP5638340B2 (ja) | 半導体装置 | |
JP6299658B2 (ja) | 絶縁ゲート型スイッチング素子 | |
JP6173987B2 (ja) | 半導体装置 | |
JP2012204379A (ja) | 電力用半導体装置 | |
US9312331B2 (en) | Semiconductor device | |
JP6362925B2 (ja) | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 | |
JP6368105B2 (ja) | トレンチ型mosfet半導体装置 | |
JP2014060336A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130802 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140616 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140624 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140731 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140930 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141022 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5638340 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |