JP5432750B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 119
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000010410 layer Substances 0.000 claims description 405
- 238000009792 diffusion process Methods 0.000 claims description 132
- 239000002344 surface layer Substances 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 44
- 239000012535 impurity Substances 0.000 claims description 29
- 238000002955 isolation Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 2
- 239000011229 interlayer Substances 0.000 description 14
- 238000000605 extraction Methods 0.000 description 10
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Description
前記第1導電型半導体層の表層に形成され、前記第1導電型半導体層よりも不純物濃度が高い、第1の第1導電型高濃度拡散層と、
前記第1導電型半導体層の表層に形成され、前記第1の第1導電型高濃度拡散層に接している第1の第2導電型高濃度拡散層と、
前記第1導電型半導体層の表層に形成され、前記第1の第2導電型高濃度拡散層より不純物濃度が低い第2導電型低濃度ドリフト層と、
前記第1の第2導電型高濃度拡散層と前記第2導電型低濃度ドリフト層との間の前記第1導電型半導体層の表面と、前記第2導電型低濃度ドリフト層の一部とを覆うように形成されるゲート絶縁膜と、
前記ゲート絶縁膜上に形成されるゲート電極と、
前記第2導電型低濃度ドリフト層の表層に形成される第2の第1導電型高濃度拡散層と、
前記第1導電型半導体層の表層に一部が少なくとも形成され、前記第2導電型低濃度ドリフト層及び前記第2の第1導電型高濃度拡散層のいずれからも離れている第2導電型シンカー層と、
前記第2導電型シンカー層の表層に形成される第2の第2導電型高濃度拡散層と、
前記第1導電型半導体層の上に形成され、前記第2の第1導電型高濃度拡散層と前記第2の第2導電型高濃度拡散層とを接続する配線と、
を備える半導体装置が提供される。
第2導電型低濃度ドリフト層の一部、及び前記第1導電型半導体層のうち前記第2導電型低濃度ドリフト層以外の部分の表層の一部とからなるゲート形成領域に、ゲート絶縁膜及び前記ゲート絶縁膜上に位置するゲート電極を形成する工程と、
平面視でゲート電極を介して前記第2導電型低濃度ドリフト層と対向する前記第1導電型半導体層の表層に、前記第2導電型低濃度ドリフト層より不純物濃度が高い、第1の第2導電型高濃度拡散層を形成する工程と、
前記第1導電型半導体層の表層に、前記第1導電型半導体層より不純物濃度が高い第1の第1導電型高濃度拡散層を、前記第1の第2導電型高濃度拡散層に接して形成する、第1の第1導電型高濃度拡散層形成工程と、
前記第2導電型低濃度ドリフト層の表層に第2の第1導電型高濃度拡散層を形成する工程と、
前記第1導電型半導体層内に第2導電型シンカー層を、前記第2導電型低濃度ドリフト層及び前記第2の第1導電型高濃度拡散層のいずれからも離れている位置に形成する工程と、
前記第2導電型シンカー層の表層に第2の第2導電型高濃度拡散層を形成する工程と、前記第1導電型半導体層上に、前記第2の第2導電型高濃度拡散層と前記第2の第1導電型高濃度拡散層とを接続する配線を形成する工程と、を備える半導体装置の製造方法が提供される。
12 半導体基板
13 絶縁層
14 エピタキシャル層
15 半導体層
16 素子分離絶縁膜
102 第1導電型ウェル
104 第2導電型ドリフト層
105 領域
106 第2導電型エミッタ層
107 第1導電型ウェル引出用拡散層
108 第1導電型コレクタ層
109 シリサイド層
110 ゲート絶縁膜
112 ゲート電極
114 第2導電型埋込層
115 シンカー層
116 第2導電型拡散層
150 第2導電型拡散層
160 第2導電型不純物層
200 層間絶縁膜
211 コンタクト
212 コンタクト
213 コンタクト
214 コンタクト
220 配線
222 配線
224 配線
400 p−基板
410 n+拡散層
412 p+拡散層
414 エミッタ電極
430 n−ドリフト層
432 p+拡散層
433 n+拡散層
434 コレクタ電極
Claims (6)
- 表層に第1導電型半導体層を有する基板と、
前記第1導電型半導体層の表層に形成され、前記第1導電型半導体層よりも不純物濃度が高い、第1の第1導電型高濃度拡散層と、
前記第1導電型半導体層の表層に形成され、前記第1の第1導電型高濃度拡散層に接している第1の第2導電型高濃度拡散層と、
前記第1導電型半導体層の表層に形成され、前記第1の第2導電型高濃度拡散層より不純物濃度が低い第2導電型低濃度ドリフト層と、
前記第1の第2導電型高濃度拡散層と前記第2導電型低濃度ドリフト層との間の前記第1導電型半導体層の表面と、前記第2導電型低濃度ドリフト層の一部とを覆うように形成されるゲート絶縁膜と、
前記ゲート絶縁膜上に形成されるゲート電極と、
前記第2導電型低濃度ドリフト層の表層に形成される第2の第1導電型高濃度拡散層と、
前記第1導電型半導体層の表層に一部が少なくとも形成され、前記第2導電型低濃度ドリフト層及び前記第2の第1導電型高濃度拡散層のいずれからも離れている第2導電型シンカー層と、
前記第2導電型シンカー層の表層に形成される第2の第2導電型高濃度拡散層と、
前記第1導電型半導体層の上に形成され、前記第2の第1導電型高濃度拡散層と前記第2の第2導電型高濃度拡散層とを接続する配線と、
を備え、
前記第2導電型シンカー層は、平面視において前記第2導電型低濃度ドリフト層、前記第1の第2導電型高濃度拡散層、及び前記第1の第1導電型高濃度拡散層を取り囲むように設けられており、
前記第1導電型半導体層は、前記第2導電型シンカー層の内側に位置する部分の不純物濃度が、前記第2導電型シンカー層の外側に位置する部分の不純物濃度より高く、
前記第2導電型シンカー層及び前記第1導電型半導体層それぞれの下に形成され、前記第2導電型シンカー層及び前記第1導電型半導体層それぞれに接している第2導電型埋込層をさらに備え、
前記基板は、
半導体基板と、
前記半導体基板上にエピタキシャル成長したエピタキシャル層と、
を備え、
前記第2導電型埋込層は前記半導体基板から前記エピタキシャル層に渡って形成されている半導体装置。 - 表層に第1導電型半導体層を有する基板と、
前記第1導電型半導体層の表層に形成され、前記第1導電型半導体層よりも不純物濃度が高い、第1の第1導電型高濃度拡散層と、
前記第1導電型半導体層の表層に形成され、前記第1の第1導電型高濃度拡散層に接している第1の第2導電型高濃度拡散層と、
前記第1導電型半導体層の表層に形成され、前記第1の第2導電型高濃度拡散層より不純物濃度が低い第2導電型低濃度ドリフト層と、
前記第1の第2導電型高濃度拡散層と前記第2導電型低濃度ドリフト層との間の前記第1導電型半導体層の表面と、前記第2導電型低濃度ドリフト層の一部とを覆うように形成されるゲート絶縁膜と、
前記ゲート絶縁膜上に形成されるゲート電極と、
前記第2導電型低濃度ドリフト層の表層に形成される第2の第1導電型高濃度拡散層と、
前記第1導電型半導体層の表層に一部が少なくとも形成され、前記第2導電型低濃度ドリフト層及び前記第2の第1導電型高濃度拡散層のいずれからも離れている第2導電型シンカー層と、
前記第2導電型シンカー層の表層に形成される第2の第2導電型高濃度拡散層と、
前記第1導電型半導体層の上に形成され、前記第2の第1導電型高濃度拡散層と前記第2の第2導電型高濃度拡散層とを接続する配線と、
を備え、
前記基板は、半導体基板上に絶縁層及び半導体層をこの順に積層したSOI(Silicon On Insulator)基板であり、
前記第2導電型シンカー層は、深さ方向において前記半導体層内に形成されており、かつ下端が前記絶縁層に達している半導体装置。 - 請求項1又は2に記載の半導体装置において、
前記第1導電型半導体層の表層に形成され、前記第2の第1導電型高濃度拡散層と前記第2の第2導電型高濃度拡散層とを分離するように配置されている素子分離絶縁膜をさらに備える半導体装置。 - 表層に第1導電型半導体層を有する基板に、前記第1導電型半導体層の表層の一部に位置する第2導電型低濃度ドリフト層を形成する工程と、
前記第2導電型低濃度ドリフト層の一部、及び前記第1導電型半導体層のうち前記第2導電型低濃度ドリフト層以外の部分の表層の一部とからなるゲート形成領域に、ゲート絶縁膜及び前記ゲート絶縁膜上に位置するゲート電極を形成する工程と、
平面視で前記ゲート電極を介して前記第2導電型低濃度ドリフト層と対向する前記第1導電型半導体層の表層に、前記第2導電型低濃度ドリフト層より不純物濃度が高い、第1の第2導電型高濃度拡散層を形成する工程と、
前記第1導電型半導体層の表層に、前記第1導電型半導体層より不純物濃度が高い第1の第1導電型高濃度拡散層を、前記第1の第2導電型高濃度拡散層に接して形成する、第1の第1導電型高濃度拡散層形成工程と、
前記第2導電型低濃度ドリフト層の表層に第2の第1導電型高濃度拡散層を形成する工程と、
前記第1導電型半導体層内に第2導電型シンカー層を、前記第2導電型低濃度ドリフト層及び前記第2の第1導電型高濃度拡散層のいずれからも離れている位置に形成する工程と、
前記第2導電型シンカー層の表層に第2の第2導電型高濃度拡散層を形成する工程と、
前記第1導電型半導体層上に、前記第2の第2導電型高濃度拡散層と前記第2の第1導電型高濃度拡散層とを接続する配線を形成する工程と、
を備え、
前記第1の第1導電型高濃度拡散層形成工程と、前記第2の第1導電型高濃度拡散層を形成する工程とを同一工程により行う半導体装置の製造方法。 - 表層に第1導電型半導体層を有する基板に、前記第1導電型半導体層の表層の一部に位置する第2導電型低濃度ドリフト層を形成する工程と、
前記第2導電型低濃度ドリフト層の一部、及び前記第1導電型半導体層のうち前記第2導電型低濃度ドリフト層以外の部分の表層の一部とからなるゲート形成領域に、ゲート絶縁膜及び前記ゲート絶縁膜上に位置するゲート電極を形成する工程と、
平面視で前記ゲート電極を介して前記第2導電型低濃度ドリフト層と対向する前記第1導電型半導体層の表層に、前記第2導電型低濃度ドリフト層より不純物濃度が高い、第1の第2導電型高濃度拡散層を形成する工程と、
前記第1導電型半導体層の表層に、前記第1導電型半導体層より不純物濃度が高い第1の第1導電型高濃度拡散層を、前記第1の第2導電型高濃度拡散層に接して形成する、第1の第1導電型高濃度拡散層形成工程と、
前記第2導電型低濃度ドリフト層の表層に第2の第1導電型高濃度拡散層を形成する工程と、
前記第1導電型半導体層内に第2導電型シンカー層を、前記第2導電型低濃度ドリフト層及び前記第2の第1導電型高濃度拡散層のいずれからも離れている位置に形成する工程と、
前記第2導電型シンカー層の表層に第2の第2導電型高濃度拡散層を形成する工程と、
前記第1導電型半導体層上に、前記第2の第2導電型高濃度拡散層と前記第2の第1導電型高濃度拡散層とを接続する配線を形成する工程と、
を備え、
前記第1の第2導電型高濃度拡散層を形成する工程と、前記第2の第2導電型高濃度拡散層を形成する工程とを同一工程により行う半導体装置の製造方法。 - 請求項4又は5に記載の半導体装置の製造方法において、
前記第1導電型半導体層の表層に、前記第2の第2導電型高濃度拡散層と前記第2の第1導電型高濃度拡散層とを分離するように、素子分離絶縁膜を形成する工程をさらに備える半導体装置の製造方法。
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US7514754B2 (en) * | 2007-01-19 | 2009-04-07 | Episil Technologies Inc. | Complementary metal-oxide-semiconductor transistor for avoiding a latch-up problem |
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US8217452B2 (en) * | 2010-08-05 | 2012-07-10 | Atmel Rousset S.A.S. | Enhanced HVPMOS |
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