JP5887233B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 153
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000012535 impurity Substances 0.000 claims description 119
- 239000000758 substrate Substances 0.000 claims description 95
- 238000002955 isolation Methods 0.000 claims description 56
- 238000000034 method Methods 0.000 claims description 46
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 238000005468 ion implantation Methods 0.000 description 16
- 229910052814 silicon oxide Inorganic materials 0.000 description 16
- 150000002500 ions Chemical class 0.000 description 14
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- 238000009826 distribution Methods 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
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- 230000000052 comparative effect Effects 0.000 description 4
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- 239000011229 interlayer Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- -1 titanium aluminum (TiN) Chemical compound 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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Description
(実施の形態1)
まず図1を用いて一実施の形態の半導体装置の構成について説明する。
図20を参照して、比較例の半導体装置においては図1の一実施の形態と基本的に同様の構成を有するが、p-エピタキシャル領域EPとn-エピタキシャル領域ENとの間の半導体基板SUB内にはn型不純物を有するn+埋め込み領域NBLが形成されている。n+埋め込み領域NBLにおけるn型不純物濃度は、n-エピタキシャル領域ENにおけるn型不純物濃度よりも高い。
図27を参照して、この平面図の分離用溝TRSに囲まれた領域にLDMOSなどの半導体装置が形成されている。そして図27においては分離用溝TRSのLDMOSが配置される側(分離用溝TRSの内側)の側壁、およびLDMOSと反対側(分離用溝TRSの外側)の側壁に溝側壁n型領域NRが形成されている。
まず図29を用いて本実施の形態の半導体装置の構成について説明する。
図31を参照して、一実施の形態のたとえばLDMOSなどの半導体装置は、主表面を有する半導体基板SUB内に形成されたp-エピタキシャル領域EPと、半導体基板SUB内であってp-エピタキシャル領域EPの、半導体基板SUBの主表面側に形成されたn-エピタキシャル領域ENとを有している。また当該半導体装置は、半導体基板SUB内であってn-エピタキシャル領域ENの、半導体基板SUBの主表面側に形成されたn型オフセット領域NOと、n-エピタキシャル領域ENの、半導体基板SUBの主表面側において、n型オフセット領域NOと隣り合いpn接合を構成するように半導体基板SUB内に形成されるp型ボディ領域BOとを有している。当該半導体装置は、p-エピタキシャル領域EPとn-エピタキシャル領域ENとの間の半導体基板SUB内に形成され、かつp-エピタキシャル領域EPよりも高いp型不純物濃度を有するp+埋め込み領域PBLと、n型オフセット領域NOを含むLDMOSの周囲を取り囲むように、半導体基板SUBの主表面からp+埋め込み領域PBLに達するように延在する分離用溝TRSを有している。当該半導体装置は、分離用溝TRSの側壁のうち、LDMOSが形成される側の側壁の少なくとも一部(たとえば図31の下側)に形成された溝側壁n型領域NRを有している。溝側壁n型領域NRにおけるn型不純物濃度はn-エピタキシャル領域ENにおけるn型不純物濃度よりも高い。溝側壁n型領域NRはp+埋め込み領域PBLに達するように分離用溝TRSの側壁に沿って延在する。
Claims (6)
- 主表面を有する半導体基板と、
前記半導体基板内に形成された第1導電型の第1領域と、
前記半導体基板内であって前記第1領域の前記主表面側に形成された第2導電型の第2領域と、
前記半導体基板内であって前記第2領域の前記主表面側に形成される第2導電型の第3領域と、
前記第2領域の前記主表面側において前記第3領域と隣り合いpn接合を構成するように前記半導体基板内に形成される第1導電型の第4領域と、
前記第1領域と前記第2領域との間の前記半導体基板内に形成され、かつ前記第1領域よりも高い第1導電型の不純物濃度を有する第1導電型の埋め込み領域と、
前記第3領域を含む素子領域の周囲を取り囲むように、前記主表面から前記埋め込み領域に達するように延在する分離用溝と、
前記分離用溝の側壁のうち前記素子領域側の前記側壁の少なくとも一部に形成された第2導電型の溝側壁高濃度領域とを備え、
前記溝側壁高濃度領域における第2導電型の不純物濃度は前記第2領域における第2導電型の不純物濃度よりも高く、
前記溝側壁高濃度領域は前記埋め込み領域に達するように前記側壁に沿って延在する、半導体装置。 - 第1導電型はp型であり、第2導電型はn型である、請求項1に記載の半導体装置。
- 前記溝側壁高濃度領域における第2導電型の不純物濃度は、前記埋め込み領域における第1導電型の不純物濃度よりも低い、請求項1に記載の半導体装置。
- 前記分離用溝は、前記主表面から前記埋め込み領域を少なくとも貫通するように延在する、請求項1に記載の半導体装置。
- 主表面を有し、第1導電型の第1領域を有する半導体基板を準備する工程と、
前記半導体基板内の前記第1領域の前記主表面側に、前記第1領域よりも高い第1導電型の不純物濃度を有する第1導電型の埋め込み領域を形成する工程と、
前記半導体基板内の前記第1領域および前記埋め込み領域の前記主表面側に第2導電型の第2領域を形成する工程と、
前記半導体基板内の前記第2領域の前記主表面側に第2導電型の第3領域を形成する工程と、
前記第3領域を含む素子領域の周囲を取り囲むように、前記主表面から前記埋め込み領域に達するように延在する分離用溝を形成する工程と、
前記分離用溝の側壁のうち前記素子領域側の前記側壁の少なくとも一部に第2導電型の溝側壁高濃度領域を形成する工程と、
前記第2領域の前記主表面側において前記第3領域と隣り合いpn接合を構成するように前記半導体基板内に第1導電型の第4領域を形成する工程とを備え、
前記溝側壁高濃度領域における第2導電型の不純物濃度は前記第2領域における第2導電型の不純物濃度よりも高く、
前記溝側壁高濃度領域は前記埋め込み領域に達するように前記側壁に沿って延在する、半導体装置の製造方法。 - 前記溝側壁高濃度領域を形成する工程においては、
前記側壁に対して斜め方向から第2導電型の不純物がイオン注入される、請求項5に記載の半導体装置の製造方法。
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