TWI223361B - Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same - Google Patents
Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same Download PDFInfo
- Publication number
- TWI223361B TWI223361B TW092102710A TW92102710A TWI223361B TW I223361 B TWI223361 B TW I223361B TW 092102710 A TW092102710 A TW 092102710A TW 92102710 A TW92102710 A TW 92102710A TW I223361 B TWI223361 B TW I223361B
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- Prior art keywords
- film
- columnar
- semiconductor device
- columnar protrusion
- pad
- Prior art date
Links
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
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- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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Description
1223361
五、發明說明 一、【發明所屬之技術領域】 本發明係關於一種半導體元件與其製造方法、及半、耸 體裝置與其製造方法，尤其關於一種面向下方安裝的倒^ 晶片型半導體元件之隆起部構造與其製造方法、及里 : 構造與其製造方法。 “了衣 先前技術】 用 兩種類 半導體 片方法 提升半 端子的 腳數傾 裝晶片 件。此 言，首 (C4)之 圖 圖。如 線的電 20經由 料隆起 法、電 於連接半導體元件之電極與外部端子之連接方法 型·使用金屬薄配線之打線接合方法與使用形成於 元件電極上的焊料隆起部之倒裝晶片方法。倒裝曰j =盈於近來的高密度與高插腳數傾向。近年來為= 導體封裝之封裝密度，具有焊料隆起部形成為 球橋陣列型半導體封裝廣泛用來作為可回應於古I 1，技術、，維持大的端子間距。在許多情況中7倒 亦且作為女裝至封裝板（lnterp〇Ser)的半導 種倒获曰μ , 守篮70 曰曰 t連接方法已經開發出許多。舉例而 、奎=^ 一 種稱為Coni:ro1 CoraPs ChiP Connection 連接方法。 3圖=習知倒裝晶片型半導體元件之構造之剖面 ^2與罝^ ’在半導體基板1上形成，連接至内部配 i J、、/、有開口於電極2上的覆蓋膜3。焊料隆起部 父互連接肢4你 部20彤忐、〃、黏附膜5而形成於電極2上。關於焊 紘、凉^你方法’通常係藉由各種方法例如蒸鍵方 解/夜電鑛方、、土 . 去、烊料膠印刷方法、以及焊料球載入
第6頁 1223361 '發明說明（2) __〜 與供應方法來彳i£雍日來、丨〇 m 而形成半球形隆：二： 助熔劑之焊料重熔流佈製程 =顯示習知倒裝晶片型半導體元件 構造之剖面圖。焊料 I 衣日日片封裝 14上，立中預先供應於配線基板（封袭板）12之塾 .0. ^墊4與焊料阻膜1 3形成於表面上。然後， :重位：2 ί ’半導體元件承載於配線基板1 2上。笋由ί +吉1 Ί 70成隆起4 2 0與墊1 4間之連接以形忐吟 Ϊ) , Γ,^ ^ 1 ^ ^ ^ ^ 1 Γ, . Λ ( ； ! 不）由底4充填樹脂（underfiUresin)填滿。、“未圖 於半導：：：η且除了焊料隆起部之外更形成金隆起部 成金法ϊ及藉由電解液金電以 線基板側的金屬膜二：二°此等隆起部黏附於形成於配 焊料。全屬膜例如金電鑛、銀/錫焊料、與銦/锡/錯 樹脂；入於半;:，片士倒，晶片安裝之後藉著底部充填 實行時，最片與配線基板間之縫隙。當樹脂填i 以實行良好的填】晶片與配線基板間之縫隙， =具有大的高度以溶化於電極 隆起部 應增加所供應的焊料欠為+球形’則 間之相鄰的焊料隆起邻之^成八有細微間距的電極 戸弓拓赖為 趣4之短路。因而，變得Μ a P、左从/ 間勢之進展而形成具有高度的焊料隆起c微 然細微間距趨勢造成樹脂流之1:=;。另 真樹月曰之填充困難度會隨著細微間距而增加。 1223361 五、發明說明（3) 藉由蒸鍍方法與焊料膠印刷方法形 ί牵涉到增加製造成本，既然遮罩之耐=料隆起部之方 罩。 不足且需要遮 亦且，焊料球供應方法牽涉到焊 且需要使焊料球對準於所要求的佈局且_ 2相對高成本’ 上之設備。既然晶圓單位中之封裁於半導體晶片 部形成總成本變高。再者，對應二：困難& ’故隆起 徑的烊料球之製造困難。然後，所要^間距之具有更小直 小，生產率愈低，招致高成本。 ，的球尺寸（直徑）愈 料作為更i起上時，且當使用焊 射1件所產生的阿線Λ所含的放 亦且，具有電鍍隆起部盥 &成权錯块。 成金材料之成本高之問題。 了 ^起部。然而，造 造成隆起部之數目愈多， =I形成各個金隆起部， 更且，舍佶用厶带屯成成本愈高之問題。 然金具有良好的可濡性，故焊二/，=枓接面實行時，既 電極與金電鍍間之介面進 &面上往上濡濕且從 最終而剝落，牵涉到可靠度之問題^致"面始、度下降，或 亦且’糟由使用鋼雷推政2 ^ ^ 出來。舉例而言，JP-Α 3二24二=之焊料技術亦且被提議 鑛方法形成銅隆起部之後，來H，露有在藉由電解液電 使得銅隆起部之上半部露/成:醯亞胺膜於半導體板上 於銅隆起部上。然而，:二藉由浸入方法形成焊料膜 田倒叙晶片以此方式塗佈有厚樹脂
1IIHH 第8頁 1223361 五、發明說明（4) :而安凌於配線基板上時，會變得難 2二：外，既然銅隆起部與聚醯亞 非對於銅隆起部側實行特殊處理，Ϊ 電極。因此類似於金隆起部之情況發 以藉著底部充填樹脂 胺膜之黏附性低， 料容！濡濕、，擴展至 生可靠度之問題。 三、【發明内 本發明之 片與基板間之 本發明之 片之隆起部構 本發明之 度下降例如軟 依據本發 容】 目的在於即 完全距離。 使電極具有細微間距仍然保有 另一目的在於提供可用低成本製造的倒 B曰 起部且 該柱狀 之上部 亦 突出部 形成於 側表面 亦 步驟： 形 部分上 經由一 突出部 塗佈有 且，依 ，作為 造 又一目的在於提供一封 錯誤或墊剝落之機率很 明之半導體 交互連接膜 之上表面或該柱狀突出 極佳可濡性 據本發明另 元件包含一 或一黏附膜 隆起部且 一電極上。一防濕 该電極之* 的一蓋膜。 一態樣之半 經由一交互 裝 曰曰 裝構造’其造成可靠 低。 fe狀突出部，作為隆 而形成於一電極上。 部之上表面與側表面 導體元件包含一柱狀 連接膜或一黏附膜而 於該枉狀突出部之該 膜至少形成 中罪近该電極之"部分。 且，依據本發明之半導體元件之製造方法包含下列 成一金屬膜於一半導體基板之形成有一電極的整個 ，作為一電鍍電極；
第9頁 !223361 、發明說明（5) 形 極之位 藉 成一杈 移 藉 屬膜； 形 亦 含下列 形 一電極 藉 移 藉 柱狀突 移 形 成一阻膜於該金屬膜上，該 置處； 由電解 狀突出 除該阻 由使用 —開口於該電 液電鍍沉積 部； 膜； 該柱狀突出 咼導電性金屬成為柱狀，以形 以及 成一防濕膜於該柱 且，依據本發明另 步驟： 成一阻膜於一半導 膜具有一^開 處理而形成 膜上之該活 電鍍沉積高 ，該阻 由活化 除該阻 由無電 出部； 部作為-遮罩而餘刻以移除該金 狀突出部之表面上。 一態樣半導冑元件之製造方法包 體基板上’該半導體基板上具有 口於該電極之位置處； 活化處理層，用於無電電鍍； 化層； V電i屬於該開口中，以形成一 除該阻膜；以及 成一防濕膜於該柱 明之半導體 依據本發 成於一半導體元件之一電 柱狀突 墊。該 膜。 亦 電柱狀 狀突出部之表面上。 裝置包含：一導電柱狀突出部形 極上且焊接至一配線基板上之一 出部之側表面之至少—部分塗佈有一防濕 且，依 突出部 據本發明另 形成於一半 怨樣之半導體裝置包含：一導 體元件之一電極上且焊接至一 1223361
出部之該焊接部分係限制 配線基板之一 於該柱狀突出 亦且，依 電柱狀突出部 配線基板之一 濡性且難以氧 之上表面或該 亦且，依 電柱狀突出部 線基板上之一 之一墊之表面 金屬膜而連結 墊。該導電柱狀突 部之上表面。 據本發明另 形成於一半 墊。該柱狀 導體元 突出部 化的一金屬膜所形 一態樣之半導 柱狀突出部 據本發明另 形成於一半 墊。該柱狀 係經由具有 之側表 件之一 係烊接 成，形 面之上 一態樣之半導 導體元 突出部 極佳焊 件之一 之一上 體裝置包含：一導 電極上且焊接至一 由具有極佳焊接可 成於該柱狀突出部 部或上表面上。 體裝置包含：一導 電極且連接至一配 表面與該配線基板
接可濡性且難以氧化的一 亦且’依據本發明之半導體裝置之製造方法包含下列 步驟： 供應具有助熔劑活性效應的熱固性樹脂至一柱狀突出 4之頂端部或焊接至其上的一配線基板之一塾，該柱狀突 出部係形成於一半導體元件之一電極上； 對準該柱狀突出部與該配線基板之供應有一預定量的 焊料之該墊；以及 加熱並焊接僅該柱狀突出部之頂端部至該配線基板之 該墊。 依據本發明另一態樣之半導體裝置之製造方法包含下 列步驟： 供應助熔劑至一柱狀突出部之一頂端部或應焊接至其
第11頁 1223361 五、發明說明（7) 上的一 元件之 對 焊料之 加 上之該 清 亦 包含下 供 出部之 對 部係形 其之該 加 之該塾 亦 包含下 供 對 部係形 之頂端 加 —墊； 配線基板之一墊，該柱狀突出部係形成於一半導體 電極上； 狀突出部與該 準該柱 該墊； 熱並焊 墊；以 潔並移 且，依 列步驟 板 一預定量的 接僅該柱狀突出部之该頂端部至該配線基板 及 除該助熔劑。 據本發明另一態樣之半導體裝置之製造方法 效應的一熱固性樹脂至一柱狀突 其上的一配線基板之一塾； 該配線基板之該墊，該柱狀突出 上之一電極上且具有一焊料膜於 ;以及 接僅該柱狀突出部之該頂端部至該配線基板 應具有助熔劑活性 一頂端部或焊接至 準該柱狀突出部與 成於一半導體元件 頂端部 熱並焊 且，依據本發明另一態樣之半導體裝置之製造方法 列步驟： 應一助 準一柱 成於一 溶劑於一配線基板之一墊上； 該配線基板之該墊，該柱狀突出 之一電極上且具有一焊料膜於其 狀突出部與 半導體元件 部； 熱並焊接僅該柱狀突出部之頂端部至該配線基板 以及 之
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Jr 1 ' 1 - ------------- - _ 、赘明說明（8) 清潔並移除該助熔劑。 亦且，依據本發明另一態樣之半導體裝置之製造方法 包含下列步驟： 、 _ 藉由電漿所激發的一非活性氣體之物理性衝擊而清潔 ^狀突出部之頂表面與一配線基板上之一墊表面，該柱 欠次出部係形成於一半導體元件之一電極上； 對準該柱狀突出部與該配線基板之該墊；以及 灸 施壓於该半導體元件與該配線基板以黏附該柱狀突出 $與該墊。 導體 金隆 ，在 墊係 此外 狀隆 表面 溫度 其不 ，當 維持 間之 充填 著較 半導 同於焊 習知連 I起部 由埤料 由埤料 I起部 起部係 等所形 對高的 柱狀隆 線基板 裝晶片 實行。 間距曰T 本發明 料彼此 接糸統 與配線 而直接 而完成 之上表 使用不 成，並 隆起部 起部不 與半導 連接後 亦即， 之焊料 連接或 。然而 基板之 連接。 時，柱 面或上 於焊接 且既然 。再者 熔化且 體晶片 之底部 關於隨 連接， 元件與 起部與 本發明 經由少 ，在本 起部與 與側表 熔化的 因重容 半導體 於起初 距離可 樹脂填 小直經 體晶片 配線基 配線基 中，半 量的焊 發明中 焊料之 面之僅 金屬由 流佈而 晶片承 形成時 完全確 充性更 尺寸的 與配線 板間之連 板側之焊 導體元件 料而連接 ，甚至當 接觸係限 一小部分 電解液電 變彎，故 載於配線 的形式。 保。此更 容易且高 隆起部而 基板之縫 側之柱壯 ’或不經 連接係藉 制於柱狀 。杈狀（1 链方法等 了办成和 基板時， 此允許酸 &許在隹, 度可靠地 4有細德 隙降低，
ψ3361 五、發明說明（9) 並且顯著改良可加工性與可靠度。 或單位。亦且此為使用電解液電鐘方法 藉而，可用比習知徵’舉例而言。 且，在使用且右助卜2 應 更低的成本製造。亦 而用於當封裝於半導體曰片之晰始性树月曰取代助熔剤 表面上之氧 ：片之配線基板上時移除隆起部之 製程降低ίίϊί 可刪除清潔製程。㈣成清潔 靠度之改良,牛&成本或無清潔殘留物。所以，獲得可 功能：：的降低或刪除所用的焊料量，"使造成 度之：良的阿法劑量降低或歸零。㈣成可靠 ^且依據本發明，焊料於封裝時不會往上濡篇遠達 隆起部之柱根部。可防七惊祖、隹λ上 ㈢^上属濕逖運 ^ Fii ^ / 1¾^ ip ； 父互連接膜/黏附膜或 gj/。隆起部之介面而造成介面剝落，且可專注於改良 之侧=當i妾面之形成係焊料往上厲濕遠達柱狀隆起部 分散且提升接面部；觸表面面積變寬時，壓力會 在本發明之半導體裝置製造方 膜形成於柱狀隆起部之匕丰η使μ I 1膜或知枓電鍍 八m & 忽丨之上表面或其上表面或側表面之一部 :敕個上定地形成接面，其中焊料可覆蓋柱狀隆起部 i個上表面，或焊料可覆蓋整個上端部。藉而，可防止
I 第14頁 1223361
柱狀隆起部j黏附膜間之接面強度下 成 且可獲得可靠接面部 四、【實施方式】 下文將ί 圖示說明本發明之較佳實施例。圖1 依據本發明之半導辦开杜夕# . ”、、'、
體兀件之弟一實施例之。彳面圖。如圖J 不 Y ^體基板1上形成一電極2，連接至内部電路。 4 上經由例如鈦（τ i)與銅（Cu )所組成的黏附膜 4與黏附膜5而形成由例如銅所組成的柱狀隆起部6。防止膜 焊料黏附與往上漂濕的防濕膜7形成於柱狀隆起部6之 面上。柱狀隆起部6得傕用钯 _ θ . ]表 金所形成。 <于使用鋼合金、或不是銅的鎳與錦合 圖2顯示本發明之半導體元件之第二實施例 圖政在圖2中，相同於圖i之部份使用之。 同於圖1所示的第一實施例之處在於 ):不 :止柱狀隆起部6氧化且由金(Au) 有=，用以 濡濕的領域。 Λ 坪接蚪界定 圖3顯示本發明之半導體元件之第二每> 圖。本發明不同於圖i所示的第一每二貫施例之剖面 形成於柱狀隆起部6之上表面或側表面J <爽在於一蓋膜8 金（A u )所組成用以防止柱狀隆起部6 ^ ^刀上’其由 濡濕的區域，並且防濕膜7從其上带=化且於烊接時界定 、有盍膜8的检狀隆起
1223361 五、發明說明（Η) 部6之側表面部移除。 關於第二與第三每# 狀隆起部之極高可；;生：二當蓋膜8係使用具有對於柱 再者，蓋膜得使用稱為=戶=成日夺，可省略防濕膜。 形成，其於焊接時藉由劑塗佈材料之樹脂材料所 圖4顯示本發明之半助導私/，：化’取代金屬蓋膜。 圖。此者施例不π θ ¥體兀件之第四實施例之剖面 此貝施例不同於圖i所示的第一垂 鍍層9形成於柱狀隆起部6之上)表弟面上幾細例之處在於一電 圖5 一顯示本發明之半導體元件之第五實施例之剖面 圖。此貫施例不同於圖1戶彳+ Μ ^ — 鍍膜9形成於柱狀隆起部/之不上的/面7=列之處在於一電 且防濕膜7從其上形成有焊料電；3貝:：面之部分上’ 部移除。 战有烊枓電鍍膜9的柱狀隆起部6之側 圖6^1 頁示本發明之半導體元件之第六實施例之剖面 貫施料㈣圖4戶斤示的第四實施例之處在於一薄 金層10形成於焊料電鍍層9之上表面上。 圖7顯示本發明之半導體元件之第七實施例之剖面 圖。此實施例不同於圖5所示的第五實施例之處在於一 金膜10形成於焊料電鍍膜9之上表面或侧表面上。 圖8A至8E依序顯示本發明之半導體元件之製造方法之 剖面圖。如圖8A所示，電極2與半導體基板}之^蓋膜^之 正表面藉由濺鍍方法等等而塗佈有一交互連接膜4與、一黏 附膜5。交互連接膜4最好係由鈦所形成。然而，除了鈦或 多重層以外’得使用含有欽合金的單一層例如氮化鈦、鈦
1223361 五、發明說明（12) /鎢合金，與含有鉻的單一層、鉻/銅合金、 替。黏附膜5最好由鋼所形成。然而若或夕重層代 形成的柱狀隆起部（鋼電鍍膜等等）之 /於由非銅所 於小金屬範圍，則不限制組成物質。4 金且阻膜位 接著，如圖8B所示，使用光阻 ，其厚度超過應形成且具有一開口 電鍵阻膜 之高度。藉由使電解液進入遮罩而實行解2上的隆起部 成柱狀隆起部6。 液電錄’且形 接著，如圖8C所示，藉由灰化等等 士使用柱狀隆起部6作為遮罩而 交互連接膜4。 山w拓附膜5與 繼而，如圖8D所示，於氧化環境實行 防濕膜7於柱狀隆起部6之表面上。 以獲侍 接著，如圖8E所示，在暴露至非活性氣體例如氮（ 之電漿後，僅移除柱狀隆起部6之上表面之防濕膜。 為了取代將不需要的防濕膜暴露至非活性氣體之電漿 而移除之方法，在藉由遮罩覆蓋不需形成防濕膜之部分^ 後，實行氧化處理，且隨後得移除遮罩。防濕膜7得由藉 由膜形成技術例如電漿CVD方法所沉積的氧化矽膜或氮化 矽膜等等所形成。亦且在此例子中，在防濕膜預先形成之 後’不品要的防濕膜暴詻至非活性氣體之電漿而移除。或 者在不需形成防濕膜之部分由遮罩所覆蓋後，形成該膜， 且隨後得移除遮罩。在防濕膜7係藉由膜形成技術例如CVD 方法而形成之情況中，於交互連接膜4與膜5之側表面上獲
第17頁 1223361 五、發明說明（13) · 得膜厚度幾乎等於柱狀隆起部6之側表面的防濕膜7。 _ « 圖9A至9E依序顯示本發明之半導體元件之製造方法之 第二實施例之剖面圖。在此實施例中，直到圖9 B所示的製 程皆相同於第一實施例。 · 然後，如圖9C所示，藉由電解液電鍍方法或無電電鍍 方法形成蓋膜8於柱狀隆起部6之上表面上。如圖9D所示， 電鍍阻膜19與下方的黏附膜4與交互連接膜5被移除。然 後’藉由在氧化環境中的熱處理形成防濕膜7於柱狀隆起 部6之側表面上。 圖10A至1 OF依序顯示本發明之半導體元件之製造方法b 之第三實施例之剖面圖。在此實施例中，直到圖1 〇 B所示 的製程皆相同於第一實施例。然後，半蝕刻實行於電鍍阻 膜1 9，且柱狀隆起部6側之一部分露出如圖1 0C所示。 繼而，藉由電解液電鍍方法或無電電鍍方法形成蓋膜 8於柱狀隆起部6之上表面或上側上，如圖1 〇 D所示。在移 除電鍍阻膜1 9與下方的交互連接膜4與黏附膜5之後，藉由 氧化環境中的熱處理而形成防濕膜7於柱狀隆起部6之側表 面上，如圖1 OF所示。 參照第二與第三實施例，防濕膜7可藉由使用膜形成 技術例如電漿CV D方法而形成。在那種情況下，在使用遮 f 罩覆蓋不形成膜的領域之後，該膜可形成。其他實施例亦 同。 在第二與第三實施例中，金係最佳的蓋膜8之材料。 然而，任何具有極佳焊料可濡性且可防止柱狀隆起部氧化
第18頁 1223361 五、發明說明（Η) 之材料皆可使用。舉例而言，例如金合金、錫、銦、或鈀 皆可使用。 圖11Α至11Ε依序顯示本發明之半導體元件之製造方法 之第四實施例之剖面圖。在此實施例中，直到圖11 Β所示 的製程皆相同於第一實施例。藉由電解液電鍍方法形成焊 料電鍍膜9於柱狀隆起部6之上表面上[圖11C]。接著，電 鍍阻膜19與下方的交互連接膜4與黏附膜5被移除[圖 11 D ]。然後’在受到氧化環境中之熱處理以形成防濕膜7
於柱狀隆起部6之表面上之後，進行焊料電鍍膜9上的氧化 膜之漱鍍移除[圖1 1Ε]。 圖12Α至12F剖面圖依序顯示本發明之半導體元件之* =去之第五實施例。除了在形成焊料電鍍‘ 刻製程以外（圖1 2 C )，Jf每a , 卞棘 施例。 此只知例相同於圖11所示的第四實 在 熔合金 焊料材 四與第 電解液 上，如 隆 互連接 一開口 行活化 弟四與第 而形成， 料。亦且 五實施例 或無電電 圖6與圖7 起部得藉 膜與黏附 於隆起部 處理，移 但不限於 ，最好採 中，在形 鍍。金屬 所示。 由無電電 膜圖案化 形成部分 除不需要 坪料電鍍膜9 此而得使用任何可用的材料作為 用未含有鉛的焊料。再者，在第 成埤料電鍍膜9之後，繼續實行 與得薄薄地形成於焊料電鍍膜9 $方法而形成。在此情況中，交 上圖9 A所示的狀態，以形成具有 之卩且膜。然後，藉由例如鋅每 丁貝 咕性層，在阻膜移除之前，實
1223361 五、發明說明（15) 行例如鎳之無電電鍍以开彡# 電極上而不用形成交互、j 5七。隆起部得直接形成於 /从又互連接膜與 圖13顯示本發明之半 附膜 圖。依據本發明之半導辦开置之第一實施例之剖面 墊1 4與焊料阻膜1 3形成於矣7载於配線基板1 2上，其中 元件之柱狀隆起部6藉由僅;^ °在此實施例巾’半導體 連結於配線基板12上之熱= t表面上的焊料填角11而 之電極2之對面側稱為上表面）/ 5兄明書中，柱狀隆起部 圖14係本發明之半導體裝置無 此實施例不同於圖丨3所示的第—给二;;貝=例之剖面圖。 形成於柱狀隆起部6之上表面上/也例之處在於一蓋膜8 圖1 5係本發明之半導體裝置之 ♦ 此實施例不同於圖13所示的第一實：：：：之剖面圖。 件之柱狀.隆起部6連結至不僅位於上"处在於半導體元 表面之一部分上的焊料填角丨丨。 亦且位於其側 圖16顯示本發明之半導體裝置 > 圖。此實施例不同於圖1 5所示的第二與二施例之剖面 膜8形成於半導體元件之柱狀隆起 又處在於一盍 面之一部分。 。之上表面上或其側表 圖17顯示本發明之半導體袭置之第五每^ 圖。在此實施例中，半導體元件之柱狀隆二例之剖面 於配線基板1 2上之墊14，不經由埤料之幫助 1接連結 圖1 8顯示本發明之半導體裝置之第六命: 圖。在此實施例中，半導體元件之柱狀^ =例之剖面 、4 6經由蓋膜8
^3361 五、發明說明（16) 而連接於配線基板1 2上之墊1 4。 々圖ljA至19C依序顯示本發明之半導體裝置之製造方法 之第一貫施例之剖面圖。此實施例係關於圖1所示的半導 體π件之封裝方法。助熔劑15供應至半導體元件之柱狀隆 起部6之頂端部。此外，焊料膜16預先形成於配線基板工2 ，墊14上，如圖19Α所示。在對準半導體元件使得柱狀隆 起部6,得位於墊14上之後，半導體元件承載於配線基板^ ^，受到焊料重熔流佈製程，且柱狀隆起部6經由焊 巧連結於墊14，如圖19B所示 '㈣，在藉著底部充填
对脂17填充並硬化之前，清潔並移除助熔劑15，如/ 所示。 ㈡i y L 知料膜1 6得為焊料膠層，或得為焊料重流 用錫/錯共溶焊料作為焊料膜16，但不限於此匕。層更最好名 錫/鉛（非共熔）、錫/銀、錫/銅、錫/辞、以及其 用 件加入此等材料中的合金。 /、額外i 在此實施例中，助熔劑丨5施加至柱狀隆起部6 面。或者，助炼劑1 5得施加至焊料膜1 6或塾1 4上。側表 其他實施例。亦且，在此實施例之焊接製程中，相，方
預定的壓力將半導體元件壓至配線基板側表面。拉好藉d 避免壓縮構造。 積而 圖20A至20C依序顯示本發明之半導體裝置之制& 之第二實施例之剖面圖。此實施例係關於一種封=造方法 用於圖2所示的半導體元件。不同於圖19所示的第、一方^， 例之處在於一蓋膜8形成於柱狀隆起部6之上表 n施 上。附帶
1223361 五、發明說明（17) 了提，當蓋係形成有熔化於薄金（或金合金） 膜或助熔劑時，既然蓋膜8於焊接時熔化於焊料、、刼脂 中，故此蓋膜8在焊料重溶流佈冑f呈 消^助熔劑 20B，與20C，所示。 现/月天，如圖 —圖2」A至21C依序顯示本發明之半導體裝置 之弟三貫施例之剖面圖。此實施例係關於 法 用於圖4所示的半導體元件。㈣劑_加至僅^衣方法，
上形”焊料電鍍膜9的柱狀隆起部6之頂端部，、= 所示，在對準之後半導體元件承載於 】2U 重溶流佈製程產生焊料填角n，如圖2 且焊料 相同於圖1 9所示的第一實施例。 俊，處理 夕笛圖2Ή2€依序顯示本發明之半導體裝置之製造方本 之弟四貫鈿例之剖面圖。此實施例係關於 =法 用於圖1所示的半導體元件。不同於圖19所示的第—方Λ， ，，處在於使用具有助熔劑活性效應的熱固性樹脂（4 = 稱為活性樹脂）於焊接，而取代助熔劑。亦即，活 $ 2供應至半導體元件之柱狀隆起部6之頂端部，更且‘ 膜16預先形成於配線基板12之墊“上，如圖22a所示” 對準之後，半導體元件承載於配線基板丨2上， 2炼流佈製程，且柱狀隆起部6經由焊料填角 墊u ’如圖22B所示，錢藉著底部充填樹脂17填^ = 化，留下活性樹脂18，如圖22C所示。 W更 在此實施例中，活性樹脂18施加至柱狀隆起部6之 表面。然而，亦得施加至焊料膜丨6或墊丨4上。相同於其他 ΙϋΗ 第22頁 1223361 、發明說明（18) 實施例。 圖23A至23C依序顯示本發明之半導體 之第五實施例之剖面圖。此實施例係關於_:種^ ^方法 用於圖2所示的半導體元件。不同於圖2〇所示的’衣方^去， 例之處僅在於藉由使用活性樹脂18之焊接，因乐、—貫施 說明。附帶一提，當蓋膜8係由薄金膜（或金合^略詳細 於助溶劑中的樹脂膜所形成時，蓋膜 、务)^溶解 於焊料或活性樹脂中。目此，在焊料重炼；^；化時^化 後，如圖23B，與23C，所示，蓋膜8消失。 、私元成之 圖24A至24C依序顯示本發明之半導體裝置 之第六實施例之剖面圖。此實施例係關於一種封ί 法 用於圖4所示的半導體元件。此實施例不同於圖21所方法， 第三實施例之處僅在於藉由使用活性樹脂18取代^ 焊接。因而，省略詳細說明。 代助熔劑之 本圖25A至25C顯示本發明之半導體裝置之製造方从 =貝&列之剖面圖。此實施例係關於一種 ： ==的半導體元件。助炼齊"5施加於其上表面去用於 :i: Γ:上形成有蓋膜8的柱狀隆起部6之頂端部、，Λ ί製：導Lrn:;:;線基板12上，且受到重心λ 成遠達柱狀隆起部6\/σΛ 往上潘濕以允許填角11形 填樹脂17填充並Γ化二表 '，圖25Β所示。在藉著底部充 25C所示。附帶一提^並移除助溶劑15 ’如圖 ^ 长，當盍膜8係形成有熔化於薄金（或金
1223361 五、發明說明（19) B i )膜中之樹脂膜或助熔劑時，既麸 失，如圖25B，與25C，所示。 师衣％ %成之後扁 圖26A至2 6C依序顯示本發明之丰 之第八實施例之剖面圖。此實施例於、置之製造方法 用於圖5所示的半導體元件Λ/^了關;^種封裝方法， 柱狀隆起部6之側表面之一部分:以了烊料電鍍膜形成於 圖2!所示的第三實施例，故省略詳細說：實施例相同於 圖27Δ至27C依序顯示本發明之半導— 例之剖面圖。此實施例係關於 ：件：苐九實施 示的半導體元件。此實施例不同於圖^^^法，用於圖3所 之處僅在於藉由使用活性樹脂18取=2助=的第七實施例 省略詳細說明。附帶-提劑之焊接’因而 (或金合金）膜或助炼劑中之樹脂膜時成缺有==$ 完成之後消失，如圖27Β，與27C，所示。 歇布1輊 ★圖2—8Α至28C依序顯示本發明之半導體裝置之製 之第十實施例之剖面圖。此實施例係關於一 ^ / ；t ° ^ ^^«26 弟八貝鉍例之處僅在於糟由使用活性樹脂18取 焊接，因而省略詳細說明。 助広d之 在第七實施例至第十-實施例中，為了獲得焊料往上 濡濕至柱狀隆起部側之部分而形成填角，亦即此每 特徵構造，最好參照助溶劑或活性樹脂之氧化膜
第24頁 1223361 發明說明（20) 供應量而進行必要的調整。 圖29Δ至29C依序顯示本發明之半導體 :第十-實施例之剖面圖。在此實施二;；法 件之柱狀隆起部6之上表面或侧面之上部塗立兀 其由於焊接時炼化於助炼劑中之樹 有盍膜8 ’ ^^ ^^ ^ ^ t ^ 2丄助熔劑預先施加於形成配線基板12 ;焊； =6卢，如圖29Α所示。在對準半導體元件 上的坏枓 1传位於墊14上之後，倘若半導體元件承已 部6之接面部ΛΠ 則蓋膜8’溶化、柱狀隆起 29Β所示。狹；路：2柱狀隆起部6焊接至塾“，如圖 前，清嘴#，銘t在精者底部充填樹脂17填充並硬化之 月，糸^移除助熔劑1 5，如圖29C所示。 外亦ϊϊ力貝ΪΓ中’助炫劑15施加至焊料膜16。然而，另 助I】 。；，起部6之側表面。亦且，得使用具有 了用^活性樹脂取代助熔劑。 樹脂Ϊ ί it I Ϊ例至第十一實施例中’參照助熔劑或活性 料往上、'需篇Ϊ 除力與供應量，必須適當地調整以獲得焊 為此實施；ί2狀隆起部側之一部分而形成填角，其 法中為了從^ 亦即’在本發明之半導體裝置製造方 足夠的氧化膜而的接面形成，重要者為當活性樹脂具有 量。倘若& 、移除力時’是否藉由助嫁劑供應了適當的 部之不:i t*膜移除力太強’焊料往上濡濕遠達柱狀隆起 人广、濕的根部且造成焊料包裹住柱狀隆起部之形
第25頁 1223361 五、發明說明（21) 式。然後，焊料進入柱狀隆起部與黏附膜間 j f接膜間之可能性上彳，降低黏附強度，且導剝；交 亦且’倘若氧化膜移除力太弱，則穩定的 。 現於焊料與銅隆起部間之介面，導致連接變差:法實 =選擇具有適當的氧化膜移除力之：桝重 且均勻地供應適當的量。 d A活〖生枒脂 然而，在本發明之半導體元件 ，脂並非必[且當接面介面與焊面 =%，半導體7G件之焊接亦可不使用此等物品。下j凊 二與第十三實施例係關於一種焊接方 1弟十 活性樹脂。 坪接方法，不使用助熔劑或 :30A至30C依序顯示纟發明之半導體裝置之 J弟：二實施例之剖面圖。此實施例係關 封：法 法，用於圖7所示的半導體元件。在此實施例中/裝#方 膜1〇形成於設於柱狀突出部6之上部 ^金 面上，金膜i。亦形成於墊14上，如圖3〇〇斤』電= 之表 此等金膜’焊料電鍍膜9與塾“之表面保持於“化3 淨狀。㈣準半導體元件使得柱狀隆起部6得 乾 上之後，倘若半導體元件承載於配線基板12上且為、 重熔流佈製程，則金膜i 0熔化於焊 ^ ^干枓 :=r結於墊14，如_所二⑵ 充填樹月曰1 7填充且硬化，如圖3 0 c所示。 & 4 在，實施例中，金膜10形成於焊 者上。然而，僅其中之一亦足夠。在此情況中，-系列兩儲
第26頁 1223361 五、發明說明（22) 存、傳輸、與封裝製程貫行於非氧化環境中，例如真空與 低壓環境。藉而’重要的是不污染接面部表面。八八 圖31A至31C依序顯示本發明之半導體裝置之製造方法 之第十三實施例之剖面圖。本發明之實施例之半導體元件 =柱狀隆起部6之頂表面與側面之上部藉由薄金膜丨〇所覆 蓋。金膜10亦形成於墊14之焊料膜表面16上，如圖31八所 示二在對準之後，半導體元件承載於配線基板12上且受到 焊料重溶流佈製程，金膜1 〇溶化於焊料中且柱狀隆起部6 經由焊料填角11連結至墊丨4，如圖3丨B所示，然後藉著底 部充填樹脂1 7填充且硬化，如圖3 1 ◦所示。 此實施例係關於一種封裝方法，用於圖7所示的半導 件。在此實施例中，雖然金膜10形成於設於柱狀突出 =之上部分的焊料電_9之表面上，但金賴亦形成: 盥埶力’ ί圖3〇八所不。11由形成此等金膜，焊料電鍍膜9 Ϊ塾14之表面保持於不氧化之清潔狀態。在對準半導體』 件使得柱狀隆起部6得位於墊14 f旱 承載於配線基板12上且成丨丨| 灼右千¥體兀件 化於焊料中且柱狀隆起；炫流佈製程’金膜10炫 如關請示，然後辨著^經由焊料填角11連結於塾’ 圖30C所示。 糟考底部充填樹脂17填充並硬化，如 圖32Α至32C依序_ — 1 之第十四實施例之剖半導體裝置之製造方法 暴露於非活性氣體之電I。半導體疋件與配線基板之表面 柱狀隆起部6之接面側产水如環境中，例如氬氣，且使塾U與 /与/糸’如圖3 2 A所示。對準之後，半
1223361 五、發明說明（23) 導體元件承載於配線基板1 2上並受壓，且藉由壓力使柱狀 隆起部6頂端部黏附至墊1 4，如圖3 2 B所示。此時，得使用 加熱或超音波其中之一’或兩者一起使用。然後，底部充 填樹脂1 7灌入並硬化，如圖32C所示。 圖33A至33C依序顯示本發明之半導體裝置之製造方法 之第十五實施例之剖面圖。在此實施例中，由金等等所組 成的盍膜8預先形成於配線基板之塾1 4上。此實施例不同 於圖32所示的第十一實施例之處僅在於蓋膜8形成於墊14 上，因而省略詳細說明。 在此貝施例中，蓋膜8僅形成於配線基板之墊側中， j 然而蓋膜可僅形成於柱狀隆起部側。亦且，如同第十一實 施例與第十二實施例，當蓋膜並未形成於至少一接面側表 面上日^，可更谷易在真空或非氧化環境中實行接面。亦 即’最好從清潔處理起即維持環境於真空或非氧化環境狀 態中直到接面藉由電漿實行。 々圖34A至34C依序顯示本發明之半導體裝置之製造方法 之第1六^施例之剖面圖。在此實施例中，對於半導體元 件而言，蓋膜8形成柱狀隆起部6之上表面上，且蓋膜8亦 預，準備^配線基板之塾i 4上。此實施例不同於圖3 2所示 的第十貝施例之處僅在於一蓋膜8形成柱狀隆起部6或墊〇 1 4上，因而省略詳細說明。（參昭 本發明之例子 [例子1 ] 參恥本發明之例子1，茲將參照圖9Α至9Ε說明半導體
1223361 五、發明說明（24) 元件之製造方法。 首先，氧化石夕膜之覆蓋膜3形成於半導體基板1上所妒 成的铭合金之配線層上，且移除形成於配線層頂端部之“ 極2上之覆蓋膜。接著，鈦作為交互連接膜4且銅膜作 = 附膜5藉由錢鏡依序形成於整個表面上。覆蓋膜3之严;1、 4·5 、父互連接膜之厚度為60 nm、且黏附膜之厚声2 500 nm。接著，電鍍阻膜19形成且藉由電解液電鍍=== 作為柱狀隆起部6。此時，柱狀隆起部之尺寸係直徑約為^ 140 //m且南度約為90 gm。繼而，實行金電鑛且厚度二 為0·1 的蓋膜8形成於柱狀隆起部上表面上。在* 膜剝落之後，銅隆起部作為遮罩，藉由濕 除又： 附膜與交互連接膜之不需要部分。然後在受到氧化产二， 之熱處理後，防濕膜7形成於柱狀隆起部侧上 ：兄中 =部之形成完成。防濕膜7得於電鍍阻膜剝落之後“ 接著’茲將參照圖2〇說明一種封裝 柱狀隆起部之半導體元件之配線基板。首先，棬ί铜 光滑且平坦的板例如玻掖姑μ认二百无精由擠出至 ^ ^ _ 坡璃板上，均勻地施加助熔劑15 $ μ 度約為40 /zm。然後，纟隆 屻塔415至厚 端。用於使助熔劑轉移推入使助炫劑轉移至頂 助溶劑於一插腳；轉===插腳轉移方法，其轉移 部之頂端的範圍内。= = 供應至銅隆起 錫/鉛共熔合金焊料膠藉由印刷於曰曰女#於配線基板上。 線基板。然後在焊料重程之，而預先供應至配 蝽L怖衣轾之後，以平行於板表面 第29頁 1223361
來推送板且焊 對準半導體元 後，半導體元 佈製程且同時 線基板之塾1 4 焊料可濡性良 然防濕膜形成 起部之上表面 霜濕遠達柱狀 之部分，導致 結部。此貢獻 助炼劑1 5之後 充且硬化之後 在倒裝晶片安 板，且先熔化 料膠之情況下 [例子2] 分被壓擠， 柱狀隆起部 於配線基板 半導體元件 半導體元件 膜僅形成於 面上，焊料 塾。亦即， 與黏附膜間 度下降，也 可靠度的構 面灌入底部 體元件之封 線基板上之 凝固。然而 連結倒裝晶 件使得 件承載 施壓於 。關於 好的蓋 於側表 連結至 隆起部 接面強 出具有 ’從側 ，半導 裝於配 然後再 承載並
使得高度均勻。接著，在 得位於配線基板之墊上之 上。然後藉著焊料重熔流 ’柱狀隆起部6連接至配 與配線基板之接面形成， 柱狀隆起部上表面上。既 不會繞至側面且僅柱狀隆 焊料不會往柱狀隆起部上 或黏附膜與交互連接膜間 不會構成被壓縮的壓力集 造。接著，在清潔並移除 充填樹脂1 7。然後，在填 裝完成。在此實施例中， 前，焊料膠供應至配線基 ，亦可在不熔化並凝固焊 片0 制關於本發明之第二例子，茲參照圖丨〇說明半導體元件 =製造方法。以類似於第一實施例之方式，如圖丨〇 B所 不’電極2上形成厚度6〇 nm之交互連接膜與厚度5〇〇 ηιη之 ^占，膜’以及直杈約為丨4 〇从m且高度為9 〇 # ^的柱狀隆 :邛6，然後藉由氧氣電漿對電鍍阻膜丨g進行蝕刻處理。 ^ ^柱狀隆起部之上部露出約1 5 // m且電鑛有金，藉以 〆成厚度約為0 · 1从m的蓋膜8。繼而，使用柱狀隆起部作
1223361 五、發明說明（26) 為遮罩藉由濕钱刻實行雷获阳腊 交互連接膜之不需；阻化學移除黏附膜與 理。因此防濕膜7形成於銅柱狀隆m境中之熱處 兹將參照圖25說明一種封裝方法 J呈表面上」接者， 成的柱狀隆起部之半導體i # 、/、有以丽述方法形 示，焊_預先：：；：：：：=;。如_所 :使付柱狀隆起部得位於配線基板之後二 件承載於配線基板上。麸德本 上之後，丰涂體疋 二i 使柱狀隆起部6連接至配線基板之勢 1 4。關於半導體元件與配線基板之接面 土 濡性良好的蓋膜形成於柱狀隆起部之上表$二=料： 部分上’且防濕膜形成於側 ：：：： 起部之根部之情況不會發生。 f濕通達柱狀隆 因ίΐ成ίϊ;樹脂17從側面灌入，以在填充後硬化。 u此凡成+導體元件之封裝。 [例子3 ] 株夕^於本發明之第三例子，兹將參照圖1 2說明半導體元 製造方法。類似於第一實㈣，在形成覆】 得=/銅作為交互連接膜4，且濺鍍銅作為黏附“，使 4之H膜/黏附膜得形成於整個表面上。交互連接膜 鍍阻膜^廿 ，且黏附膜5之厚度為500 nm。在形成電 、並猎由電解液電鍍形成直徑約為14〇 且高度
第31頁 I22336l
約為90从m的銅柱狀隆起部6之後，藉由乾式方法每一 刻處理，使用電鍍阻膜與銅之蝕刻速率差異讓鋼具仃立蝕 亡部分露出。露出的部分之高度設定成約為丨5 “巳冲之 著’藉由電解液電鍍使96. 5重量％的錫與3· 5重旦$ °接 銀共熔合金之焊料電鍍層9形成於銅隆起部里G的之 15 。 尽度約為 士既然焊料電鍍膜9亦形成於柱狀隆起部側表面上， 時，膜厚度之控制係重要的，使得在隨後的融此 =間=會發生短路。接著，在受到氧化環境中之日才電 刖，貫行電鍍阻膜剝落且藉由濕蝕刻移除過多的交^ = 膜與黏附膜，使得防濕膜7得形成於柱狀隆起部6側表面接 上。然後’形成於焊料電鍍膜9上的氧化膜藉 & 蒋昤。 日田电水處理 接著，茲將參照圖2 8說明一種封裝方法，用於以吁 形成於配線基板上的半導體元件。藉由擠壓於平=、 、滑的板上例如破璃板，活性樹脂1 8均勻地施加至銅^- ^上之焊料電鑛膜9之頂端，厚度約為4G㈣。使柱狀= 、已推向它並轉移熱固性樹脂（活性樹脂1 8)於頂端。轉.
f生樹脂之方法不限於可穩定供應至柱狀隆起部之頂端: 如插腳轉移之範圍 、麵丨 關於i: ΐ ’助熔劑用於移除隆起部之表面上的氧化膜。 淨半導體ίίΪ熔劑清潔，需要導入特殊的清潔設備以清 潔時間且得視己ΐ基板間之狹窄缝隙。此要求較長的清 τ Μ馬成本增加之原因。再者，清潔殘留物容易
第32頁 1223361 五、發明說明（28) 留下’成為可靠度下降之原因。 微間距傾向，縫隙清潔預計會變 施例般使用活性樹脂，則可有效 資、改良生產率、並且藉由省略 在施加活性樹脂1 8之後，對 線基板上，受到焊料重熔流佈製 基板之墊連接。最後藉著底部充 而完成半導體元件之封裝製程。 此處轉移且安裝活性樹脂， 樹脂。亦且，倘若金係薄薄地電 的焊料膜上，則接面更可改良到 接面。 在此實施例中，活性樹脂之 之頂端，且隨後填充底部充填樹 度高於所用的底部充填樹脂，則 脂灌入下實現，使得適當量的活 半體晶片承載於板上、且於焊 樹脂硬化。亦且，在實施例1至3 料膜、與焊料電鍍膜上，用以防 轉移至隆起部頂端並用於連接的 溶劑效應之活性樹脂，藉由接合 後增強連接部分。 [例子4 ] 參照本發明之第四例子，兹 亦且，藉由從現在起的細 得更加困難。倘若如此實 地降低人力與工廠設備投 清潔而改良封裝可靠度。 準半導體元件且承載於配 程，使柱狀隆起部與配線 填樹脂填充縫隙並硬化， 但助炼劑得用以取代活性 鑛於形成於柱狀隆起部上 無須使用助炫劑即可達成 非常小量地轉移 脂。倘若活性樹 樹脂填充亦可於 性樹脂供應至配 料重溶流佈製程 中，樹脂膜得設 止氧化。更且， 助熔劑，亦可使 時之熱量而硬化 至隆起部 脂之可靠 不實行樹 線基板、 時亦實行 於墊、焊 為了取代 用具有助 且於連接 將參照圖2說明半導體元 1223361 五、發明說明（29) 件之製造方法三首先，氧化矽沉積於整個半導體基板2上 方，且形成覆蓋膜3。在濺鍍銅膜之前，移除 一 部分且由鋁合金所形成的電極2之表面露出，以鈦作為交 互連接膜4且以銅膜作為黏附膜5。交互連接膜與黏附膜因 此形成於整個表面上。覆蓋層之厚度設定為4 5 、交 互連接，之厚度設定為60 nm、且黏附膜之厚度設定為5〇〇 rim。接者’電鍍阻膜19形成且藉由電解液電鍍沉積銅以獲 得柱狀隆起部6。柱狀隆起部之尺寸設定成直徑約為14〇 ^且南度約為9G _。繼而，#由金電鍍使厚度 p的蓋膜8連續形成於柱狀隆起部上表面 铲 膜剝落且藉由濕餘刻移除交互連接膜與黏附膜之 要又^ = = Γ罩。在此例子中不形成防濕 之半導體元件之配線基板。在f 於f有銅隆起部 於配線基板上之前，實施氬電載半導體元件 基板上。隨後對準半導體元件與 (〇._ — 〇. 49Ν)的負載，且同時隆加(埶^力=約5至5〇以 與墊間之接面得以達成。此處，既:於350 f ’使得隆起部 須清潔。此後立即從側面灌入底;U使用助熔劑故無 後硬化的樹脂。 底#充填樹脂，以獲得填充 如前所述，既然使用小量的煤 至配線基板上之墊，故可降低導耖^ 用丈干料而連接 双軚錯获的阿法劑量，並 第34頁 ^23361
專注於改良可靠度。亦且，既然連結至柱狀隆起部之焊 的部分係僅限於柱狀隆起部之上表面，或上表面附近^隆 起部側表面。藉而，即使隆起部變高，隆起部之直徑仍無 f變厚’且可確保半導體板與配線基板間之距離，回廡^ 兩插腳數目。據此，即使LS I之高密度傾向進展，依據〜本、 發明’仍可容易並可靠地填充底部充填樹脂。此外，依據 本發明’焊料不會往上濡濕遠達柱狀隆起部之根部，導致 柱狀隆起部與黏附膜間或黏附膜與交互連接膜間之接面強 度下降。可因此專注於改良可靠度。 既然本發明之柱狀隆起部係藉由電解液電鍍方法等等 而在晶圓階段形成，故可獲得比焊料球載入方法更低的製 造成本。亦且，依據實施例，於倒裝晶片安裝時使用異有 助熔劑活性效應的熱固性樹脂（活性樹脂）取代助熔劑，實 現了藉由減縮清潔製程且消除清潔殘留物降低成本而改良 玎靠度。
第35頁 1223361 圖式簡單說明 五、【圖示之簡單說明】 圖1係本發明半導體元件之第一實施例之剖面圖。 圖2係本發明半導體元件之第二實施例之剖面圖。 圖3係本發明半導體元件之第三實施例之剖面圖。 圖4係本發明半導體元件之第四實施例之剖面圖。 圖5係本發明半導體元件之第五實施例之剖面圖。 圖6係本發明半導體元件之第六實施例之剖面圖。 圖7係本發明半導體元件之第七實施例之剖面圖。 圖8A至8E係本發明半導體元件之製造方法之第一實施 例之剖面圖。 圖9A至9E係本發明半導體元件之製造方法之第二實施 例之剖面圖。 圖10A至1 OF係本發明半導體元件之製造方法之第三實 施例之剖面圖。 圖11A至11E係本發明半導體元件之製造方法之第四實 施例之剖面圖。 圖12A至12F係本發明半導體元件之製造方法之第五實 施例之剖面圖。 圖1 3係半導體裝置之第一實施例之剖面圖。 圖1 4係半導體裝置之第二實施例之剖面圖。 圖1 5係半導體裝置之第三實施例之剖面圖。 圖1 6係半導體裝置之第四實施例之剖面圖。 圖1 7係半導體裝置之第五實施例之剖面圖。 圖1 8係半導體裝置之第六實施例之剖面圖。
第36頁 1223361 圖式簡單說明 圖19A至19C係本發明半導體裝置之製造方法之第一實 施例之剖面圖。 圖20A至20C係本發明半導體裝置之製造方法之第二實 施例之剖面圖。 圖21A至21C係本發明半導體裝置之製造方法之第三實 施例之剖面圖。 圖22A至22C係本發明半導體裝置之製造方法之第四實 施例之剖面圖。 圖23A至23C係本發明半導體裝置之製造方法之第五實 施例之剖面圖。 圖24A至24C係本發明半導體裝置之製造方法之第六實 施例之剖面圖。 圖25A至2 5C係本發明半導體裝置之製造方法之第七實 施例之剖面圖。 圖26A至26C係本發明半導體裝置之製造方法之第八實 施例之剖面圖。 圖2 7A至2 7C係本發明半導體裝置之製造方法之第九實 施例之剖面圖。 圖28A至28C係本發明半導體裝置之製造方法之第十實 施例之剖面圖。 圖29A至29C係本發明半導體裝置之製造方法之第十一 實施例之剖面圖。 圖30A至30C係本發明半導體裝置之製造方法之第十二 實施例之剖面圖。
第37頁 1223361 圖式簡單說明 ， 圖3 1 A至3 1 C係本發明半導體裝置之製造方法之第十三 實施例之剖面圖。 圖32A至32C係本發明半導體裝置之製造方法之第十四 實施例之剖面圖。 - 圖33A至33C係本發明半導體裝置之製造方法之第十五 實施例之剖面圖。 圖34A至34C係本發明半導體裝置之製造方法之第十六 實施例之剖面圖。 圖3 5係半導體元件之習知例子之剖面圖。 圖3 6係半導體裝置之習知例子之剖面圖。 · 元件符號說明 1 半導體基板 2 電極 3 覆蓋膜 4 交互連接膜 5 黏附膜 6 柱狀隆起部 7 防濕膜 8, 8’ 蓋膜 9 電鍍膜 10 金膜 11 焊料填角 12 配線基板
第38頁 1223361 圖式簡單說明 13 焊料阻膜 14 墊 15 助溶劑 16 焊料膜 17 底部充填樹脂 18 活性樹脂 19 電鍍阻膜 20 隆起部 Φ Ο Ι1·Ι· 第39頁
Claims (1)
- 1· g —導體元件，包含：一柱狀突出部，作為^ Si: 一電極上，露出於…體基板上；其中上部 大部之一上表面上或上表面與侧表面之^ ^ ,Λ防止該柱狀突出部氧化並於焊接時被烊料濡 ; δΛ柱狀突出部的該側表面之靠近該電極之下邮 界定-難以被焊料漂濕之區域。 之下和 作ψ 1申㉔專利範圍第1項之半導體元件，其中，在該柱狀 =出邛之側表面之上部上與〆上表面上，包覆一蓋膜，該 盖膜係界定該區域用以防止該柱狀突出部氧化並於 被焊料濡濕。 3；如申請專利範圍第1項之半導體元件，其中，一防濕 膜’至少形成於該柱狀突出部之側表面中靠近該電極之部 如申請專利範圍第2或第3項之半導體元件，其中該柱狀 犬出部係經由一交互連接膜或一黏附膜而形成於該電極 〕·如申請專利範圍第3項之半導體元件，其中該柱狀突出 4之上表面或該柱狀突出部之側表面之上部與上表面係由 —蓋膜所塗佈，用以防止該柱狀突出部氧化且界定出一領 域’該領域係由該柱狀突出部之焊料濡濕。第40頁6. 如申請專利範圍第2或第5項之半導體元件，其中該蓋 膜係由金、金合金、錫、銦、或把所形成。 7. 如申請專利範圍第2或第5項之半導體元件，其中該蓋 膜係一樹脂塗佈膜，於焊接時熔化於助熔劑中。 8. 如申請專利範圍第3項之半導體元件，其中該柱狀突出 部之上表面或該柱狀突出部之側表面之上部與上表面係由 一焊料膜所塗佈。 係 膜 料 焊 該 中 其 件 元 體 導 半 之 項 8 第 圍 範 利 專 請 申 如 9 成 形 所 料 材 之 & 含 不 由 第 或 合 丨金 第或 圍膜 範金 利薄 專有 請佈 申塗 如係 •膜 L0料 焊 該 中 其 件 元 體 導 半 之。 項膜 金 膜 濕 防 該 中 其 件 元 體 導 半 〇 之膜 Λ 3 /1 第氣 圍層 範一 利或 專膜 請化 申氧 如層 • 一 L1係 的 成 形 所 面 表 之 丨部 第出 圍突 範狀 JnJ. t 矛柱 專該 請化 申氧 如由 •藉 2 係 件 元 體 導 半 之 項 膜 濕 防 該 中 其 膜 柱 該 中 其 件 元 體 導 半 之 項 3 第 或 2 第 圍 範 利 專 請 申 如^1第41頁 年 六、申請專利範圍 狀突出部係由銅或銅合金所形二種半導體元件之製造方法，包含下列+驟· 形成一金屬膜於一半導體基板之 夕驟· 部分上，作為一電鍍電極； v 一電極的整個 形成一阻膜於該金屬膜上，該阻膜具一 極之位置處； …、有一開口於該電 藉由電解液電鍍沉積一高導電性金屬成 成一柱狀突出部； …、主狀，以形 移除該阻膜； 藉由使用該柱狀突出部作為一遮罩而飾 屬膜·，以及 x彳以移除該金 形成一防濕膜於該柱狀突出部之表面上。 列步驟： 導體基板上具有 S處； 用於無電電鍍； 15. —種半導體元件之製造方法，包含下 形成一阻膜於一半導體基板上’該半 一電極，該阻膜具有一開口於該電極之位 精由活化處理而形成一活化處理層， 移除遠阻膜上之該活化層； 藉由無電電鍍沉積高導電金屬於該開D 柱狀突出部； ’以形成一 移除該阻膜；以及 形成一防濕膜於該柱狀突出部之表面上第42頁 換頁 k 號 92102710 年月 _j-fc, 六、申請專利範圍 16·如申請專利範圍第14或第15項之半導體元件之製造方 法’其中在該防濕膜形成於該柱狀突出部之表面上之後， 移除位於該柱狀突出部中連接至一封裝基板之部分上的該 防濕膜。 ’ · 17·如申請專利範圍第1 4或第1 5項之半導體元件之製造方 法’其中在該防濕膜形成於該柱狀突出部之表面上之前， 一遮罩形成於該柱狀突出部中不應形成該防濕膜之一區域 上’以及在該防濕膜形成於該柱狀突出部之表面上之後， 移除該遮罩。 18·如申請專利範圍第1 4或第1 5項之半導體元件之製造方 法，其中該防濕膜係藉由CVD方法所沉積的一層氧化矽膜 一層氮化矽膜。 、5 19.如申請專利範圍第14或第15項之半導體元件之製造方 法，其中該防濕膜形成於該柱狀突出部之表面上 露該柱狀突出部至氣化璜谙以游# ^ ^ ^示稽田泰 出部之表面上 兄形成一層乳化膜於該柱狀突 2 0.如申請專利 中移除該柱狀突 露該柱狀突出部 摩色圍第1 6項之半 出部之連接部分 至非活性氣體之 導體元件之製造 中之該防濕膜係 電漿。 方法，其 對應於暴第43頁21·如申請專利範圍第14或第15項之半導體元件之製造方 法’其中在形成该柱狀突出部之後以及在移除該阻膜之 前’一蓋膜塗佈於該柱狀突出部之上表面上，該蓋膜係由 比該柱狀突出部更難氧化的一金屬所形成。 ' 2 2·如申請專利範圍第1 4或 法，其中在形成該柱狀突出 前’藉由施加半餘刻於該阻 表面之上部’且一蓋膜塗佈 側表面，該蓋膜係由比該柱 形成。 第15項之半導體元件之製造方 部之後以及在移除該阻膜之 膜而暴露該柱狀突出部之該側 於該柱狀突出部之上表面與上 狀突出部更難氧化的一金屬所 23·如申請專利範圍第14項之半導體元件之製造方法，盆 中在形成該柱狀突出邱w β 八 枓Μ塗佈於該柱狀突出部之上表面上。 太干 24 含 由 部 25 下專利範圍第14項之半導體元件之製造方法，包 施： = = 及在移除該阻膜之前，藉 ;以及藉』i狀突出部之侧表面之上 稭者坏枓膑塗佈上表面與侧表面之上部。 •一種半導體裝置，包含：― 半導體元件之一電極上，焊’、柱狀突出部’形成於 电斤上斗接至一配線基板之一墊；其第44頁 货，換頁丨 -早3^ 7·月曰墚號9210271立 六、申請專利範圍 中’在該柱狀突出部之— 部上，界定一區域用w κ 面上或上表面與側表面之上 被焊料《，在===狀突出部氧化並於焊接時 部分被焊接。 篇‘之£域，只有被焊料濡濕之 26·如申請專利範圍第25項之半 犋，至少塗佈於該柱狀突出 =裝置八中，一防濕 部分。 °之側表面中靠近該電極之一2 7.如 突出部28. 上； 以 部， 其 屬膜係 部之該 上。 申請專利範圍第25項之半導體裝置… 之一焊接部分僅為該柱狀突㈣之^面/ 種半導體裝置，包含··導電柱狀突出部，形成於 ,及 田丨形成於一半導體元件上之一電極 塾，位於一配線基板上且捏拉 1焊接至該導電柱狀突出 中該柱狀突出部經由一金屬比兮妇肿办山如$ # '屬膜而焊接至該墊，該金 1*矣品μ々#上, 乳化且形成於該柱狀突出 上表面上或該柱狀突出部 ^& 1 <側表面之上部與上表面、換頁 7月OJg[案號92102710__年月曰 鯈L___ 六、申請專利範圍 一導電柱狀突出部，形成於一半導體元件之一電極 上；以及 一墊，位於一配線基板上且焊接至該導電柱狀突出 部， … 其中該柱狀突出部之上表面與該配線基板之一墊表面 係經由比該柱狀突出部更難以被氧化的一金屬膜而黏附。 30·如申請專利範圍第28或第29項之半導體裝置，其中該 難以被氧化的金屬膜係由金或金合金所形成。 31·如申請專利範圍第2 6至第2 9項中任一項之半導體裝 置’其中樹脂填充於該半導體元件與該配線基板間。 32· 一種半導體裝置之製造方法，包含下列步驟： 立 供應具有助炼劑活性效應的熱固性樹脂至一柱狀突出 4之頂端部或焊接至其上的一配線基板之一墊，該柱狀突 出部係形成於一半導體元件之一電極上； 日 對準該柱狀突出部與該配線基板之供應有一預定量的 焊料之該墊；以及 加熱並焊接僅該柱狀突出部之頂端部至該配線基板之 一種半導體裝置之製造方法，包含下列步驟： 供應助熔劑至一柱狀突出部之一頂端部或應焊接至其第46頁 1¾%換頁 )〒·年 7·月案號 921 0 六、申請專利範圍 上的一配線基板之一墊，該柱狀突出部係形成於一半導體 元件之一電極上； 對準该柱狀突出部與該配線基板之供應有一預定量的 焊料之該墊； ^ 加熱並焊接僅該柱狀突出部之該頂端部至該配線基板 上之該墊；以及 清潔並移除該助熔劑。 34·如申請專利範圍第32或第33項之半導體裝置之製造方 法其中至少在該烊接製程之前，該柱狀突出部之上表面 或f柱狀突出部之側表面之上部與上表面塗佈有一蓋膜， 4蓋膜係由具有極佳可濡性的一金屬所形成。 35·如申請專利範圍第32或第33項之半導體裝f之裨古 法’其，在焊接之前，—蓋膜覆蓋於該柱狀突【部= 面上f該柱狀突出部之侧表面之上部與上表面，該蓋膜係 树知材料所形成，该樹脂材料於實行焊接時溶化於^ 有助熔劑作用的一材料中。 、八 一種半導體裝置之製造方法，包含下列步驟： 立供應具有助熔劑活性效應的一熱固性樹脂至一柱狀突 出部之一頂端部或焊接至其上的一配線基板之一墊；犬 對準該柱狀突出部與該配線基板之該墊，該壯如 部係形成於一半導體元件上之一電極上且具有一焊料ς:ιψλ% fe% 1餘7月_ I號 92102710 年月曰 修正 六、申請專利範圍 其之該頂端部；以及 之該墊 加熱並悍接僅該柱狀突出部之該頂端部至該配 執。 、、&卷板 37· —種半導體裝置之製造方法，包含下列步驟： 至其上 供應助熔劑至一柱狀突出部之一頂端部或烊接 的一配線基板之一墊； 該桎狀突 一焊料膜 對準該柱狀突出部與該配線基板上之該墊， 出邻係形成於一半導體元件上之一電極上且具有 於其之該頂端部； 加熱並焊接僅該柱狀突出部之該頂端部至該配線其 上之該墊；以及 土攸 移除並清潔該助熔劑。 38. —種半導體裝置之製造方法，包含下列步驟： 焊料：準：柱狀突出部與一配線基板之供應有-預定量的 =之-[該柱狀突出部係形成於—半導 極上，以及 ^ 加熱並焊接僅該柱狀突中^ 之該塾· 穴出"卩之该頂端部至該配線基板 其中該柱狀突出部之焊垃都八+ ^ 接部分中之至少一處彤# ^ Ρ刀或该墊上之該焊料之焊 丨刀Υ之至V處形成有一薄金膜。 39· 種半導體裝置之製造方法，包含 下列步驟：第48頁 -墊對：7柱狀突出部與應焊接至其上的-配線基板上之 具有-;部係形成於一半導體元件之-電極上且 ^ ¥科膜於其之頂端部；以及 之該ί熱並悍接僅該柱狀突出部之該頂端部至該配線基板 料膜膜形成於該柱狀突出部與該塾上之該焊、如申請專利範圍第32、第33、或第36至第39項之半導 裝置之製造方法，其中在該焊接製程中，壓力施加於該 導體元件與該配線基板間 • 種半導體裝置之製造方法，包含下列步驟： 藉由電漿所激發的一非活性氣體之物理性衝擊而清嗲 -柱狀突出部之頂表面與一配線基板上之一塾：：而 狀突出部係形成於一半導體元件之一電極上； 對準該柱狀突出部與該配線基板之該塾；以及 當施壓於該半導體元件與該配線基板時黏附該柱狀突 出部與該墊。 4 2 ·如申請專利範圍第41項之半導體裝置之製造方法，其 中該黏附係藉由加熱及/或超音波震盪而完成。 43·如申請專利範圍第41或第42項之半導體裝置之製造方第49頁 I2^i6 “換頁€3年7月0 Q曰案號92102710 六、申請專利範圍 法，其中在該柱狀突出部之上表面及/或該墊之外表面上形 成難以氧化的一金屬膜，以經由該難以氧化的金屬膜黏y 該柱狀突出部與該墊。 44·如申請專利範圍第41項之半導體裝置之製造方法，其 中該柱狀突出部與該墊之黏附係實行於一真空或非氧化環 境中。45·如申請專利範圍第32、第36、第37、第38、第39、或 第41項之半導體裝置之製造方法’其中在該柱狀突出部焊 接至該塾或該柱狀突出部黏附至該墊之後，樹脂填充於該 半導體元件與該配線基板間。第50頁
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2002
- 2002-02-07 JP JP2002030334A patent/JP3829325B2/ja not_active Expired - Lifetime
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2003
- 2003-02-06 US US10/359,124 patent/US7135770B2/en not_active Expired - Lifetime
- 2003-02-07 KR KR1020030007943A patent/KR100545008B1/ko active IP Right Grant
- 2003-02-07 TW TW092102710A patent/TWI223361B/zh not_active IP Right Cessation
- 2003-02-08 CN CNB031042406A patent/CN100511658C/zh not_active Expired - Lifetime
- 2003-02-08 CN CNA2005100897126A patent/CN1873939A/zh active Pending
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- 2005-11-14 US US11/271,819 patent/US7268438B2/en not_active Expired - Lifetime
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- 2006-09-12 US US11/519,153 patent/US7449406B2/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8736060B2 (en) | 2009-09-23 | 2014-05-27 | Chipmos Technologies Inc. | Packaging structure |
Also Published As
| Publication number | Publication date |
|---|---|
| US20090035893A1 (en) | 2009-02-05 |
| JP2003234367A (ja) | 2003-08-22 |
| KR20030067590A (ko) | 2003-08-14 |
| US20060065978A1 (en) | 2006-03-30 |
| US7135770B2 (en) | 2006-11-14 |
| CN100511658C (zh) | 2009-07-08 |
| JP3829325B2 (ja) | 2006-10-04 |
| CN1873939A (zh) | 2006-12-06 |
| US7449406B2 (en) | 2008-11-11 |
| TW200303058A (en) | 2003-08-16 |
| US20030151140A1 (en) | 2003-08-14 |
| US20070020912A1 (en) | 2007-01-25 |
| CN1437256A (zh) | 2003-08-20 |
| US7749888B2 (en) | 2010-07-06 |
| KR100545008B1 (ko) | 2006-01-24 |
| US7268438B2 (en) | 2007-09-11 |
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