TW507337B - Method of forming high flip chip solder bump - Google Patents
Method of forming high flip chip solder bump Download PDFInfo
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- TW507337B TW507337B TW090112677A TW90112677A TW507337B TW 507337 B TW507337 B TW 507337B TW 090112677 A TW090112677 A TW 090112677A TW 90112677 A TW90112677 A TW 90112677A TW 507337 B TW507337 B TW 507337B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Description
507337507337
五、發明說明(1) 發明領域: 本發明與一種積體電路之凸塊製程(bumping process)有關,特別是有關於一種可以增加凸塊高 凸塊製程。 ^長 發明背景: 晶片封裝是目前積體電路製程中不可或缺的步驟,隨 著半導體元件高積集度的需求,如何提高I C晶片數目於5^ 封裝體以及如何使封装後的晶片變得更薄,將變得更 要。 ’堇 C封裝的主要功能包括:保護1C、提供晶粒(chip)和 外界系統裝置之間訊息傳遞的介面,所以I C製程發展、系 統產品的功能性都是影響I C封裝技術發展的主要原因。^ 曰電子產品的要求是輕薄短小,就要有減少晶粒尺寸的技 術’ I c製程微細化,造成晶粒内包含的邏輯線路增加, 且由於時下晶片操作速率越來越快,因此其與外部連接之 1C封裝體的I/O引腳數目不僅越來越多且越來越密,造成 了許多不同的新一代的封裝方式,如··球柵陣列(b a i i grid array, BGA)、晶片尺寸封裝(CSP)、多晶片模組 (multi-chip module; MCM)、覆晶(flip chip) 曰等先進 技術應運而生。覆晶封裝由於減少了晶片至外界系統裝置 之間訊息傳遞的路徑距離,而具有較佳的電氣特性,^為 頗受矚目的下一世代封裝技術。 ”V. Description of the invention (1) Field of the invention: The present invention relates to a bumping process of an integrated circuit, and more particularly to a bumping process that can increase the bump height. ^ Long background of the invention: Chip packaging is an indispensable step in the current integrated circuit manufacturing process. With the demand for high integration of semiconductor components, how to increase the number of IC chips to 5 ^ package and how to make the packaged chip become Thinner, will become more important. The main functions of the CV package include: protecting the 1C and providing an interface for information transmission between the chip and external system devices. Therefore, the development of the IC process and the functionality of the system products are the main reasons that affect the development of the IC packaging technology. ^ The requirements for electronic products are light, thin and short, and there must be a technology to reduce the size of the crystal grains. The miniaturization of the IC process has resulted in an increase in the number of logic circuits contained in the crystal grains. The number of I / O pins of the 1C package connected to the outside is not only increasing and denser, which has led to many different new-generation packaging methods, such as · baii grid array (BGA), Advanced technologies such as chip size package (CSP), multi-chip module (MCM), and flip chip have come into being. Flip-chip packaging has better electrical characteristics because it reduces the path distance for information transmission between the chip and external system devices. It is the next generation packaging technology that has attracted much attention. "
507337 五、發明說明(2) ir 覆晶封裝技術是利用導體凸塊作為輸入/輸出。對於 形成導體銲接凸塊的製程中,通常在鋁金屬焊墊(pad) 上’利用麵刻製程蝕刻護層以暴露出焊墊。再分別沈積阻 障層與導電層之組合層於其上,一般的組成包含Cr/Cu、 Ti/Cu。之後,利用微影製程塗佈光阻且形成圖案,形成 在銘焊墊上具有一開窗1用電鍍法形成錫於 塊。下一步驟為利用銲接凸塊作 = 、接507337 V. Description of the invention (2) ir flip-chip packaging technology uses conductor bumps as input / output. In the process of forming a conductive solder bump, the protective layer is usually etched on the aluminum metal pad using a face-etching process to expose the solder pad. A combination layer of a barrier layer and a conductive layer is deposited thereon, and the general composition includes Cr / Cu and Ti / Cu. After that, a photoresist is applied and patterned using a lithography process to form a window 1 on the pad, and tin is formed by electroplating. The next step is to use solder bumps as =, then
之阻障層與導電層,完成形成垃J罩幕去除未被遮住 障層與導電層的組合層即所稱::$製程,❿留下之阻 metallurgy,UBM)。 鬼下金屬(under bump 凸塊高度對於後續封裝步驟 得到較健全的可靠度,是相當驟會的I成功與否以及是否可以 塊製程中之凸塊高度可藉由擴 的,雖然上述習知的凸 加,但是仍然、會被最後的凸〗^塊下金屬㈣尺寸而增 不穩定。此外,凸塊下金屬的又所限制,而且使得性能 鄰的二個凸塊下金屬發生互寸擴展之後,可能造成相 及相接觸的缺陷。The barrier layer and the conductive layer are completed to form a J-mask to remove the uncovered combination layer of the barrier layer and the conductive layer, which is called: $ process, the resistance left by metallurgy (UBM). Under bump metal (under bump) The bump height is relatively reliable for subsequent packaging steps. The success or failure and whether the bump height in the block process can be expanded can be achieved. Convex increase, but still, it will be unstable due to the size of the final convex metal. In addition, the metal under the convex is limited, and the performance of the two adjacent metal under the convex expands after each other. , May cause defects in contact and contact.
目前長凸塊的主要方法_ · (plating),在增加凸塊高声、(print)及電鍍法 所能增加有限,光阻過高在^办自有困難,因光阻的高度 凸塊材料則可能造成相鄰的^衫上會有問題。電鍍較多的 、一個凸塊發生相互連接而產生At present, the main method of long bumps is (plating), which can increase the increase of bump high-frequency, (print) and electroplating methods. The increase in photoresistance is limited. If the photoresistance is too high, it is difficult to handle it. It may cause problems on adjacent shirts. More plating, one bump is connected to each other
507337507337
五、發明說明(3) 短路缺陷。因此如何提供一種增加凸塊高度而又能避免上 述問題的產生的方法,是目前業界的一大努力方向。 發明目的及概述: 本發明之目的係提供一種凸塊形成方法,以得到足夠 的凸塊高度,以健全良率及可靠度。 本發明誕出一種凸塊形成方法,其包括了下列步驟: 提供一晶片’其中此晶片已完成積體電路製程且此晶片之 上具有金屬焊墊。形成護層於晶片上並蝕刻露出金屬焊墊 表面。接著在護層與金屬銲墊上形成凸塊下金屬層,然後 利用光阻疋義出凸塊下金屬的位置,然後形成銲接凸塊於 凸塊下金屬的位置上,隨後利用助銲劑(f丨ux )及硬烤 (hard bake)除去銲接凸塊表面的氧化物,接著以盔電電 鍍法形成一額外的電鍍層,然後除去光阻,並去除露出的 凸塊下金屬層,最後熱回流銲接凸塊,以形成錫球。 發明詳細說明: 本發明之目的係提供一種凸塊形成 的凸塊高度,以健全良率及可靠产成方法:以付到足V. Description of the invention (3) Short circuit defect. Therefore, how to provide a method to increase the height of the bumps while avoiding the above problems is a major effort in the industry. OBJECTS AND SUMMARY OF THE INVENTION The object of the present invention is to provide a bump formation method to obtain a sufficient bump height, with a sound yield and reliability. The present invention provides a bump forming method, which includes the following steps: Provide a wafer 'wherein the wafer has completed the integrated circuit manufacturing process and has metal pads on the wafer. A protective layer is formed on the wafer and etched to expose the surface of the metal pad. Next, a metal layer under the bump is formed on the protective layer and the metal pad, and then a photoresist is used to define the position of the metal under the bump, and then a solder bump is formed on the metal position under the bump, and then a flux (f 丨ux) and hard bake to remove the oxide on the surface of the solder bumps, and then use the helmet electroplating method to form an additional plating layer, then remove the photoresist, remove the exposed metal layer under the bumps, and finally reflow solder Bumps to form solder balls. Detailed description of the invention: The object of the present invention is to provide a bump height formed by bumps, with a sound yield and a reliable production method:
凸塊的高度,太 特別疋就增加完Θ 兩階段形成銲Λ掄M t 4…、電鍍成凸塊的方法, 或網印的古a / ^ , f j f又巧的凸塊。先以1 二P的方式形成原始焊接凸塊,再 始凸塊上报士 丹从無電電鍍法在it 疋上形成一層新的銲接材料,一 新凸塊(new bumiThe height of the bumps is too special, and it will increase the Θ two stages to form the welding Λ 形成 M t 4 ..., the method of plating into bumps, or the screen-printed ancient a / ^, f j f, and clever bumps. First, the original solder bumps are formed in the form of 1 2 P, and then the bumps are reported to Dan. From the electroless plating method, a new layer of welding material is formed on it 疋, a new bump (new bumi
507337507337
說明非用以限定本發明。 參閱圖一,在晶圓100上具有一金屬焊墊(pad)2 π 晶圓100及,金屬銲墊2的表面形成一護層(Passivati〇n)4 亚利用光阻定義出焊墊的所在區域,以蝕刻製程蝕刻護層 j暴路出.:!:于墊2。上述之護層4之組成可以包含聚亞醯胺 if〇」yimjde,Pl)、BCB (benZ〇Cycl〇butene)或氮化石夕。 接著形成凸塊下会屬厚·几 metal,_的作用:連接下金屬―13, 面,通常包含阻障層與導電層,具有 用包含鈦或路的金屬=構:先形成阻障,:可以選 般包含銅或銅合金’可以先::‘電層於其上’導電層-子層(seedlng Uyer),再/^成一利於銅材質電鍍的銅種 以再使用電鍍法在立表面开使/電鑛法電錄㈣,之後可 Ϊ=;方度約為2至4微米。上述之銅種子層 用气鍵方式形成在阻障層The description is not intended to limit the invention. Referring to FIG. 1, there is a metal pad 2 on the wafer 100. The wafer 100 and the surface of the metal pad 2 form a passivation layer 4. The photoresist is used to define the location of the pad. Area, the protective layer j is eroded by the etching process.:!: 于 垫 2. The composition of the protective layer 4 described above may include polyimide (polyimide), yimjde (Pl), BCB (benzo, Cyclbutene), or nitride. Next, the thickness of the bump will be thick. Several metal, the role of _: connected to the lower metal -13, the surface, usually contains a barrier layer and a conductive layer, with a metal structure containing titanium or a road: first form a barrier ,: You can choose to include copper or copper alloys. You can first :: 'Electric layer on it' conductive layer-sublayer (seedlng Uyer), and then a copper seed that is good for copper plating, and then use the plating method to open the surface The recording is performed by the electric / electric mining method, and then can be calculated; the squareness is about 2 to 4 microns. The above copper seed layer is formed on the barrier layer by gas bonding.
Ti/Cu。則述所舉之材質盎 耿局ur/Lu :¾ 明,非用以限定本發明精、神子度3僅做為一實施例用以說 功能材質之替換。 ,疋故本發明之範圍包含均等Ti / Cu. The description of the materials mentioned here is ur / Lu: ¾, but it is not used to limit the essence of the present invention and the degree of god son 3 only as an embodiment to describe the replacement of functional materials. Therefore, the scope of the present invention includes equality
佈—光阻層8於此凸塊下金屬社 製程在光阻上定慕Φ•層6結構 接著利用微影 接凸堍ίο τ =義出人形成銲接凸塊的區域。接著形成銲 極心微Π:】;:方式,以凸塊下金屬為電鍵陰 中’在露出的λ、Γ二』含有鉛(1 ead)和錫(t i η)的溶液 一般合在盤作Ϊ 屬6表面形成銲接凸塊10於其上。 比例;以啁整二接凸:時摻雜鉛,乃依照需求設定混合之 斜m 他作為銲接凸塊材料者尚有混合 視所!不^ 、鉍或銦等金屬的不同組成的合金, 見所*不同熔點及抗疲勞程度加以搭配運用。 塗佈之後Λ除/阻,如圖四所示,接著並於銲接凸塊ι〇上 層助#劑(flux)12。助銲劑12的功能為清潔銲接凸 低炼融銲錫與基板之間的表面張力以提高潤 =/供適當的腐姓性、發泡性(Foaming)、揮發性與 黏π性’以利銲接的進行。助銲劑12的成分包括活化劑 (Actlvators)、載劑、溶劑與其他特殊功能之添加物。助 銲劑活性越高’清潔的效果越好’藉助鲜劑12之塗佈 (flux coating)去除銲接凸塊10表面生成的氧化物以利後 續無電電鍍及銲接的進行。隨後硬烤(hard bake)去除助 銲劑與氧化物。 接著’將銲接凸塊1 0浸於無電電鍍液2 〇 〇中(如圖五 所不)’進行無電電鑛’於銲接凸塊1〇表面形成一層新凸 塊(new bump)層14。此新鍍之凸塊層ι4之組成物質與銲接The cloth-photoresist layer 8 is formed on the photoresist by the metal film process under this bump. The layer 6 structure is then determined by lithography. Then τ = defines the area where the solder bumps are formed. Next, the formation of the solder core micro Π:] ;: way: the solution containing lead (1 ead) and tin (ti η) in the exposed λ and Γ2 in the cathode under the bump as the key bond is generally combined on the disk. The metal bump 6 has solder bumps 10 formed on the surface. Proportion; Integrate the two convex projections: doped lead at times, and set the oblique m of the mixture according to the needs. He, as a solder bump material, still has a mixture. Alloys with different compositions of metals such as bismuth, bismuth, or indium, etc. See different melting points and fatigue resistance levels for matching. After coating, it is removed / resisted, as shown in Fig. 4, and then flux 12 is applied on the solder bumps. The function of the flux 12 is to clean the surface tension between the solder bump and the substrate to improve the wettability. For proper soldering, foaming, volatility and viscosity, to facilitate soldering. get on. The composition of the flux 12 includes activators, carriers, solvents and other special functional additives. The higher the flux activity, the better the cleaning effect. The oxide coating on the surface of the solder bump 10 is removed by the flux coating of the flux 12 to facilitate subsequent electroless plating and soldering. The hard bake is then removed to remove the flux and oxides. Next, 'immersion solder bump 10 is immersed in electroless plating solution 2000 (as shown in Fig. 5)' and perform electroless mining 'to form a new bump layer 14 on the surface of solder bump 10. Composition and welding of this newly plated bump layer ι4
第9頁 507337 五、發明說明(6) 凸塊10有相同的選擇,如船錫合金等。其無電鍍浴乃藉由 氧化還原電位的不同,使要鍍金屬附於被鍍物表面。無電 電鍍液中須包含要鍍金屬的水溶性鹽類,如水溶性錫鹽、 水溶性鉛鹽、水溶性鉍鹽、水溶性銦鹽等及可溶解此等鹽 類的酸液,如過氣酸、有機磺酸、磷酸、氟硼酸、縮合磷 酸、鹽酸及焦磷酸或二種以上此類酸之混合物與錯合^, 如草酸、酒石酸、檸檬酸、乙二胺四乙酸(EDTA)&其鹽、 硫[CX8A68]、硫[CX8A68]衍生物及三乙醇胺或二種以上此 類錯合劑之混合物。 最後,如圖七所示,經過預烤(pre_bake)、預熱流 jpre-flow)以及熱流(refl〇w),將銲接凸塊因内聚力等因 f 球狀結構完成錫球301之製作,再以錫球3〇1為罩冪 蚀刻去除露出的凸塊下金屬層。 錫球3 0 〇為沒有 鍀接材料較少,所 凸塊層的體積換算 球高度,因此吾人 夠的新凸塊層厚度 艘新凸塊層14,熱 形成的錫球高度亦 成成球後的體積, 可視需增加的錫球 來達成。 流後所得結果,因 較低。將所增加的新 可估計出所增加的錫 高度,藉無電電鍍足 後再上進述實施例攝中」光阻8的去除亦可於形成新凸塊層η -個銲接凸塊㈣形成之新凸塊電層Page 9 507337 V. Description of the invention (6) The bump 10 has the same choice, such as ship tin alloy. The electroless plating bath makes the metal to be plated on the surface of the object to be plated by the difference of the redox potential. The electroless plating solution must contain water-soluble salts of the metal to be plated, such as water-soluble tin salts, water-soluble lead salts, water-soluble bismuth salts, water-soluble indium salts, etc. Organic sulfonic acid, phosphoric acid, fluoboric acid, condensed phosphoric acid, hydrochloric acid and pyrophosphoric acid or a mixture of two or more of these acids ^, such as oxalic acid, tartaric acid, citric acid, ethylenediaminetetraacetic acid (EDTA) & its salts , Sulfur [CX8A68], sulfur [CX8A68] derivatives and triethanolamine or a mixture of two or more of these complexing agents. Finally, as shown in FIG. 7, after pre-bake, pre-flow, and reflow, the solder bumps are produced due to cohesive forces and the like due to the f-ball structure. The solder ball 301 was used as a mask to remove the exposed metal layer under the bump. The solder ball 3 0 〇 is a material with no bonding material and the volume of the bump layer is converted into a ball height. Therefore, the thickness of the new bump layer is sufficient to ship the new bump layer 14. The height of the solder ball formed by the heat also becomes a ball. The volume can be achieved by adding solder balls as needed. The results obtained after the flow are lower. The added tin can be used to estimate the increased tin height. After the electroless plating is completed, the above photo is taken. The removal of the photoresist 8 can also form a new bump layer η-a new solder bump ㈣. Bump layer
507337 五、發明說明(7) 晶圓都會有彎曲的情形,使浸入無電電鍍液2 0 0的程度不 同,使最後增加的錫球高度有所差異。 本發明以較佳實施例說明如上,而熟悉此領域技藝 者,在不脫離本發明之精神範圍内,當可作些許更動潤 飾,其專利保護範圍更當視後附之申請專利範圍及其等同 領域而定。507337 V. Description of the invention (7) The wafers may be bent, so that the degree of immersion in the electroless plating solution 2000 is different, and the height of the solder balls added at the end is different. The present invention has been described above with reference to the preferred embodiments, and those skilled in the art can make some modifications and modifications without departing from the spirit of the present invention. Field-specific.
第11頁 507337 圖式簡單說明 利用後續說明以及下列圖示之配合,可更清晰的了解 本發明之内容及優點,其中: 第一圖顯示依據本發明之一實施例形成凸塊之橫截面 示意圖,係先於晶片上依序形成金屬焊墊、護層、凸塊下 金屬層。 · 第二圖顯示依據本發明之一實施例利用光阻定義定義 出凸塊下金屬的位置。 第三圖顯示依據本發明之一實施例形成凸塊之橫截面 不意圖。 第四圖顯示依據本發明之一實施例於凸塊上塗佈助銲 劑並去除光阻之橫截面示意圖。 第五圖顯示依據本發明之一實施例將凸塊浸泡於無電 電鍍溶液中。 第六圖顯示依據本發明之一實施例形成凸塊之橫截面 示意圖,包含在凸塊上再形成一層銲錫材料。 第七圖顯示依據本發明之一實施例熱流形成球形凸塊 之橫截面示意圖。Page 507337 Brief description of the diagram Using the following description and the cooperation of the following diagrams, the contents and advantages of the present invention can be more clearly understood, where: The first diagram shows a schematic cross-sectional view of a bump formed according to an embodiment of the present invention First, a metal pad, a protective layer, and a metal layer under the bump are sequentially formed on the wafer. The second figure shows the use of a photoresist definition to define the position of the metal under the bump according to one embodiment of the present invention. The third figure shows a cross-section of a bump formed according to an embodiment of the present invention, which is not intended. The fourth figure is a schematic cross-sectional view of applying a flux on a bump and removing photoresist according to an embodiment of the present invention. The fifth figure shows that the bumps are immersed in an electroless plating solution according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a bump formed according to an embodiment of the present invention, which includes forming another layer of solder material on the bump. FIG. 7 is a schematic cross-sectional view of a spherical bump formed by heat flow according to an embodiment of the present invention.
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TW090112677A TW507337B (en) | 2001-05-25 | 2001-05-25 | Method of forming high flip chip solder bump |
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2001
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