TW418470B - Method for forming solder bumps on flip chips and devices formed - Google Patents
Method for forming solder bumps on flip chips and devices formed Download PDFInfo
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- TW418470B TW418470B TW088104959A TW88104959A TW418470B TW 418470 B TW418470 B TW 418470B TW 088104959 A TW088104959 A TW 088104959A TW 88104959 A TW88104959 A TW 88104959A TW 418470 B TW418470 B TW 418470B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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Abstract
Description
4184 70 五、發明說明(1) 【發明之範圍】 , 本發明係有關於一種復晶焊料球的製造方法及其結構 ,且特別係有關於一種利用雙層光阻劑,其第一薄光阻劑 層係用以在BLM (Bali-Limitting-Metallurgy)層上定義-至所需的位置,其第二厚光阻劑層係用以定義所欲、焊料 凸塊的開孔及其所長成之焊料凸塊的高度,藉由此雙重光‘ 阻劑層以形成微細間距覆晶焊料球的結構及其製造方法。 【發明之背景】 在目前半導體元件製造技術中,大都藉由增加半導體 元件的電路密度或是減少元件的尺寸以得到高密度的半導 體元件,但如此一來,由於it件的尺寸減少與密度增加_, 導致對封裝(Packaging)技術與内連線(interconnecting) 技術之可靠度的要求日益嚴苛,其中一種用來封裝晶片的 方法疋覆晶接合技術(Flip-Chip Attachment Method), 此一覆晶接合技術是以金屬導體取代引線架(Lead Frame) ,亦即將裸晶以表面朝下的方式與基板(Substrate)連結 的技術’金屬導體可為金屬凸塊(Metal Bump)、捲帶接合 (Tape-Automated Bonding)、異方性導電膠(Anisotropic Conductive Adhesives)、高分子凸塊(p〇iymer Bump)等 ’其中以金屬凸塊為覆晶接合技術的主流,而金屬凸塊的 材料又以錫鉛合金為主’因此由錫鉛合金製成的金屬凸塊 又稱為錫鉛凸塊,其利用錫鉛凸塊以接合的方法是先在半 導體晶粒表面形成一錫鉛凸塊接點,再藉由錫鉛凸塊的融 您使晶片的鋁焊墊(A1 Bonding Pad)與基板線路接合而完4184 70 V. Description of the invention (1) [Scope of the invention] The present invention relates to a method and a structure for manufacturing a polycrystalline solder ball, and particularly relates to a first photoresist using a double-layer photoresist. The layer is used to define on the BLM (Bali-Limitting-Metallurgy) layer-to the desired position, and its second thick photoresist layer is used to define the desired openings of the solder bumps and the solder they grow into. The height of the bumps is used to form the structure of the fine-pitch flip-chip solder ball by the double photoresist layer and the manufacturing method thereof. [Background of the Invention] In the current semiconductor element manufacturing technology, most of the semiconductor elements are obtained by increasing the circuit density of the semiconductor element or reducing the size of the element to obtain a high-density semiconductor element. _, Leading to increasingly stringent requirements for the reliability of packaging technology and interconnecting technology. One of the methods used to package chips is the Flip-Chip Attachment Method. The crystal bonding technology is to replace the lead frame with a metal conductor, that is, a technology that connects the bare crystal with the substrate in a face-down manner. The metal conductor can be metal bumps, tape bonding ( Tape-Automated Bonding), Anisotropic Conductive Adhesives, polymer bumps, etc. 'Among them, metal bumps are the mainstream of flip-chip bonding technology, and the material of metal bumps is Tin-lead alloy is the main component. Therefore, metal bumps made of tin-lead alloy are also called tin-lead bumps. A first solder bumps formed in the joint surface of the semiconductor die, and then by melting solder bumps your aluminum pads of the wafer (A1 Bonding Pad) bonded to the substrate and the line End
4 184 TO 五'發明說明(2) t 成组裝,其中上述之錫鉛凸塊接點在晶粒表面成面矩陣(' Area Array)排列,可提高晶圓的I /〇比,而目前製作錫鉛 凸塊的方法有蒸鑛(Evaporation)、電鑛(Electroplating )、印刷(Printing)、電沉積(Electrodeposition)或是其 它方式,其中電沉積方式是最近幾年才發展的新技術。 除了上述技術外,尚有其它可在各種不同基板上成長 錫鉛凸塊的技術也已經被揭露,例如其中一種普遍應用於 8 11寸晶圓封裝的錫膏印刷技術(Solder-Paste Screening M e t h o d ) ’然而,隨著元件尺寸的縮小化與減少錫鉛凸塊 之間距(P i t c h )的要求下,錫膏印刷因受限於下述原因而 變得不切實際,第一點是當使用此錫膏印刷技術在接合錫 鉛凸塊與基板時常會被皇_己i複合物黏合,這是由於錫膏( S ο 1 d e r P a s t e )是由可流動(F 1 u X)之材料及焊料(S ο 1 d e r ) 合金顆粒形成,因此當錫鉛凸塊體積減少時要控制錫膏複 合物的濃度與均一性是一件很困難的事,針對此點,習知 曾揭露一種包含有粒徑大小均一的微細顆粒,藉此改善上 述之缺點,但如此一來,勢必會增加生產成本;第二點是 當使用此錫膏印刷技術製造高密度半導體元件時會使兩錫 鉛凸塊之間的間距變得很有限,這是由於當錫從流動狀態 變成固態時其體積會大幅縮減,而使得錫膏印刷孔 (Screen Holes)的____直..,彳呈會變得比真實的錫錯&塊要來得大 所造成的結果,上述之錫錯凸塊體積大幅縮減也會造成錫 膏印刷技術在製造高密度元件所面臨的困難。 其它能製造錫鉛凸塊的技術尚有C4技術(Controlled4 184 TO Five 'invention description (2) t-assembly, in which the above-mentioned tin-lead bump contacts are arranged in a surface matrix (' Area Array) on the surface of the die, which can improve the wafer's I / 0 ratio, and currently Methods for making tin-lead bumps include evaporation, electroplating, printing, electrodeposition, or other methods. The electrodeposition method is a new technology that has only been developed in recent years. In addition to the above technologies, there are other technologies that can grow tin-lead bumps on various substrates, such as one of the solder paste printing technologies (Solder-Paste Screening M ethod) commonly used in 8 11-inch wafer packaging. ) 'However, with the reduction in component size and the reduction of the pitch of tin-lead bumps, solder paste printing becomes impractical due to the following reasons. The first point is when used This solder paste printing technology is often bonded by the emperor compound when bonding tin-lead bumps to the substrate. This is because the solder paste (S ο 1 der Paste) is made of a flowable (F 1 u X) material and The solder (S ο 1 der) alloy particles are formed, so it is very difficult to control the concentration and uniformity of the solder paste compound when the volume of tin-lead bumps is reduced. For this reason, the conventional method has disclosed Fine particles with uniform particle size can improve the disadvantages mentioned above, but this will inevitably increase the production cost. The second point is that when using this solder paste printing technology to manufacture high-density semiconductor components, two tin-lead bumps will be produced. Of The space between them becomes very limited. This is because the volume of the tin will be greatly reduced when the tin changes from a flowing state to a solid state, making the solder paste screen holes (Screen Holes) ____straight .. As a result of the large tin fault & block coming, the significant reduction in the volume of the aforementioned tin fault bumps will also cause difficulties in solder paste printing technology in manufacturing high density components. Other technologies that can produce tin-lead bumps are C4 technology (Controlled
4 184T j_ 五、發明說明¢3)4 184T j_ V. Description of invention ¢ 3)
Col lapse Chip Connection Technique)與薄膜沉積技術 (Thin Film Electrodeposition Technique)也都已經在 最近幾年被應用於半導體元件的製造,其中C4技術受限於 在製造過程中必需使用鉬光罩(Molybdeum Mask)以定義 - BLM層與錫鉛凸塊的圖形大小,因鉬光罩對位之精確度不_ ,因此要以C 4技術製造微細間距(亦即間距< 1 5 0 μ m )錫/ 鉛凸塊是件困難的事。相同地,薄膜沉積技術也受限於在 製程中必需沉積一 B L Μ層並在其上塗佈一層厚光阻,因厚 光阻在對位上準確度較差’因此也具有與C4相同無法製成 微細間距錫鉛凸塊的缺點’其中習知利用薄膜沉積技術以 製造錫鉛球的製造流程圖如「第1 Α〜1 F圖」所示。 其中一種習知的半導體結構10如「圖1A」所示,此半 導體結構10是建立於一矽基板12之上,其製造方法是先在 石夕基.板12之頂部表面16形成一焊塾(Bonding Pad)14,用 以當成矽基板1 2與外面基板線路之間的電氣連接,此焊墊 14是由導電金屬材質(如鋁’A1)製成,接著沉積一保護層 2 0於矽基板1 2 ’用以保護焊墊1 4,其中此一保護層2 0係由 一絕緣材質如氧化物、氮化物或是有機材料所製成,然後 再利用微影技術在保護層2 0上開出欲當電氣連接的視窗2 2 〇 接著在保護層20之頂部表面24與焊墊14所裸露之頂部 表面18上都沉積一焊接金屬墊層(Ball Limiting Metallurgy ,BLM ’ 其中BLM 也可稱為UBM ,Under Bump Metallurgy ’)層26 (如圖IB所示),此blM層26是由一黏Col lapse Chip Connection Technique and Thin Film Electrodeposition Technique have also been applied to the manufacture of semiconductor components in recent years. Among them, the C4 technology is limited to the use of molybdeum masks in the manufacturing process. By definition-The pattern size of the BLM layer and the tin-lead bumps is not precise because of the alignment of the molybdenum mask. Therefore, the fine pitch (that is, the pitch < 150 μm) of tin / lead must be manufactured by C 4 technology. Bumps are difficult. Similarly, the thin film deposition technology is also limited to the need to deposit a BL LM layer and coat a thick photoresistor on the process, because the thick photoresistor has poor accuracy in alignment, so it also has the same unmanufacturability as C4. Disadvantages of forming fine-pitch tin-lead bumps' The manufacturing flow chart of conventionally using thin-film deposition technology to manufacture tin-lead balls is shown in "Figure 1A ~ 1F". One of the conventional semiconductor structures 10 is shown in FIG. 1A. This semiconductor structure 10 is built on a silicon substrate 12, and its manufacturing method is to first form a soldering pad on the top surface 16 of the substrate. (Bonding Pad) 14 is used as an electrical connection between the silicon substrate 12 and the outer substrate circuit. This pad 14 is made of a conductive metal material (such as aluminum 'A1), and then a protective layer 20 is deposited on the silicon. The substrate 1 2 ′ is used to protect the bonding pads 14. The protective layer 20 is made of an insulating material such as oxide, nitride, or organic material, and then the photolithography technology is used on the protective layer 20. A window 2 2 is opened to be electrically connected, and then a welding metal pad layer (BLM) can be deposited on the top surface 24 of the protective layer 20 and the exposed top surface 18 of the pad 14 (BLM can also be called Is UBM, Under Bump Metallurgy ') layer 26 (as shown in Figure IB), this blM layer 26 is made of a glue
4184T0 五、發明說明(4) 附防止擴散層(Adhe.s ion Diffusion Barrier Layer)30 與一濕潤層(Wetting Layer,亦可稱為沾錫層)28構成, 其中黏附.防止擴散層3 0可由鈦(T i )、氮化鈦(T i N )、銘_ ( c r )或是其他金屬材質之一製成,而濕潤層28可由銅(cu)咬. 鎳(Ni)等材料之一製成,其中上述BLM層26主要是用以改 善即將形成的錫鉛球與焊墊1 4之頂部表面1 8之間的沾黏關· 係。 如圖1 C所示,在此步驟中係將一厚光阻劑層3 4沉積於 BLM層26表面,再利用曝光、顯影的方式,定義出—欲θ長' 錫鉛球的視窗開孔38,接著再以電鍍方式於此視窗開孔^ 形成一錫鉛凸塊4 0,前述光阻劑層3 4的厚度一般都維持在 3 0 μ m〜4 0 // m之間,較佳是維持在3 5 # m左右,此—光阻 劑層3 4的厚度與疋否能製成微細間距锡錯凸塊4 〇有關,奋 所使用的光阻劑層3 4愈厚,其對位準確率愈差,較難製^ 微細間距錫鉛凸塊4 0,但又因光阻劑層3 4厚度與錫鉛凸塊 4 0的高度成正比關係,因此光阻劑層3 4必需要有一定的尸 度,故必須謹慎選擇光阻劑層3 4的厚度,而在此步驟中係 選用一足夠薄的光阻劑層34而製成一香菇狀的錫鉛凸4〇 ,如圊1 D所示d 如圖1E所示’當形成錫鉛凸塊4〇之後 ,〜一 1 UΊ又’巾一屬 光阻砍程(Wet Stripping proceSs)移去光阻劑層34, 時香菇狀錫鉛凸塊40與81^層26都維持原狀’接著 下:步驟,如圖1 F所示’在此步驟中是利用錫鉛凸魂u 光罩,利用濕式蝕刻製程將多餘的Bu層2 6蝕刻乾淨,接、'、4184T0 V. Description of the invention (4) An anti-diffusion layer (Adhe. Ion diffusion barrier layer) 30 and a wetting layer (also known as a tin layer) 28 are formed, wherein the adhesion. The anti-diffusion layer 30 may be Titanium (Ti), titanium nitride (TiN), Cr (Cr) or other metal materials, and the wet layer 28 can be bitten by copper (Cu). Nickel (Ni) and other materials The BLM layer 26 is mainly used to improve the adhesion relationship between the tin-lead ball to be formed and the top surface 18 of the pad 14. As shown in FIG. 1C, in this step, a thick photoresist layer 34 is deposited on the surface of the BLM layer 26, and then the exposure and development methods are used to define the window opening 38 of the tin-lead ball to be θ long. Then, a hole is formed in this window by electroplating ^ to form a tin-lead bump 40. The thickness of the aforementioned photoresist layer 34 is generally maintained between 30 μm and 4 0 // m, preferably Maintained at about 3 5 # m, this—the thickness of the photoresist layer 34 is related to whether or not a fine-pitch tin bump 4 can be made. The thicker the photoresist layer 34 is, the more it is aligned. The worse the accuracy, the more difficult it is to make ^ fine-pitch tin-lead bumps 40, but because the thickness of the photoresist layer 34 is directly proportional to the height of the tin-lead bumps 40, the photoresist layer 3 4 must be There is a certain degree of corpse, so the thickness of the photoresist layer 34 must be carefully selected. In this step, a sufficiently thin photoresist layer 34 is used to make a mushroom-shaped tin-lead bump 40, such as 圊As shown in FIG. 1D, as shown in FIG. 1E, after the formation of the tin-lead bump 40, ~ 1 UΊ is a photoresist cutting process (Wet Stripping proceSs) to remove the photoresist layer 34. tin The bumps 40 and the 81 ^ layer 26 are maintained in their original state. 'Next: Step, as shown in Figure 1 F.' In this step, a tin-lead convex soul U mask is used, and the excess Bu layer is wet-etched using a wet etching process. 2 6 Etching clean, then, ',
4184 70 五、發明說明(5) 著利用一重流製程(R e f 1 〇 w P r 〇 c e s s )以高於錫錯β塊4 0熔-點的溫度加熱錫鉛凸塊4 0,使錫鉛凸塊4 0由固態變成液態 ,最後在冷卻的過程中使錫鉛凸塊4 0因本身的内聚力而形 成一球狀的錫鉛球42,至此步驟,即完成錫鉛球42的製造 ,如圖1 F所示。 但是上述以電鍍技術製造錫鉛凸塊的方式卻有若干不' 佳之處,如下所述:第一點是習知香菇狀錫鉛凸塊的體積 限制了微細化的製程,其中微細間距錫鉛凸塊的意義是兩 錫鉛凸塊之間的距離至少要小於1 5 0 y m,最好是小於1 2 0 // m,但是依照上述之製造方法,錫錯凸塊是先形成,接 著再藉由一濕式蝕刻製程將沉積於錫鉛凸塊下方的B L Μ層 移除,因此當微細錫鉛凸塊形成於B L Μ層欲留之視窗開口 時,因兩錫鉛凸塊之間的間距很小,因此要在這麼細小的 間距内完全去除BLM層是一件很困難的事,為達此一目的 ,大都將姓刻時間增長以完全去除B L Μ層,但如此一來, 有可能會因蝕刻時間過長而蝕刻至錫鉛凸塊或是造成錫鉛 凸塊的嚴重氧化;第二點是厚光阻劑層在對位的精確度上 較差,有可能導致因鋁墊片裸露而影響錫鉛凸塊的可靠度 ,由於錫錯凸塊接點的疲勞壽命(Fatigue Life)是與錫錯 凸塊高度成(大於1次方)成正比,因此在製造錫鉛凸塊 時都會增加錫錯球的高度,以增加錫鉛凸塊接點的疲勞壽 命,但如此一來,勢必要增加光阻劑層的厚度,但厚光阻 劑層在對位的準確度較差,且有可能會蝕刻至鋁墊片,使 鋁墊片裸露於外而影響錫鉛凸塊的品質與可靠度。4184 70 V. Description of the invention (5) Using a heavy-flow process (R ef 1 〇w P r cess) to heat the tin-lead bump 40 at a temperature higher than the melting point of the tin-block β block 4 0 to make tin-lead The bump 40 changes from a solid state to a liquid state. Finally, during the cooling process, the tin-lead bump 40 forms a spherical tin-lead ball 42 due to its cohesion. At this step, the manufacture of the tin-lead ball 42 is completed, as shown in FIG. 1 F. However, the above-mentioned method of manufacturing tin-lead bumps by electroplating technology has several disadvantages, as follows: The first point is that the volume of the conventional mushroom-shaped tin-lead bumps limits the miniaturization process, among which fine-pitch tin-lead The meaning of the bump is that the distance between the two tin-lead bumps must be at least less than 150 μm, and preferably less than 1 2 0 // m. However, according to the above manufacturing method, the tin bumps are formed first, and then The BL Μ layer deposited under the tin-lead bump is removed by a wet etching process. Therefore, when the fine tin-lead bump is formed in the opening of the window to be left by the BL Μ layer, due to the The pitch is very small, so it is very difficult to completely remove the BLM layer in such a small pitch. To achieve this purpose, most of the time is increased by the time of the last name to completely remove the BL Μ layer, but in this case, it is possible It will etch to the tin-lead bumps or cause severe oxidation of the tin-lead bumps due to the long etching time; the second point is that the thick photoresist layer has poor alignment accuracy, which may cause the aluminum gasket to be exposed Which affects the reliability of tin-lead bumps, The fatigue life of a point is directly proportional to the height of the tin bump (greater than the power of 1). Therefore, the height of the tin bump is increased when the tin-lead bump is manufactured to increase the contact of the tin-lead bump. Fatigue life, but in this case, it is necessary to increase the thickness of the photoresist layer, but the alignment accuracy of the thick photoresist layer is poor, and it may etch into the aluminum gasket, leaving the aluminum gasket exposed. Affects the quality and reliability of tin-lead bumps.
f 418470 五、發明說明(6) 【發明之目的及概述】 有鑑於此,本發明之主要目的在於提供一種覆晶焊料 球的製造方法,以改善習知製造方法所無法製成之具微細 間距焊料球以及產生厚光阻劑層對位不準、焊料球被氧化 等問題。 本發明之另一目的在於提供一種至少使用兩次微影技 術之具微細間距覆晶焊料球的製造方法。 本發明之另一目的在於提供一種在焊料球建立前先使 BLM層對位之具微細間距覆晶焊料球的製造方法。 本發明之另一目的在於提供一種能使焊料球之間距小 於1 2 0以m之具微細間距覆晶焊料球的製造方法。 本發明之另一目的在於提供一種使用兩次微影技術之 具微細間距覆晶焊料球的製造方法,其中第一次微影技術 是以薄光阻劑將B L Μ層定義至所需的位置,而第二次微影 技術則是以厚光阻劑開出欲長焊料凸塊的開孔。 本發明之另一目的在於提供一種使用雙重微影技術之 具微細間距覆晶焊料球的製造方法,其中先在欲形成焊料 之焊墊上方塗覆一層BLM層,再利用濕式蝕刻製程準確地 將B L Μ層去除。 本發明之另一目的在於提供一種使用雙重微影技術之 具微細間距覆晶焊料球的製造方法,其中非可融性(non-leachable)金屬層(如銅,Cu或鉻,Cr)最後被沉積於被ϋ 刻之BLM層的頂部,用以當做電鍍時之電極使用。 本發明之另一目的在於提供一種具微細間距之覆晶焊f 418470 V. Description of the invention (6) [Objective and summary of the invention] In view of this, the main purpose of the present invention is to provide a method for manufacturing flip-chip solder balls to improve the fine pitch that cannot be made by conventional manufacturing methods. Problems such as misalignment of the solder ball and the thick photoresist layer, and oxidation of the solder ball. Another object of the present invention is to provide a method for manufacturing a fine-pitch flip-chip solder ball using lithography at least twice. Another object of the present invention is to provide a method for manufacturing a fine-pitch flip-chip solder ball having a fine pitch aligned with the BLM layer before the solder ball is established. Another object of the present invention is to provide a manufacturing method capable of making the pitch of solder balls with a fine pitch smaller than 120 m between them. Another object of the present invention is to provide a method for manufacturing a fine-pitch flip-chip solder ball using two lithography techniques. The first lithography technique uses a thin photoresist to define a BL Μ layer to a desired position, and The second lithography technique uses a thick photoresist to open the openings of the solder bumps to be grown. Another object of the present invention is to provide a method for manufacturing a micro-pitch flip-chip solder ball using dual lithography technology, in which a BLM layer is first coated on a solder pad to be formed, and then the wet etching process is used to accurately The BL M layer was removed. Another object of the present invention is to provide a method for manufacturing a fine-pitch flip-chip solder ball using dual lithography technology, in which a non-leachable metal layer (such as copper, Cu, or chromium, Cr) is finally It is deposited on top of the engraved BLM layer and used as an electrode in electroplating. Another object of the present invention is to provide a flip chip welding with a fine pitch.
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4184 TO 五、發明說明(7) 料球的製造方法,其中焊料球是藉由包含有非可融性金屬 離子(如Cu或Cr)的界面而與BLM層相連接。 為達上述之目的,本發明揭露一種覆晶焊料球的製造 方法,至少包括下列步驟:提供一頂部形成有金屬焊墊的· 基板,其中焊墊除頂部裸露於外其餘的部份皆埋入於一絕 緣層;沉積一 BLM層於基板的表面;塗覆一第一光阻劑層— 於BLM層表面,其中第一光阻劑層具有一第一厚度,第一 厚度必需要很薄,以使曝光準確率至少在± 2 // m ;蝕刻掉 沉積於焊墊以外區域的BLM層中之濕潤層;塗覆一第二光 阻劑層於被蝕刻之BLM層的頂面,其中第二光阻劑層有一 第二厚度,第二厚度大於第一厚度,並在第二光阻劑層上 形成一開孔,並將一焊料注入開孔以形成一柱狀之焊料凸 塊;以及去除第二光阻劑層並經重流製程使柱狀之焊料凸 塊因本身的内聚力而形成一球狀之焊料球,至此步驟,即 完成焊料球的製造。 其中焊料球可由錫鉛合金或是其它焊料合金製成,且 上述本發明所揭露之製造步驟中,尚可包括一金屬沉積製 程,係指在未塗覆第二光阻劑層之前,先在被蝕刻之B L Μ 層表面上沉積一非可融性金屬層(None-Leachable Metal L a y e r ),此一非可融性金屬層係由不會被焊料凸塊融解的 金屬形成,一般都由高導電性的材料製成,如Cu或Νι等, 而其厚度不能超過1/zm,一般都是在0.01/zm〜lym之間, 較佳的是在0.05μιη 之間。 上述提及之BLM層是由2〜3層不同金屬構成,其分別是4184 TO V. Description of the Invention (7) A method for manufacturing a ball, wherein the solder ball is connected to the BLM layer through an interface containing non-meltable metal ions (such as Cu or Cr). In order to achieve the above-mentioned object, the present invention discloses a method for manufacturing a flip-chip solder ball, which includes at least the following steps: providing a substrate with a metal pad formed on the top thereof, wherein all parts of the pad except the top are exposed are buried; On an insulating layer; depositing a BLM layer on the surface of the substrate; coating a first photoresist layer on the surface of the BLM layer, wherein the first photoresist layer has a first thickness, the first thickness must be very thin, So that the exposure accuracy is at least ± 2 // m; etch away the wet layer deposited in the BLM layer outside the pad; apply a second photoresist layer on the top surface of the etched BLM layer, where the first The two photoresist layers have a second thickness, the second thickness is greater than the first thickness, an opening is formed in the second photoresist layer, and a solder is injected into the opening to form a columnar solder bump; and The second photoresist layer is removed and the columnar solder bumps are formed into a spherical solder ball due to the cohesive force of the columnar solder bump through a heavy-flow process. At this step, the manufacture of the solder ball is completed. The solder ball may be made of tin-lead alloy or other solder alloys, and the manufacturing steps disclosed in the present invention may further include a metal deposition process, which means that before the second photoresist layer is coated, A non-leachable metal layer (None-Leachable Metal Layer) is deposited on the surface of the etched BLM layer. This non-meltable metal layer is formed of a metal that will not be melted by solder bumps. It is made of conductive material, such as Cu or Ni, and its thickness cannot exceed 1 / zm, it is generally between 0.01 / zm ~ lym, preferably between 0.05 μm. The BLM layer mentioned above is composed of 2 ~ 3 layers of different metals, which are
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4184 TO 五、發明說明(8) 黏附防止擴散層(Adhesion Diffusion Barrier Layer) ,此層具有兩個功用,其一是當成擴散防止層,用以防止 焊料(如錫、鉛)的擴散,其二是當成黏附層,用以與鋁焊 墊及焊料形成較強的黏著性,其中此黏附防止擴散層可由 C r或Τ ί等金屬製成;以及濕潤層(Β ο n d 1 n g 〇 r W e 11 i n g Layer),其可由Cu、Pd、Pt或Ni等金屬製成;而上述之第 一光阻劑層的厚度最好不要超過l〇Vm,當然最好的是在2 "m〜5 # m之間,而第二光阻劑層是用以開出欲長烊料球的 開孔以及提供焊料球所需的高度,為了要增加焊料球的可 靠性,都會在製造過程中藉由增加此光阻劑層的厚度以增 加焊料球的高度,因此第二光阻劑層的厚度最好不要低於 5 0 # m,而將焊料注入開孔中以形成焊料球的步驟係由電 鍍方式形成。 雖然上述所揭露的是一種覆晶焊料球的製造方法,但 是此一方法也可應用於在矽晶圓上成長微細間距焊料凸塊 的製造方法,至少包括下列步驟:提供一頂部形成有複數 個金屬焊墊的矽晶圓;沉積一 BLM層於該些金屬焊墊的頂 面,並塗覆一第一光阻劑層於B L Μ層表面,同時將欲形成 之圖案定義於第一光阻劑層,其中第一光阻劑層的塗佈厚 度小於1 0 V m ;於第二光阻劑層上定義及形成複數個開孔 ;於該些開孔内注入一焊料以形成複數個谭料凸塊;以及 移除第二光阻劑層,至此步驟即完成具微細間距之矽晶圓 焊料凸塊的製造。 之後使焊料凸塊經一重流製程使焊料凸塊因本身的内4184 TO V. Description of Invention (8) Adhesion Diffusion Barrier Layer This layer has two functions. One is to act as a diffusion prevention layer to prevent the diffusion of solder (such as tin and lead). It is used as an adhesion layer to form strong adhesion with aluminum pads and solders. The adhesion prevention diffusion layer can be made of metals such as C r or Τ ί; and a wet layer (B ο nd 1 ng 〇r W e 11 ing Layer), which can be made of metals such as Cu, Pd, Pt, or Ni; and the thickness of the above-mentioned first photoresist layer is preferably not more than 10Vm, and of course, the best is between 2 " m ~ 5 # m, and the second photoresist layer is used to open the opening of the long ball and provide the height required for the solder ball. In order to increase the reliability of the solder ball, it will be used in the manufacturing process by Increasing the thickness of this photoresist layer to increase the height of the solder ball, so the thickness of the second photoresist layer is preferably not less than 50 # m, and the step of injecting solder into the opening to form the solder ball is performed by electroplating Way to form. Although what is disclosed above is a method for manufacturing flip-chip solder balls, this method can also be applied to a method for manufacturing fine-pitch solder bumps on a silicon wafer, including at least the following steps: providing a plurality of top portions Silicon wafers with metal pads; a BLM layer is deposited on the top surfaces of the metal pads, and a first photoresist layer is coated on the surface of the BL M layer, and the pattern to be formed is defined in the first photoresist Agent layer, wherein the coating thickness of the first photoresist layer is less than 10 V m; defining and forming a plurality of openings on the second photoresist layer; injecting a solder into the openings to form a plurality of tans Material bumps; and removing the second photoresist layer, so far this step completes the manufacture of the fine-pitch silicon wafer solder bumps. After that, the solder bump is subjected to a heavy-flow process to make the solder bump due to its internal
第12頁 .A184TQ_ 五'發明說明(9) 聚力而形成一球狀的焊料球,而焊料可以由錫鉛合金或是 其他的焊料合金製成,且上述製程尚可包括一金屬沉積製 程,係指在未塗覆第二光阻劑層之前,先在被蝕刻之B L Μ 層表面上沉積一非可融性金屬層,此一非可融性金屬層是 由高導電性的材料製成,如Cu或Ni等,而其厚度不能超過 lym,一般都是在0.01/zm~l/2m之間,最好的是在0.05// m〜0 · 3 y m之間。 在上述所揭露之B L Μ層是由一黏附防止擴散層與一濕 潤層所構成,BLM層可選擇性地由Ti/Cu、TiN/Cu、Cr/Ni 、A1/Ni-V/Cu或是Cr/CrCu/Cu/Au製成,而焊料球的材質 係由S η與P d組成。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂,下文特舉一較佳實施例,並配合所附圖式,作詳細 說明如下: 【圊式簡單說明】 第1 A〜1 F圖,係為習知利用薄膜沉積技術以製造錫鉛 球的製造流程圖; 第2圖,係為本發明製造錫鉛球的方塊流程圖; 第3 A〜3 I圖,係為本發明製造錫鉛球之每一製造步驟 的剖面圖;以及 第4 A ~ 4 I圖,係為本發明之另一種製造錫鉛球之每一 製造步驟的剖面圖 【實施例說明】 在本發明所揭露之覆晶焊料球的製造方法中,是藉由Page 12. A184TQ_ Five 'Description of the Invention (9) Converge to form a spherical solder ball, and the solder can be made of tin-lead alloy or other solder alloys, and the above process can also include a metal deposition process, It means that before the second photoresist layer is applied, a non-meltable metal layer is deposited on the surface of the BL BL layer being etched. This non-melt metal layer is made of a highly conductive material , Such as Cu or Ni, and its thickness cannot exceed lym, generally between 0.01 / zm ~ l / 2m, and most preferably between 0.05 // m ~ 0 · 3 ym. The BL LM layer disclosed above is composed of an adhesion prevention diffusion layer and a wetting layer. The BLM layer can be selectively made of Ti / Cu, TiN / Cu, Cr / Ni, A1 / Ni-V / Cu or Cr / CrCu / Cu / Au, and the material of the solder ball is composed of S η and P d. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: [Simple description of the formula] Section 1 A ~ Figure 1 F is a flow chart of the conventional manufacturing process of tin-lead balls using thin film deposition technology; Figure 2 is a block flow chart of the tin-lead ball manufacturing process of the present invention; Figures 3 A to 3 I are manufacturing processes of the present invention A cross-sectional view of each manufacturing step of the tin-lead ball; and FIGS. 4A to 4I are cross-sectional views of each manufacturing step of the tin-lead ball manufacturing method of the present invention. In the method of manufacturing crystal solder balls,
第13頁 A184T0 五、發明說明(ίο) 一種唯一且新奇的雙重微影技術並配合雙重光阻劑層以達 到製成微細焊料球的目的,在第一次微影技術中,是先在 BLM層上塗覆一層薄光阻劑,利用曝光及顯影的方式,定 義欲長錫鉛凸塊之位置,之後再將此薄光阻連同位於焊墊-之外的B L Μ層之濕潤層去除;而在第二次微影技術中,則 是在BLM層上塗覆一層厚光阻劑,利用曝光及顯影的方式 ,定義出欲長焊料凸塊的開孔及所長之焊料凸塊的高度; 一般而言,第一光阻劑層的厚度最好不要超過10/zm,當 然最好的是在2 # m〜5 // m之間,其原因是當使用厚光阻劑 (亦即厚度大於5 0 // m )時,常會伴隨有曝光/聚焦等問題的 發生,使得對位的精確度較差,因此本發明使用一薄光阻 當第一光阻劑層,可以避免曝光/聚焦等問題的發生,而 使對位變得十分準禮,以製成微細間距的錫船球。 而在第二微影技術中所使用的厚光阻,是用以開出欲 長焊料凸塊的開孔以及提供焊料凸塊所需的高度,一般所 使用之厚光阻的厚度大都大於50 //m。 如前述曾提及在本發明之製造步驟中尚可包含一金屬 沉積製程,係在B L Μ層與焊料球之間沉積一非可融性金屬 層,用以當作電鍍時之電極,而此一非可融性金屬層的厚 度很薄,大約是小於1 # m,一般大都在0 . 0 1 y m〜1 μ m之 間,最好是在0.05 /zm〜0.3 //in之間。 其中本發明所揭露之BUi層是由2〜3層不同金屬構成, 其分別是黏附防止擴散層、濕潤層以及保護層 (Protecting Layer),而BLM層可以由Ti/Cu 、TiN/Cu ,CrPage 13 A184T0 V. Description of the Invention (() A unique and novel double lithography technology combined with a double photoresist layer to achieve the purpose of making fine solder balls. In the first lithography technology, it was first in the BLM A thin photoresist is coated on the layer, and the positions of the tin-lead bumps to be grown are defined by the way of exposure and development, and then the thin photoresist is removed together with the wet layer of the BL Μ layer located outside the pad-; In the lithography technology, a thick photoresist is applied on the BLM layer, and the exposure and development methods are used to define the openings of the solder bumps and the height of the solder bumps. Generally speaking, the first The thickness of the photoresist layer is preferably not more than 10 / zm, and of course the best is between 2 # m ~ 5 // m, the reason is that when using a thick photoresist (that is, the thickness is greater than 5 0 // m ), It is often accompanied by problems such as exposure / focus, which makes the alignment accuracy worse. Therefore, the present invention uses a thin photoresist as the first photoresist layer, which can avoid the problems of exposure / focus and so on. Be polite to make fine pitch tin Ball. The thick photoresist used in the second lithography technology is used to open the openings for the solder bumps and provide the height required for the solder bumps. Generally, the thickness of the thick photoresist used is more than 50 // m. As mentioned earlier, the manufacturing steps of the present invention may further include a metal deposition process, which is to deposit a non-meltable metal layer between the BL MM layer and the solder ball, which is used as an electrode during electroplating. The thickness of a non-fusible metal layer is very thin, about less than 1 # m, and it is generally between 0.01 μm and 1 μm, and preferably between 0.05 / zm and 0.3 // in. The BUi layer disclosed in the present invention is composed of 2 to 3 layers of different metals, which are an adhesion prevention diffusion layer, a wetting layer, and a protective layer, respectively. The BLM layer can be made of Ti / Cu, TiN / Cu, and Cr.
第14頁 4184 70 五、發明說明(11) /Ni 、A1/Ni-V/Cu 、Cr/CrCu/Cu/Au或是其它的金屬製成, 其中在本發明中係利用一滅鍵製程在基板表面沉積一 B L Μ 層,並在隨後製程中將位於焊墊之外的BLM層去除。 請配合「第2圖」所繪示的方塊流程圖與「第3 Α〜3 I圖 」所繪示之每一製造步驟的剖面圖來加以說明本發明製造 微細錫鉛球的製造方法。其中在本發明所揭露的實施例〆 是以錫鉛合金製成焊料凸塊及焊料球,因此在後續相關說 明中以錫鉛凸塊與錫鉛球來代替,首先請參閱第2圖的第 一步驟5 2與「第3 A圖」來說明第一製造步驟,其中晶圓7 0 包括有一 I呂焊塾(Aluminum bond pad)72,其形成於晶圓 70之頂部表面74以及一保護層76,其中鋁焊墊72的表面至 少具有一裸露於外的區域以供錫鉛凸塊成長,藉此錫鉛凸 塊當電氣連接以使鋁焊墊7 2能與基板線路接合。 請繼續配合第2圖的第二步驟54與「第3B圖」來說明 第二製造步驟,在此步驟中,係在保護層7 6與鋁焊墊7 2裸.. 露於外區域之上方沉積一BLM層80,此BLM層80包含有 層不同金屬構成,其分別是黏附防止擴散層、濕潤層(或 稱為沾錫層)以及保護層(使用者可視情況而選擇是否要沉 積此層),而在本實施例中所使用的B L Μ層8 0只包括有黏附 防止擴散層8 2與濕潤層8 4,並將其沉積於保護層7 6的頂面 與鋁焊墊72裸露於外的頂面,當然如前述曾提及BLM層80 也可包含一保護層(未標示),只是這是在使用某些金屬的 前題下才需要包含此層,例如當黏附防止擴散層8 2的材質 是由C r或T i製成,而濕潤層8 4是由C u、P d、P t或N i製成時Page 14 4184 70 V. Description of the invention (11) / Ni, A1 / Ni-V / Cu, Cr / CrCu / Cu / Au or other metals, in which in the present invention a bond extinction process is used in A BLM layer is deposited on the substrate surface, and the BLM layer located outside the pads is removed in a subsequent process. Please refer to the block flow chart shown in "Figure 2" and the cross-sectional view of each manufacturing step shown in "Figures 3 Α ~ 3 I" to explain the method for manufacturing the fine tin lead ball of the present invention. In the embodiment disclosed in the present invention, solder bumps and solder balls made of tin-lead alloy are used. Therefore, in the following related description, tin-lead bumps and tin-lead balls are used instead. First, refer to the first figure in FIG. 2 Step 5 2 and “3A” illustrate the first manufacturing step. The wafer 70 includes an aluminum bond pad 72 formed on the top surface 74 of the wafer 70 and a protective layer 76. Wherein, the surface of the aluminum pad 72 has at least an exposed area for the tin-lead bump to grow, whereby the tin-lead bump is electrically connected so that the aluminum pad 72 can be bonded to the substrate circuit. Please continue to cooperate with the second step 54 in Figure 2 and "Figure 3B" to explain the second manufacturing step. In this step, the protective layer 76 and the aluminum pad 7 2 are exposed .. Exposed above the outer area A BLM layer 80 is deposited. The BLM layer 80 includes different layers of metal, which are an adhesion prevention diffusion layer, a wetting layer (also called a tin dip layer), and a protective layer (the user can choose whether to deposit this layer according to the circumstances) ), And the BL M layer 80 used in this embodiment only includes an adhesion prevention diffusion layer 82 and a wetting layer 84, and is deposited on the top surface of the protective layer 76 and the aluminum pad 72 is exposed on The outer top surface, of course, as mentioned above, the BLM layer 80 may also include a protective layer (not labeled), but this is only required under the premise of using some metals, such as when the adhesion prevention diffusion layer 8 When the material of 2 is made of C r or T i and the wet layer 8 4 is made of C u, P d, P t or Ni
第15頁 41847〇 五、發明說明(12) ,此時為恐在後鍍錫鉛凸塊之前會有濕潤層8 4的表層被氧- 化的顧慮,因此一般會在鍍完濕潤層8 4後再鍍上一保護層 ,以避免濕潤層8 4被氧化,其中上述保護層係由貴金屬( 、 —— 如Au、Pt)材質製成。 - 請繼續配合第2圖的第三步驟5 6與「第3 C圖」來說明 第三製造步驟,在此步驟中係以沉積或塗佈方式在BLM層 8 0之上形成第一光阻劑層9 0,此第一光阻劑層9 0的厚度最 好不要超過10 /im,其較佳是在2 /zm〜5 /zm之間,由於此第 一光阻劑層9 0可以允許在B L Μ層8 0上進行高準確的顯影技 術,亦即此第一光阻劑層9 0可使對位變得十分準確,因此 可以準確地決定出欲長錫鉛凸塊的位置,而此位置就是在 鋁焊墊7 2的中心點附近,其中上述之光微影的方法是藉由 一光罩(Photomask)92以正確決定出欲長錫鉛凸塊的位置 ,亦即在此位置上方覆蓋有光罩92,利用在UV Light下曝 光及顯影技術將光罩92上的圖案轉移至BLM層80上方,再 利用濕式蝕刻或乾式蝕刻將未被光罩9 2覆蓋之濕潤層8 4去 除,此步驟即為第2圖之第四步驟5 8 ,而其剖面圖如「第 3 D圖」所示,但是在此步驟中有一點需特別注意,即在 B L Μ層8 0被蝕刻時,只蝕刻上層而保留底層,這是因為底 層材質是C r或T i ,可以在後續進行電鍍過程中當作電極使 用。 請繼續配合第2圖的第五步驟6 0與「第3 E圖」來說明 第五製造步驟,在此步驟中係在晶圓7 0上方沉積第二光阻 劑層1 0 0 ,其中由於此第二光阻劑層1 0 0的高度與所形成之Page 15 41847 05. Description of the invention (12) At this time, there is a concern that the surface layer of the wet layer 8 4 will be oxidized before the tin-lead bump is plated. Therefore, the wet layer 8 4 is generally finished after plating. After that, a protective layer is plated to prevent the wet layer 84 from being oxidized. The above protective layer is made of precious metals (, such as Au, Pt). -Please continue to cooperate with the third step 5 of Figure 2 and "3C" to explain the third manufacturing step. In this step, a first photoresist is formed on the BLM layer 80 by deposition or coating. Agent layer 90, the thickness of the first photoresist layer 90 is preferably not more than 10 / im, it is preferably between 2 / zm ~ 5 / zm, because the first photoresist layer 90 can Allows highly accurate development technology on the BL Μ layer 80, that is, the first photoresist layer 90 can make the alignment very accurate, so it can accurately determine the position of the tin-lead bump to be grown. And this position is near the center point of the aluminum pad 72, where the above-mentioned method of photolithography is to correctly determine the position of the tin-lead bump by a photomask 92, that is, here A mask 92 is covered above the position. The pattern on the mask 92 is transferred to the BLM layer 80 by exposure and development under UV Light, and then the wet layer that is not covered by the mask 9 2 is wet-etched or dry-etched. 8 4 is removed, this step is the fourth step 5 8 in FIG. 2, and the sectional view is as shown in FIG. 3 D, but in this step That need special attention, i.e. when B L Μ layer 80 is etched, etching only the upper layer and the underlying retention, because the bottom layer material or is C r T i, the electroplating process may be used as an electrode in a subsequent. Please continue to cooperate with the fifth step 60 in FIG. 2 and the “FIG. 3E” to explain the fifth manufacturing step. In this step, a second photoresist layer 1 0 0 is deposited on the wafer 70, where The height of the second photoresist layer 100 and the formed
第16頁 4104 70 五、發明說明(13) 錫鉛凸塊的高度有關,且錫鉛凸塊的高度與其可靠度成正-比,因此為了要獲得較高的可靠度,都會藉由增加第二光 阻劑層1 0 0的高度以形成較高的錫鉛凸塊,而一般所使用 之第二光阻劑層100的厚度大都超過50 μηι ;在第五步驟結' 束後,接著再利用第二光罩1 〇 2定義出欲長錫鉛凸塊的開 孔110,如圖2之第六步驟62及「第3F圖」所示。 接著再利用電鍍方式將由Sn與Pd所組成的焊料注入上 述開孔1 1 0中而形成一柱狀的錫鉛凸塊1 2 0,如圖2之第七 步驟6 4及「第3 G圖」所示,之後再將第二光阻劑層1 0 0去 除,並藉由一重流製程(Reflow Process) 以高於錫错凸 塊1 2 0熔點的溫度加熱錫鉛凸塊1 2 0,使錫鉛凸塊1 2 0由固 態變成液態,最後在冷卻的過程中使柱狀的錫鉛凸塊1 2 0 因本身的内聚力而形成一球狀的錫鉛球1 3 0,如圖2之第八 步驟68及「第3H圖」所示。 最後請繼續配合第2圖的第九步驟6 6與「第3 I圖」來 說明第九製造步驟,在此步驟中是利用一蝕刻製程(可為 濕式或是乾式蝕刻)將其它多餘的黏附防止擴散層8 2去除 ,至此即完成覆晶錫鉛球的製造;其中在本發明所揭露的 方法中,第八步驟6 8之重流焊料與第九步驟6 6之蝕刻B L Μ 層的步驟是可以對調的,亦即可以先利用一蝕刻製程去除 黏附防止擴散層8 2,再經重流製程形成球狀的錫鉛球1 3 0 ,一樣可以達到製成具微細間距錫鉛球的目的。 其中在上述所揭露的製程中,在第四步驟5 8蝕刻BLM 層8 0步驟中是只蝕刻濕潤層8 4,未蝕刻黏附防止擴散層Page 16 4104 70 V. Description of the invention (13) The height of the tin-lead bump is related to the reliability of the tin-lead bump. Therefore, in order to obtain higher reliability, it is necessary to add a second The height of the photoresist layer 100 is to form a high tin-lead bump, and the thickness of the second photoresist layer 100 generally used is more than 50 μηι; after the fifth step is completed, it is then reused. The second photomask 1 02 defines the opening 110 of the tin-lead bump to be grown, as shown in the sixth step 62 and "3F figure" of FIG. 2. Next, a solder composed of Sn and Pd is injected into the above-mentioned openings 1 10 by electroplating to form a columnar tin-lead bump 1 2 0, as shown in the seventh step 64 of FIG. 2 and “3G diagram”. ", And then remove the second photoresist layer 100, and then heat the tin-lead bump 1 2 0 by a reflow process at a temperature higher than the melting point of the tin bump 1 120, The tin-lead bump 1 2 0 is changed from a solid state to a liquid state, and the columnar tin-lead bump 1 2 0 is formed into a spherical tin-lead ball 1 3 0 due to its cohesion during the cooling process, as shown in FIG. 2 The eighth step 68 and "Figure 3H" are shown. Finally, please continue to cooperate with the ninth step 6 of FIG. 2 and the “3rd I” to explain the ninth manufacturing step. In this step, an etching process (which can be wet or dry etching) is used to remove other excess The adhesion prevention diffusion layer 8 2 is removed, and thus the fabrication of the flip-chip tin lead ball is completed. In the method disclosed in the present invention, the eighth step 68 heavy-flow solder and the ninth step 66 etch the BL Μ layer. It can be reversed, that is, the adhesion prevention diffusion layer 8 2 can be removed by an etching process first, and then a spherical tin-lead ball 130 can be formed through a heavy-flow process, which can also achieve the purpose of making a fine-pitch tin-lead ball. In the process disclosed above, in the fourth step 5 8 the BLM layer is etched. In the 8 step, only the wet layer 8 4 is etched. The adhesion prevention diffusion layer is not etched.
第17頁 4184 70 五、發明說明(14) 8 2,如「第3 D圖」所示,而在本發明所揭露的另一實施例 中則是直接將BLM層80 (包括濕潤層84及黏附防止擴散層82 )完全蝕刻(如「第4 D圖」所示),只是在此實施例中必需 在第四步驟與第五步驟之間插入一金屬沉積步驟,係指在 未塗覆第二光阻劑層1 0 0之前,先在被蝕刻之B L Μ層8 0的頂 面沉積一非可融性金屬層9 6,此非可融性金屬層9 6係由不 會被錫鉛凸塊1 2 0融解的金屬形成,一般是由高導電性的 材料製成,如Cu或Νι等,其厚度一般是在0.01 /zm與1 之間,較佳是在0 . 0 5 # m與0 . 3 // m之間,但在此需注意的 是當加入此沉積金屬層的步驟之後,在後續步驟中必需先 進行蝕刻步驟以將除鋁焊墊7 2上方之外其餘的地區的非可 融性金屬層9 6去除,再進行重流製程以形成錫鉛球1 3 0, 其整個製造步驟的剖面圖如「第4 A- 41圖」所示,除上述 步驟外,其餘的步驟皆與「第3 A〜3 I圖」之製造步驟相似 ,在此不加以詳述。 其中本發明係利用第一光阻劑層9 0在BLM層8 0上定義 出欲長錫鉛凸塊1 2 0的位置,由於此第一光阻劑層9 0的厚 度很薄,因此在對位上可以對的很準確,雖然在使用第二 光阻劑層1 0 0定義欲長錫鉛凸塊1 2 0的開孔及錫鉛凸塊1 2 0 高度時,會因所使用的第二光阻劑層1 0 0較厚而產生對位 不準的問題,但在後續之重流製程中,會因錫鉛凸塊1 2 0 與濕潤層84的結合效應而自行對準(Sel f-Al lgment),即 在重流製程中在焊料熔融狀態時將偏移的焊料拉回鋁焊墊 7 2上,亦即拉回原先在第一光阻劑層9 0已定義的錫鉛凸塊Page 17 4184 70 V. Description of the invention (14) 8 2 As shown in "3D drawing", in another embodiment disclosed in the present invention, the BLM layer 80 (including the wet layer 84 and The adhesion prevention diffusion layer 82) is completely etched (as shown in "Figure 4D"), but in this embodiment, a metal deposition step must be inserted between the fourth step and the fifth step. Before the two photoresist layers 100, a non-fusible metal layer 96 is deposited on the top surface of the etched BL M layer 80. The non-fusible metal layer 96 is made of tin and lead. The bump 1 2 0 is formed of melted metal, and is generally made of a highly conductive material, such as Cu or Ni. The thickness is generally between 0.01 / zm and 1, preferably 0. 0 5 # m Between 0.3 m and 0.3 m, but it should be noted that after adding the step of depositing the metal layer, an etching step must be performed in the subsequent steps to remove the rest of the area except above the aluminum pad 7 2 The non-fusible metal layer 9 6 is removed, and then a reflow process is performed to form a tin-lead ball 1 3 0. A cross-sectional view of the entire manufacturing process is shown in FIG. 4A-41. It is shown that, except for the above steps, the remaining steps are similar to the manufacturing steps of "Figures 3A to 3I", which will not be described in detail here. The present invention uses the first photoresist layer 90 to define the positions of the tin-lead bumps 120 on the BLM layer 80. Since the thickness of the first photoresist layer 90 is very thin, The alignment can be very accurate, although when the second photoresist layer 1 0 0 is used to define the opening of the tin-lead bump 1 2 0 and the height of the tin-lead bump 1 2 0, the The second photoresist layer 100 is thick and causes misalignment. However, in the subsequent heavy-flow process, it will be self-aligned due to the combination effect of the tin-lead bump 1 2 0 and the wetting layer 84 ( Sel f-Al lgment), that is, in the reflow process, when the solder is molten, the offset solder is pulled back to the aluminum pad 72, that is, the tin that was previously defined in the first photoresist layer 90 is pulled back. Lead bump
第18頁 418470 五、發明說明(15) 1 2 0的位置,因此只要能在第一光阻劑層9 0中準確地定義 欲長錫鉛凸塊1 2 0的位置,即可確保能得到一具微細間距 的錫鉛球1 3 0。 【發明之功效】 , 本發明先利用第一層薄光阻劑在BLM層上定義出欲長_ 焊料球的位置,再利用第二層厚光阻劑定義欲長焊料球的 開孔及焊料球高度,其中由於第一薄光阻劑的厚度很薄, 在對位上準確度很高,亦即可以準確地定義出欲長焊料球 的位置,同時由於本發明所形成的焊料凸塊是一柱狀焊料 凸塊,可以增進微細間距的製程,且由於先蝕刻B L Μ層, 因此可避免因長時間的蝕刻,而導致焊料凸塊被蝕刻或造 成嚴重氧化,因此藉由本發明所揭露的技術,可以製成具 微細間距的覆晶焊料球。 【圖式符號之說明】 10 ......................................................... f f體'结才冓 12 ...............................................................石夕基板 14..................................................................¥ t 16 ............................................................頂部表面 18............................................................ 丁頁部表®Page 18 418470 V. Description of the invention (15) 1 2 0 position, so long as the position of the tin-lead bump 1 2 0 to be long can be accurately defined in the first photoresist layer 90, it can be ensured that A finely pitched tin-lead ball 1 3 0. [Effect of the invention] In the present invention, the first layer of thin photoresist is used to define the position of the solder ball on the BLM layer, and then the second layer of thick photoresist is used to define the opening and height of the solder ball. Among them, because the thickness of the first thin photoresist is very thin, the accuracy of the alignment is high, that is, the position of the solder ball to be grown can be accurately defined, and the solder bump formed by the present invention is a columnar solder. The bumps can improve the fine-pitch manufacturing process, and because the BL M layer is etched first, it can avoid the solder bumps being etched or severely oxidized due to long-term etching. Therefore, the technology disclosed in the present invention can make Form fine-chip flip-chip solder balls. [Explanation of Schematic Symbols] 10 .............................. ............... ff body 'knot only 12 ............... ................... Shi Xi substrate 14 .............. ........................................ ..... ¥ t 16 ..................................... ........ Top surface 18 ............. ............... Dingle Table®
2 0 ...............................................................4 呆言蔓I 22 ..................................................................視窗 24............................................................頂部表面 26 ...............................................................BLM 層 28...............................................................濕潤層2 0 ................................................ ......... 4 Silent Words I 22 ............... ..................... window 24 .............. .................................................top Surface 26 ... ......... BLM layer 28 ............ ............... wet layer
第19頁 ^ ^8470 五、發明說明¢16) 3 0 ...................................................黏附防止擴散層 3 4............................................................ tIg )¾ Μ Μ 38 ............................................................才見f ?斤1 1 40 ............................................................Wj ^ ώ ^ - 42...............................................................m ^ 52 ............................................................ $ - Ψ ^ 54............................................................ % ^ % 5 6 ............................................................ $ ^ 58 ............................................................ % n ^ 60 ............................................................ $ Έ. ψ ^ 62 ............................................................ g六步驟Page 19 ^ 8470 V. Description of the invention ¢ 16) 3 0 ................................... ...... adhesion preventing diffusion layer 3 4 ............ tIg) ¾ Μ 38 ............ ................................... f? catty 1 1 40 ............... Wj ^ FREE ^-42 ............ ......... m ^ 52 ......... .................................. $- ^ ^ 54 ............................... .............% ^% 5 6 ... ............ $ ^ 58 ......... ...............% n ^ 60 ..... ........................................ ..... $ Έ. Ψ ^ 62 ............... ........... g Six steps
64............................................................ $ -t ^ W 66 ..................................................;.........第九步驟 6 8 ............................................................ $ y\ ^ 7 0 ..................................................................晶圓 72 ...............................................................is ^ ^ 7 4............................................................頂部表面 7 6...............................................................^ fi >f 78 ..................................................................表面 80 ...............................................................BLM ^ 82 ...................................................黏附防止擴散層 84...............................................................濕'潤層 9 0 ......................................................第一光阻劑層 92 ..................................................................先革64 ....................................... ........... $ -t ^ W 66 ............. .......; ...... 9th step 6 8 ........ ................. $ y \ ^ 7 0 .. ........................................ .............. wafer 72 ............. ................... is ^ ^ 7 4 ............... ............................................................................. 7 6. ........................................ ............ fi > f 78 ............ ........................ Surface 80 .............. ....................... BLM ^ 82 ................................................ ... adhesion preventing diffusion layer ... ........... wet 'moisture layer 9 0 ......... ............... First photoresist layer 92 ......... ........................................ .... Xiange
第20頁 4 184 70 五、發明說明(17) 10 0 ...................................................第二光阻劑層 102 ............................................................... ft ^ 110 ...............................................................開孔 120.........................................................m ^ a it 130 ............................................................錫鉛球 画_画關 第21頁Page 20 4 184 70 V. Description of the invention (17) 10 0 ......... ...... Second photoresist layer 102 ............... .......................... ft ^ 110 ........... ........................................ ..Opening 120 .................... ............ m ^ a it 130 ............. ................. Pin Shot _ Painting Off Page 21
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US7863739B2 (en) | 2001-03-05 | 2011-01-04 | Megica Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US8178967B2 (en) | 2001-09-17 | 2012-05-15 | Megica Corporation | Low fabrication cost, high performance, high reliability chip scale package |
US8481418B2 (en) | 2002-05-01 | 2013-07-09 | Megica Corporation | Low fabrication cost, high performance, high reliability chip scale package |
US8901733B2 (en) | 2001-02-15 | 2014-12-02 | Qualcomm Incorporated | Reliable metal bumps on top of I/O pads after removal of test probe marks |
-
1999
- 1999-03-30 TW TW088104959A patent/TW418470B/en not_active IP Right Cessation
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8901733B2 (en) | 2001-02-15 | 2014-12-02 | Qualcomm Incorporated | Reliable metal bumps on top of I/O pads after removal of test probe marks |
US7863739B2 (en) | 2001-03-05 | 2011-01-04 | Megica Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US8072070B2 (en) | 2001-03-05 | 2011-12-06 | Megica Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US8368213B2 (en) | 2001-03-05 | 2013-02-05 | Megica Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US8178967B2 (en) | 2001-09-17 | 2012-05-15 | Megica Corporation | Low fabrication cost, high performance, high reliability chip scale package |
US9369175B2 (en) | 2001-09-17 | 2016-06-14 | Qualcomm Incorporated | Low fabrication cost, high performance, high reliability chip scale package |
US8481418B2 (en) | 2002-05-01 | 2013-07-09 | Megica Corporation | Low fabrication cost, high performance, high reliability chip scale package |
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