JP4667736B2 - 多重チャンネルを有するモストランジスターの製造方法 - Google Patents
多重チャンネルを有するモストランジスターの製造方法 Download PDFInfo
- Publication number
- JP4667736B2 JP4667736B2 JP2003342265A JP2003342265A JP4667736B2 JP 4667736 B2 JP4667736 B2 JP 4667736B2 JP 2003342265 A JP2003342265 A JP 2003342265A JP 2003342265 A JP2003342265 A JP 2003342265A JP 4667736 B2 JP4667736 B2 JP 4667736B2
- Authority
- JP
- Japan
- Prior art keywords
- channel
- pattern
- layer
- semiconductor device
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 113
- 238000004519 manufacturing process Methods 0.000 title claims description 81
- 239000010410 layer Substances 0.000 claims description 166
- 239000004065 semiconductor Substances 0.000 claims description 153
- 239000000758 substrate Substances 0.000 claims description 69
- 239000011229 interlayer Substances 0.000 claims description 57
- 238000005530 etching Methods 0.000 claims description 48
- 239000013078 crystal Substances 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 229910021332 silicide Inorganic materials 0.000 claims description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 19
- 125000006850 spacer group Chemical group 0.000 claims description 16
- 239000012212 insulator Substances 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 15
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 9
- 239000011810 insulating material Substances 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 230000003746 surface roughness Effects 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 2
- 230000003796 beauty Effects 0.000 claims 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims 1
- 239000012300 argon atmosphere Substances 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
- 150000002739 metals Chemical class 0.000 claims 1
- 230000003647 oxidation Effects 0.000 description 17
- 238000007254 oxidation reaction Methods 0.000 description 17
- 239000012535 impurity Substances 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000003963 antioxidant agent Substances 0.000 description 2
- 230000003078 antioxidant effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Description
ゲート絶縁膜7は熱酸化膜又はONO膜で形成することができる。
図3は本発明の第1実施例による半導体装置の平面図であり、図4及び図5は各々、図3のAA′線及びBB′線による半導体装置の断面図である。
図31は図23のA部分の拡大図である。図31を参照すると、実施例1による垂直型MOSトランジスターではゲート電極48とソース/ドレーン領域34(具体的にはソース/ドレーン領域の拡張層32)との間にゲート絶縁膜が存在することによってゲート電極48とソース/ドレーン領域34との間にオーバーラップキャパシタンスが発生する。本実施例はこのようなオーバーラップキャパシタンスの発生を抑制するためのものである。
図48は本発明の第3実施例による半導体装置の断面図である。本実施例による半導体装置は、ポリシリコンゲート電極48と金属シリサイドでなされたゲート積層膜50aとが同一な幅を有することを除いては前述した実施例2に図示した半導体装置と同一である。
図49ないし図58は本発明の第4実施例による半導体装置の製造方法を説明するための断面図らである。本実施例で前述した実施例1と同一な部材に対しては同一な参照符号を使用して説明する。
図59は本発明の第5実施例による半導体装置の断面図である。本実施例で実施例1と同一な部材は同一参照符号を使用して示す。
図60は本実施例による半導体装置の断面図である。本実施例で実施例1と同一な部材は同一参照符号を使用して示す。
また、前述した第2、第3または第4実施例のうちひとつ以上と第6実施例とを組合せて多重チャンネルを有する垂直型MOSトランジスターを具現することができる。
図61は本実施例による半導体装置の断面図である。本実施例による半導体装置はアクティブパターンを構成するチャンネル層間層及びチャンネル層の厚さ及び反復回数を調節してチャンネル44の数とトンネルの厚さとが実施例7で図示した半導体装置と異なることを除いては、実施例7に説明した半導体装置と同一である。
図62は本実施例による半導体装置の断面図である。本実施例による半導体装置はSOI基板の酸化膜70上に実施例5または実施例6で記載したところと同一な方法で遂行して形成する。
図63は本発明の第9実施例による半導体装置の断面図である。本実施例による半導体装置は、最低部チャンネル44aの寄生トランジスターが動作することを防止するためにゲート電極48が埋めたてられる最低部トンネルの厚さ(t)を残りのトンネルに比べて厚く形成することを除いては実施例5の図59に図示した半導体装置と同一である。したがって、同一な部材は同一参照符号を使用して示す。
図64ないし図68は本発明の第10実施例による半導体装置及びこれの製造方法を説明するための断面図らである。
図70ないし図72は本発明の第11実施例による半導体装置及びこれの製造方法を説明するための断面図らである。本実施例でも実施例1ないし実施例10と同一な部材に対しは同一参照符号を使用して説明する。
12 不純物領域
30 アクティブパターン
32 ソース/ドレーン拡張層
34 ソース/ドレーン領域
42 トンネルら
44 チャンネル
Si シリコン
SiGe シリコンゲルマニウム
SOI シリコン−オン−インシュレータ
SGOI シリコンゲルマニウム−オン−インシュレータ
Claims (14)
- 半導体基板の上に単結晶シリコンからなる複数個のチャンネル層及び単結晶ゲルマニウムまたは単結晶シリコン−ゲルマニウムからなる複数個のチャンネル層間層を互いに反復して形成する工程と、
前記チャンネル層及びチャンネル層間層をエッチングして予備アクティブパターンを形成し、該エッチング領域に絶縁膜を埋め込んで前記予備アクティブパターンを取り囲むフィールド領域を形成する工程と、
前記予備アクティブパターン上にダミーゲートパターンを含むハードマスクを形成する工程と、
前記ハードマスクをエッチングマスクとして前記予備アクティブパターンをエッチングして予備アクティブパターンをアクティブチャンネルパターンとするとともに、前記エッチングでは前記半導体基板を露出させる工程と、
前記エッチングにより露出した前記半導体基板の上面及び前記エッチングにより露出した前記アクティブチャンネルパターンの側面上に選択的なエピタキシャル成長させてエピタキシャル単結晶膜を成長させたのち、傾斜イオン注入を実施して前記選択的なエピタキシャル単結晶膜を均一にドーピングさせてソース/ドレイン拡張層を形成する工程、ソース/ドレイン領域を形成するために、前記ソース/ドレイン拡張層上にポリシリコン、金属、及び金属シリサイドからなる群より選択されたいずれか1つの導電性物質を蒸着及びエッチバックさせることによって、前記予備アクティブパターンをエッチングして形成されたエッチング領域の内部にのみ前記導電性物質を残留させる工程と、
前記ソース/ドレイン領域及び前記フィールド領域上に、前記ハードマスクを覆うようにマスク層を堆積させたのち、前記ダミーゲートパターンが露出されるまで前記マスク層を平坦化除去する工程と、
前記マスク層を利用して前記ダミーゲートパターンを選択的に除去する工程と、
前記マスク層をエッチングマスクとして前記フィールド領域を選択的にエッチングしてチャンネル領域の前記アクティブチャンネルパターンの側面を露出させる工程と、
前記側面が露出したアクティブチャンネルパターンにおける前記チャンネル層間層を選択的に除去して、前記チャンネル層の表面を露出させると共に前記アクティブチャンネルパターンを貫通するトンネルを形成する工程と、
前記露出したチャンネル層の表面にゲート絶縁膜を形成する工程と、
前記トンネルを埋めたてながら前記複数個のチャンネル層を囲むように前記ゲート絶縁膜上にゲート電極を形成する工程と、
前記ゲート電極の最上層の上面にゲート積層膜を形成する工程と、を上記工程順に実行することを特徴とする半導体装置の製造方法。 - 前記複数個のチャンネル層及び前記複数個のチャンネル層間層を形成する工程は、3個のチャンネル層及び2個のチャンネル層間層を形成する段階であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記半導体基板はシリコン、シリコンゲルマニウム、シリコン−オン−インシュレータ(SOI)及びシリコンゲルマニウム−オン−インシュレータ(SGOI)からなる群より選択されたいずれか一つで形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記複数個のチャンネル層及び前記複数個のチャンネル層間層を形成する工程は、
前記半導体基板上に酸化膜を形成する段階、前記複数個のチャンネル層及び前記複数個のチャンネル層間層を形成する領域の前記酸化膜をエッチング除去して酸化膜パターンを形成する段階、前記酸化膜がエッチング除去されて露出した前記半導体基板表面上に選択的なエピタキシャル成長法で前記複数個のチャンネル層及び前記複数個のチャンネル層間層を互いに反復して積層する段階と、を含んでなされることを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記複数個のチャンネル層及び前記複数個のチャンネル層間層を形成する工程の前に、前記酸化膜がエッチング除去されて露出した前記半導体基板表面に高濃度ドーピング領域を形成するイオン注入段階をさらに具備することを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記導電性物質を蒸着する段階前に、熱処理を実施して前記エピタキシャル単結晶膜の表面荒さを改善して再結晶化させる段階をさらに具備することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記チャンネル層間層を選択的に除去する工程前に、前記露出されたアクティブパターンに投射範囲がそれぞれのチャンネル層内に形成されるようにチャンネルイオン注入を実施する段階をさらに具備することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記チャンネルイオン注入はそれぞれのチャンネル層ごとにドーピング濃度が異なるように実施することによって、前記ゲート電極に印加されるゲート電圧によって前記ゲート電極を有するトランジスターを段階的に作動させることを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記複数個のチャンネル層間層を選択的に除去する段階は等方性のエッチング工程で遂行することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記ゲート積層膜は金属シリサイドまたは絶縁物質で形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記ゲート絶縁膜を形成する段階前に、水素またはアルゴン雰囲気で熱処理を実施して前記チャンネル層の表面荒さを減少させる段階をさらに具備することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記アクティブチャンネルパターンを形成することにより露出した前記チャンネル層間層の側面に絶縁物質からなるゲートスペーサを形成する段階をさらに含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記ゲートスペーサは、
前記露出した複数個のチャンネル層間層を部分的に水平蝕刻してアンダーカット領域を形成する段階と、
前記アンダーカット領域を埋めたてる絶縁膜を形成する段階と、
前記絶縁膜をエッチングして前記アンダーカット領域に前記ゲートスペーサを形成する段階と、により形成することを特徴とする請求項12に記載の半導体装置の製造方法。 - 前記複数個のチャンネル層間層を形成する時に、最低部のチャンネル層間層が残りのチャンネル層間層に比べて厚くなるように形成し、前記アクティブチャンネルパターンを貫通する複数個ある前記トンネルのうち、最下部にあるトンネルが残りのトンネルに比べて
大きい高さを有するように形成することを特徴とする請求項1に記載の半導体装置の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0059886A KR100481209B1 (ko) | 2002-10-01 | 2002-10-01 | 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004128508A JP2004128508A (ja) | 2004-04-22 |
JP4667736B2 true JP4667736B2 (ja) | 2011-04-13 |
Family
ID=29267962
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003342265A Expired - Fee Related JP4667736B2 (ja) | 2002-10-01 | 2003-09-30 | 多重チャンネルを有するモストランジスターの製造方法 |
Country Status (9)
Country | Link |
---|---|
US (4) | US7002207B2 (ja) |
JP (1) | JP4667736B2 (ja) |
KR (1) | KR100481209B1 (ja) |
CN (1) | CN100456498C (ja) |
DE (1) | DE10339920B4 (ja) |
FR (1) | FR2845203B1 (ja) |
GB (1) | GB2395603B (ja) |
IT (1) | ITMI20031884A1 (ja) |
TW (1) | TWI251343B (ja) |
Families Citing this family (238)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050005310A1 (en) * | 1999-07-12 | 2005-01-06 | Genentech, Inc. | Expression vectors and methods |
DE10220923B4 (de) * | 2002-05-10 | 2006-10-26 | Infineon Technologies Ag | Verfahren zur Herstellung eines nicht-flüchtigen Flash-Halbleiterspeichers |
KR100451459B1 (ko) * | 2003-02-10 | 2004-10-07 | 삼성전자주식회사 | 더블 게이트 전극 형성 방법 및 더블 게이트 전극을포함하는 반도체 장치의 제조 방법 |
KR100471173B1 (ko) * | 2003-05-15 | 2005-03-10 | 삼성전자주식회사 | 다층채널을 갖는 트랜지스터 및 그 제조방법 |
US7456476B2 (en) * | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US6921700B2 (en) * | 2003-07-31 | 2005-07-26 | Freescale Semiconductor, Inc. | Method of forming a transistor having multiple channels |
JP2005064500A (ja) * | 2003-08-14 | 2005-03-10 | Samsung Electronics Co Ltd | マルチ構造のシリコンフィンおよび製造方法 |
KR100496891B1 (ko) * | 2003-08-14 | 2005-06-23 | 삼성전자주식회사 | 핀 전계효과 트랜지스터를 위한 실리콘 핀 및 그 제조 방법 |
KR100555518B1 (ko) * | 2003-09-16 | 2006-03-03 | 삼성전자주식회사 | 이중 게이트 전계 효과 트랜지스터 및 그 제조방법 |
FR2860099B1 (fr) * | 2003-09-18 | 2006-01-06 | St Microelectronics Sa | Procede de realisation d'un transistor a effet de champ et transistor ainsi obtenu |
FR2861501B1 (fr) * | 2003-10-22 | 2006-01-13 | Commissariat Energie Atomique | Dispositif microelectronique a effet de champ apte a former un ou plusiseurs canaux de transistors |
US6946377B2 (en) * | 2003-10-29 | 2005-09-20 | Texas Instruments Incorporated | Multiple-gate MOSFET device with lithography independent silicon body thickness and methods for fabricating the same |
KR100542750B1 (ko) * | 2003-10-31 | 2006-01-11 | 삼성전자주식회사 | 반도체 장치의 제조 방법. |
US7074657B2 (en) * | 2003-11-14 | 2006-07-11 | Advanced Micro Devices, Inc. | Low-power multiple-channel fully depleted quantum well CMOSFETs |
KR100550343B1 (ko) | 2003-11-21 | 2006-02-08 | 삼성전자주식회사 | 다중 채널 모오스 트랜지스터를 포함하는 반도체 장치의제조 방법 |
US7335945B2 (en) * | 2003-12-26 | 2008-02-26 | Electronics And Telecommunications Research Institute | Multi-gate MOS transistor and method of manufacturing the same |
KR100552058B1 (ko) * | 2004-01-06 | 2006-02-20 | 삼성전자주식회사 | 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 제조 방법 |
KR100587672B1 (ko) * | 2004-02-02 | 2006-06-08 | 삼성전자주식회사 | 다마신 공법을 이용한 핀 트랜지스터 형성방법 |
US7115947B2 (en) * | 2004-03-18 | 2006-10-03 | International Business Machines Corporation | Multiple dielectric finfet structure and method |
US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
JP2005354023A (ja) * | 2004-05-14 | 2005-12-22 | Seiko Epson Corp | 半導体装置および半導体装置の製造方法 |
JP4796329B2 (ja) * | 2004-05-25 | 2011-10-19 | 三星電子株式会社 | マルチ−ブリッジチャンネル型mosトランジスタの製造方法 |
KR100625177B1 (ko) | 2004-05-25 | 2006-09-20 | 삼성전자주식회사 | 멀티-브리지 채널형 모오스 트랜지스터의 제조 방법 |
US7262104B1 (en) * | 2004-06-02 | 2007-08-28 | Advanced Micro Devices, Inc. | Selective channel implantation for forming semiconductor devices with different threshold voltages |
DE102005026228B4 (de) * | 2004-06-08 | 2010-04-15 | Samsung Electronics Co., Ltd., Suwon | Transistor vom GAA-Typ und Verfahren zu dessen Herstellung |
JP2006012898A (ja) * | 2004-06-22 | 2006-01-12 | Toshiba Corp | 半導体装置及びその製造方法 |
US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
KR100555567B1 (ko) | 2004-07-30 | 2006-03-03 | 삼성전자주식회사 | 다중가교채널 트랜지스터 제조 방법 |
US7348284B2 (en) * | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
KR100585157B1 (ko) * | 2004-09-07 | 2006-05-30 | 삼성전자주식회사 | 다수의 와이어 브릿지 채널을 구비한 모스 트랜지스터 및그 제조방법 |
TWI283066B (en) * | 2004-09-07 | 2007-06-21 | Samsung Electronics Co Ltd | Field effect transistor (FET) having wire channels and method of fabricating the same |
US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US7332439B2 (en) * | 2004-09-29 | 2008-02-19 | Intel Corporation | Metal gate transistors with epitaxial source and drain regions |
US7361958B2 (en) * | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
KR100604908B1 (ko) * | 2004-10-11 | 2006-07-28 | 삼성전자주식회사 | 이종의 게이트 절연막을 구비하는 씬-바디 채널 씨모스소자 및 그 제조방법 |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
TWI277210B (en) * | 2004-10-26 | 2007-03-21 | Nanya Technology Corp | FinFET transistor process |
KR100615096B1 (ko) * | 2004-11-15 | 2006-08-22 | 삼성전자주식회사 | 다중 채널을 갖는 모스 트랜지스터 제조방법 |
US20140110770A1 (en) * | 2004-12-11 | 2014-04-24 | Seoul National University R&Db Foundation | Saddle type mos device |
KR100689211B1 (ko) * | 2004-12-11 | 2007-03-08 | 경북대학교 산학협력단 | 안장형 엠오에스 소자 |
KR100640616B1 (ko) * | 2004-12-21 | 2006-11-01 | 삼성전자주식회사 | 매몰 게이트 패턴을 포함하는 전계 효과 트랜지스터구조물 및 그것을 포함하는 반도체 소자의 제조방법 |
WO2006069340A2 (en) * | 2004-12-21 | 2006-06-29 | Carnegie Mellon University | Lithography and associated methods, devices, and systems |
KR100687431B1 (ko) * | 2004-12-30 | 2007-02-27 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조 방법 |
US7202117B2 (en) * | 2005-01-31 | 2007-04-10 | Freescale Semiconductor, Inc. | Method of making a planar double-gated transistor |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US20060202266A1 (en) | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
JP4561419B2 (ja) * | 2005-03-16 | 2010-10-13 | ソニー株式会社 | 半導体装置の製造方法 |
KR100594327B1 (ko) * | 2005-03-24 | 2006-06-30 | 삼성전자주식회사 | 라운드 형태의 단면을 가지는 나노와이어를 구비한 반도체소자 및 그 제조 방법 |
FR2884648B1 (fr) * | 2005-04-13 | 2007-09-07 | Commissariat Energie Atomique | Structure et procede de realisation d'un dispositif microelectronique dote d'un ou plusieurs fils quantiques aptes a former un canal ou plusieurs canaux de transistors |
KR100699839B1 (ko) * | 2005-04-21 | 2007-03-27 | 삼성전자주식회사 | 다중채널을 갖는 반도체 장치 및 그의 제조방법. |
GB0508407D0 (en) * | 2005-04-26 | 2005-06-01 | Ami Semiconductor Belgium Bvba | Alignment of trench for MOS |
KR100691006B1 (ko) * | 2005-04-29 | 2007-03-09 | 주식회사 하이닉스반도체 | 메모리 소자의 셀 트랜지스터 구조 및 그 제조방법 |
KR100608377B1 (ko) * | 2005-05-02 | 2006-08-08 | 주식회사 하이닉스반도체 | 메모리 소자의 셀 트랜지스터 제조방법 |
US7101763B1 (en) | 2005-05-17 | 2006-09-05 | International Business Machines Corporation | Low capacitance junction-isolation for bulk FinFET technology |
EP1727194A1 (en) * | 2005-05-27 | 2006-11-29 | Interuniversitair Microelektronica Centrum vzw ( IMEC) | Method for high topography patterning |
FR2886761B1 (fr) | 2005-06-06 | 2008-05-02 | Commissariat Energie Atomique | Transistor a canal a base de germanium enrobe par une electrode de grille et procede de fabrication d'un tel transistor |
KR100618900B1 (ko) * | 2005-06-13 | 2006-09-01 | 삼성전자주식회사 | 다중 채널을 갖는 모스 전계효과 트랜지스터의 제조방법 및그에 따라 제조된 다중 채널을 갖는 모스 전계효과트랜지스터 |
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
KR100644019B1 (ko) * | 2005-06-17 | 2006-11-10 | 매그나칩 반도체 유한회사 | 씨모스 이미지센서 및 그 제조 방법 |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7279375B2 (en) | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
FR2889622A1 (fr) * | 2005-08-08 | 2007-02-09 | St Microelectronics Crolles 2 | Procede de fabrication d'un transistor a nanodoigts semiconducteurs paralleles |
US7354831B2 (en) * | 2005-08-08 | 2008-04-08 | Freescale Semiconductor, Inc. | Multi-channel transistor structure and method of making thereof |
KR100674987B1 (ko) * | 2005-08-09 | 2007-01-29 | 삼성전자주식회사 | 벌크 웨이퍼 기판에 형성된 트랜지스터의 구동 방법 |
US7402875B2 (en) | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
KR100630764B1 (ko) | 2005-08-30 | 2006-10-04 | 삼성전자주식회사 | 게이트 올어라운드 반도체소자 및 그 제조방법 |
KR100630763B1 (ko) * | 2005-08-30 | 2006-10-04 | 삼성전자주식회사 | 다중 채널을 갖는 mos 트랜지스터의 제조방법 |
US7323374B2 (en) * | 2005-09-19 | 2008-01-29 | International Business Machines Corporation | Dense chevron finFET and method of manufacturing same |
US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
JP4525928B2 (ja) * | 2005-12-27 | 2010-08-18 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US7498211B2 (en) * | 2005-12-28 | 2009-03-03 | Intel Corporation | Independently controlled, double gate nanowire memory cell with self-aligned contacts |
US20070152266A1 (en) * | 2005-12-29 | 2007-07-05 | Intel Corporation | Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers |
FR2895835B1 (fr) | 2005-12-30 | 2008-05-09 | Commissariat Energie Atomique | Realisation sur une structure de canal a plusieurs branches d'une grille de transistor et de moyens pour isoler cette grille des regions de source et de drain |
FR2897201B1 (fr) * | 2006-02-03 | 2008-04-25 | Stmicroelectronics Crolles Sas | Dispositif de transistor a doubles grilles planaires et procede de fabrication. |
US7803668B2 (en) * | 2006-02-24 | 2010-09-28 | Stmicroelectronics (Crolles 2) Sas | Transistor and fabrication process |
KR100756808B1 (ko) * | 2006-04-14 | 2007-09-07 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
FR2900765B1 (fr) * | 2006-05-04 | 2008-10-10 | Commissariat Energie Atomique | Procede de realisation d'une grille de transistor comprenant une decomposition d'un materiau precurseur en au moins un materiau metallique, a l'aide d'au moins un faisceau d'electrons |
US20070257322A1 (en) * | 2006-05-08 | 2007-11-08 | Freescale Semiconductor, Inc. | Hybrid Transistor Structure and a Method for Making the Same |
US20090321830A1 (en) * | 2006-05-15 | 2009-12-31 | Carnegie Mellon University | Integrated circuit device, system, and method of fabrication |
KR100739658B1 (ko) * | 2006-07-03 | 2007-07-13 | 삼성전자주식회사 | 반도체 장치의 제조 방법. |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
KR100801065B1 (ko) * | 2006-08-04 | 2008-02-04 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그 제조 방법 |
JP2008042206A (ja) * | 2006-08-04 | 2008-02-21 | Samsung Electronics Co Ltd | メモリ素子及びその製造方法 |
US7456471B2 (en) * | 2006-09-15 | 2008-11-25 | International Business Machines Corporation | Field effect transistor with raised source/drain fin straps |
KR100757328B1 (ko) | 2006-10-04 | 2007-09-11 | 삼성전자주식회사 | 단전자 트랜지스터 및 그 제조 방법 |
KR100763542B1 (ko) * | 2006-10-30 | 2007-10-05 | 삼성전자주식회사 | 다중 채널 모오스 트랜지스터를 포함하는 반도체 장치의제조 방법 |
TWI313514B (en) * | 2006-11-16 | 2009-08-11 | Au Optronics Corporatio | Thin film transistor array substrate and fabricating method thereof |
US7842579B2 (en) * | 2007-01-22 | 2010-11-30 | Infineon Technologies Ag | Method for manufacturing a semiconductor device having doped and undoped polysilicon layers |
US7709893B2 (en) * | 2007-01-31 | 2010-05-04 | Infineon Technologies Ag | Circuit layout for different performance and method |
KR100855977B1 (ko) * | 2007-02-12 | 2008-09-02 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
US8227857B2 (en) * | 2007-03-19 | 2012-07-24 | Nxp B.V. | Planar extended drain transistor and method of producing the same |
KR100827529B1 (ko) * | 2007-04-17 | 2008-05-06 | 주식회사 하이닉스반도체 | 다중채널을 갖는 반도체 소자 및 그의 제조 방법 |
US8779495B2 (en) * | 2007-04-19 | 2014-07-15 | Qimonda Ag | Stacked SONOS memory |
US7453125B1 (en) * | 2007-04-24 | 2008-11-18 | Infineon Technologies Ag | Double mesh finfet |
FR2921757B1 (fr) * | 2007-09-28 | 2009-12-18 | Commissariat Energie Atomique | Structure de transistor double-grille dotee d'un canal a plusieurs branches. |
US7781825B2 (en) * | 2007-10-18 | 2010-08-24 | Macronix International Co., Ltd. | Semiconductor device and method for manufacturing the same |
FR2923646A1 (fr) * | 2007-11-09 | 2009-05-15 | Commissariat Energie Atomique | Cellule memoire sram dotee de transistors a structure multi-canaux verticale |
US7923315B2 (en) * | 2007-12-21 | 2011-04-12 | Nxp B.V. | Manufacturing method for planar independent-gate or gate-all-around transistors |
US7915659B2 (en) * | 2008-03-06 | 2011-03-29 | Micron Technology, Inc. | Devices with cavity-defined gates and methods of making the same |
US8273591B2 (en) * | 2008-03-25 | 2012-09-25 | International Business Machines Corporation | Super lattice/quantum well nanowires |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
JP5236370B2 (ja) * | 2008-07-10 | 2013-07-17 | 三菱電機株式会社 | Tft基板の製造方法及びtft基板 |
KR101020099B1 (ko) * | 2008-10-17 | 2011-03-09 | 서울대학교산학협력단 | 스타 구조를 갖는 반도체 소자 및 그 제조방법 |
KR101061264B1 (ko) * | 2009-02-27 | 2011-08-31 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
US8138054B2 (en) * | 2009-04-01 | 2012-03-20 | International Business Machines Corporation | Enhanced field effect transistor |
KR20100121101A (ko) * | 2009-05-08 | 2010-11-17 | 삼성전자주식회사 | 리세스 채널을 갖는 메모리 소자 및 이의 제조방법 |
US8422273B2 (en) * | 2009-05-21 | 2013-04-16 | International Business Machines Corporation | Nanowire mesh FET with multiple threshold voltages |
SG176129A1 (en) | 2009-05-21 | 2011-12-29 | Stella Chemifa Corp | Fine-processing agent and fine-processing method |
US7868391B2 (en) * | 2009-06-04 | 2011-01-11 | International Business Machines Corporation | 3-D single gate inverter |
US7820537B1 (en) * | 2009-07-03 | 2010-10-26 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
KR101036155B1 (ko) | 2009-07-09 | 2011-05-23 | 서울대학교산학협력단 | 스타 구조를 갖는 낸드 플래시 메모리 어레이 및 그 제조방법 |
KR101140060B1 (ko) * | 2009-08-28 | 2012-05-02 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
JP4922373B2 (ja) | 2009-09-16 | 2012-04-25 | 株式会社東芝 | 半導体装置およびその製造方法 |
US8574982B2 (en) * | 2010-02-25 | 2013-11-05 | International Business Machines Corporation | Implementing eDRAM stacked FET structure |
US8314001B2 (en) | 2010-04-09 | 2012-11-20 | International Business Machines Corporation | Vertical stacking of field effect transistor structures for logic gates |
JP5718585B2 (ja) * | 2010-05-19 | 2015-05-13 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置及びその製造方法、並びにデータ処理システム |
US9029834B2 (en) | 2010-07-06 | 2015-05-12 | International Business Machines Corporation | Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric |
US8492220B2 (en) | 2010-08-09 | 2013-07-23 | International Business Machines Corporation | Vertically stacked FETs with series bipolar junction transistor |
CN102683588A (zh) * | 2011-03-10 | 2012-09-19 | 中国科学院微电子研究所 | 一种有机场效应晶体管结构及其制备方法 |
US9087863B2 (en) | 2011-12-23 | 2015-07-21 | Intel Corporation | Nanowire structures having non-discrete source and drain regions |
KR101767352B1 (ko) | 2011-12-23 | 2017-08-10 | 인텔 코포레이션 | 변조된 나노와이어 카운트를 갖는 반도체 구조물 및 그 제조 방법 |
JP5726770B2 (ja) * | 2012-01-12 | 2015-06-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP5580355B2 (ja) * | 2012-03-12 | 2014-08-27 | 株式会社東芝 | 半導体装置 |
FR2989515B1 (fr) | 2012-04-16 | 2015-01-16 | Commissariat Energie Atomique | Procede ameliore de realisation d'une structure de transistor a nano-fils superposes et a grille enrobante |
US8652932B2 (en) * | 2012-04-17 | 2014-02-18 | International Business Machines Corporation | Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures |
JP6083783B2 (ja) * | 2012-06-12 | 2017-02-22 | 猛英 白土 | 半導体装置及びその製造方法 |
US9142400B1 (en) | 2012-07-17 | 2015-09-22 | Stc.Unm | Method of making a heteroepitaxial layer on a seed area |
US8785909B2 (en) * | 2012-09-27 | 2014-07-22 | Intel Corporation | Non-planar semiconductor device having channel region with low band-gap cladding layer |
US8765563B2 (en) * | 2012-09-28 | 2014-07-01 | Intel Corporation | Trench confined epitaxially grown device layer(s) |
US8877604B2 (en) * | 2012-12-17 | 2014-11-04 | International Business Machines Corporation | Device structure with increased contact area and reduced gate capacitance |
US8901607B2 (en) * | 2013-01-14 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabricating the same |
WO2014134490A1 (en) | 2013-02-28 | 2014-09-04 | Massachusetts Institute Of Technology | Improving linearity in semiconductor devices |
US9634000B2 (en) * | 2013-03-14 | 2017-04-25 | International Business Machines Corporation | Partially isolated fin-shaped field effect transistors |
US10181532B2 (en) * | 2013-03-15 | 2019-01-15 | Cree, Inc. | Low loss electronic devices having increased doping for reduced resistance and methods of forming the same |
TWI574308B (zh) * | 2013-06-11 | 2017-03-11 | 聯華電子股份有限公司 | 半導體結構及其製程 |
US9093496B2 (en) | 2013-07-18 | 2015-07-28 | Globalfoundries Inc. | Process for faciltiating fin isolation schemes |
US9349730B2 (en) | 2013-07-18 | 2016-05-24 | Globalfoundries Inc. | Fin transformation process and isolation structures facilitating different Fin isolation schemes |
US9224865B2 (en) * | 2013-07-18 | 2015-12-29 | Globalfoundries Inc. | FinFET with insulator under channel |
US9716174B2 (en) | 2013-07-18 | 2017-07-25 | Globalfoundries Inc. | Electrical isolation of FinFET active region by selective oxidation of sacrificial layer |
US9035277B2 (en) | 2013-08-01 | 2015-05-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabricating the same |
US9184269B2 (en) * | 2013-08-20 | 2015-11-10 | Taiwan Semiconductor Manufacturing Company Limited | Silicon and silicon germanium nanowire formation |
US11404325B2 (en) | 2013-08-20 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon and silicon germanium nanowire formation |
WO2015033381A1 (ja) * | 2013-09-03 | 2015-03-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置 |
US9041062B2 (en) | 2013-09-19 | 2015-05-26 | International Business Machines Corporation | Silicon-on-nothing FinFETs |
US9312272B2 (en) * | 2013-11-27 | 2016-04-12 | Globalfoundries Inc. | Implementing buried FET utilizing drain of finFET as gate of buried FET |
US9059020B1 (en) * | 2013-12-02 | 2015-06-16 | International Business Machins Corporation | Implementing buried FET below and beside FinFET on bulk substrate |
US9590090B2 (en) | 2014-01-08 | 2017-03-07 | Taiwan Semiconductor Manufacturing Company Limited | Method of forming channel of gate structure |
US9508830B2 (en) * | 2014-01-23 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company Limited | Method of forming FinFET |
US9837440B2 (en) | 2014-02-07 | 2017-12-05 | International Business Machines Corporation | FinFET device with abrupt junctions |
TWI557915B (zh) * | 2014-03-05 | 2016-11-11 | 財團法人國家實驗研究院 | 垂直式電晶體元件及其製作方法 |
CN105097535B (zh) * | 2014-05-12 | 2018-03-13 | 中国科学院微电子研究所 | FinFet器件的制造方法 |
US9293523B2 (en) * | 2014-06-24 | 2016-03-22 | Applied Materials, Inc. | Method of forming III-V channel |
US9608116B2 (en) * | 2014-06-27 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FINFETs with wrap-around silicide and method forming the same |
US9917169B2 (en) * | 2014-07-02 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method of formation |
US9868902B2 (en) | 2014-07-17 | 2018-01-16 | Soulbrain Co., Ltd. | Composition for etching |
KR101631240B1 (ko) * | 2015-01-07 | 2016-06-17 | 서강대학교산학협력단 | 구동전류 향상을 위한 터널링 전계효과 트랜지스터 |
US9450046B2 (en) * | 2015-01-08 | 2016-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor structure with fin structure and wire structure and method for forming the same |
KR101649441B1 (ko) * | 2015-01-23 | 2016-08-18 | 울산과학기술원 | 전계효과트랜지스터를 이용한 테라헤르츠 검출기 |
US9553172B2 (en) * | 2015-02-11 | 2017-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for FinFET devices |
US9647071B2 (en) | 2015-06-15 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | FINFET structures and methods of forming the same |
EP3112316B1 (en) | 2015-07-02 | 2018-05-02 | IMEC vzw | Method for manufacturing transistor devices comprising multiple nanowire channels |
US10634397B2 (en) | 2015-09-17 | 2020-04-28 | Purdue Research Foundation | Devices, systems, and methods for the rapid transient cooling of pulsed heat sources |
CN106549053B (zh) * | 2015-09-17 | 2021-07-27 | 联华电子股份有限公司 | 半导体结构及其制作方法 |
US9876025B2 (en) | 2015-10-19 | 2018-01-23 | Sandisk Technologies Llc | Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices |
US9780108B2 (en) * | 2015-10-19 | 2017-10-03 | Sandisk Technologies Llc | Ultrathin semiconductor channel three-dimensional memory devices |
US9590038B1 (en) | 2015-10-23 | 2017-03-07 | Samsung Electronics Co., Ltd. | Semiconductor device having nanowire channel |
US9985101B2 (en) * | 2015-10-30 | 2018-05-29 | Varian Semiconductor Equipment Associates, Inc. | Encapsulated nanostructures and method for fabricating |
US9899387B2 (en) * | 2015-11-16 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
KR102413371B1 (ko) * | 2015-11-25 | 2022-06-28 | 삼성전자주식회사 | 반도체 소자 |
US9704962B1 (en) * | 2015-12-16 | 2017-07-11 | Globalfoundries Inc. | Horizontal gate all around nanowire transistor bottom isolation |
WO2017111819A1 (en) | 2015-12-26 | 2017-06-29 | Intel Corporation | Gate isolation in non-planar transistors |
US9899269B2 (en) * | 2015-12-30 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-gate device and method of fabrication thereof |
KR102577628B1 (ko) * | 2016-01-05 | 2023-09-13 | 어플라이드 머티어리얼스, 인코포레이티드 | 반도체 응용들을 위한 수평 게이트 올 어라운드 디바이스들을 위한 나노와이어들을 제조하기 위한 방법 |
KR102360333B1 (ko) * | 2016-02-18 | 2022-02-08 | 삼성전자주식회사 | 반도체 장치 |
US9899416B2 (en) | 2016-01-11 | 2018-02-20 | Samsung Electronics Co., Ltd. | Semiconductor device and fabricating method thereof |
KR102461174B1 (ko) | 2016-02-26 | 2022-11-01 | 삼성전자주식회사 | 반도체 소자 |
KR102413610B1 (ko) | 2016-03-02 | 2022-06-24 | 삼성전자주식회사 | 레이아웃 디자인 시스템, 이를 이용한 반도체 장치 및 그 제조 방법 |
KR101784489B1 (ko) * | 2016-04-15 | 2017-10-12 | 고려대학교 산학협력단 | 다층 구조를 갖는 반도체 소자 및 그 제조방법 |
CN116110941A (zh) | 2016-04-25 | 2023-05-12 | 应用材料公司 | 水平环绕式栅极元件纳米线气隙间隔的形成 |
US9755073B1 (en) * | 2016-05-11 | 2017-09-05 | International Business Machines Corporation | Fabrication of vertical field effect transistor structure with strained channels |
JP6763703B2 (ja) * | 2016-06-17 | 2020-09-30 | ラピスセミコンダクタ株式会社 | 半導体装置および半導体装置の製造方法 |
US9831324B1 (en) | 2016-08-12 | 2017-11-28 | International Business Machines Corporation | Self-aligned inner-spacer replacement process using implantation |
KR102618607B1 (ko) * | 2016-09-06 | 2023-12-26 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US9859421B1 (en) * | 2016-09-21 | 2018-01-02 | International Business Machines Corporation | Vertical field effect transistor with subway etch replacement metal gate |
CN106298778A (zh) * | 2016-09-30 | 2017-01-04 | 中国科学院微电子研究所 | 半导体器件及其制造方法及包括该器件的电子设备 |
US10833193B2 (en) | 2016-09-30 | 2020-11-10 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device, method of manufacturing the same and electronic device including the device |
KR20180068591A (ko) | 2016-12-14 | 2018-06-22 | 삼성전자주식회사 | 식각용 조성물 및 이를 이용한 반도체 장치 제조 방법 |
US9972542B1 (en) | 2017-01-04 | 2018-05-15 | International Business Machines Corporation | Hybrid-channel nano-sheet FETs |
KR102564325B1 (ko) * | 2017-01-04 | 2023-08-07 | 삼성전자주식회사 | 다수의 채널 영역을 가지는 반도체 장치 |
US10103241B2 (en) * | 2017-03-07 | 2018-10-16 | Nxp Usa, Inc. | Multigate transistor |
JP2018148123A (ja) * | 2017-03-08 | 2018-09-20 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置及び半導体装置の製造方法 |
KR102400558B1 (ko) | 2017-04-05 | 2022-05-20 | 삼성전자주식회사 | 반도체 소자 |
KR102318560B1 (ko) * | 2017-04-12 | 2021-11-01 | 삼성전자주식회사 | 반도체 소자 |
US10297663B2 (en) * | 2017-04-19 | 2019-05-21 | International Business Machines Corporation | Gate fill utilizing replacement spacer |
TWI758464B (zh) * | 2017-04-20 | 2022-03-21 | 美商微材料有限責任公司 | 含矽間隔物的選擇性形成 |
US10566245B2 (en) * | 2017-04-26 | 2020-02-18 | Samsung Electronics Co., Ltd. | Method of fabricating gate all around semiconductor device |
CN108807386B (zh) * | 2017-04-28 | 2023-04-07 | 三星电子株式会社 | 半导体器件 |
EP3404702A1 (en) * | 2017-05-15 | 2018-11-21 | IMEC vzw | A method for forming vertical channel devices |
US10403550B2 (en) * | 2017-08-30 | 2019-09-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device and a semiconductor device |
US10699956B2 (en) | 2017-08-30 | 2020-06-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device and a semiconductor device |
DE102017126225A1 (de) * | 2017-08-31 | 2019-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Verfahren zum herstellen einer halbleitervorrichtung und eine halbleitervorrichtung |
US10332985B2 (en) * | 2017-08-31 | 2019-06-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10236217B1 (en) | 2017-11-02 | 2019-03-19 | International Business Machines Corporation | Stacked field-effect transistors (FETs) with shared and non-shared gates |
US10566330B2 (en) * | 2017-12-11 | 2020-02-18 | Samsung Electronics Co., Ltd. | Dielectric separation of partial GAA FETs |
US10818800B2 (en) * | 2017-12-22 | 2020-10-27 | Nanya Technology Corporation | Semiconductor structure and method for preparing the same |
KR102480348B1 (ko) | 2018-03-15 | 2022-12-23 | 삼성전자주식회사 | 실리콘게르마늄 식각 전의 전처리 조성물 및 이를 이용한 반도체 장치의 제조 방법 |
US10446664B1 (en) * | 2018-03-20 | 2019-10-15 | International Business Machines Corporation | Inner spacer formation and contact resistance reduction in nanosheet transistors |
CN110767549B (zh) * | 2018-07-26 | 2023-05-16 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构及其形成方法 |
US10680065B2 (en) | 2018-08-01 | 2020-06-09 | Globalfoundries Inc. | Field-effect transistors with a grown silicon-germanium channel |
KR102534246B1 (ko) | 2018-08-30 | 2023-05-18 | 삼성전자주식회사 | 반도체 장치 |
KR102509307B1 (ko) | 2018-09-19 | 2023-03-10 | 삼성전자주식회사 | 반도체 장치 |
US11101360B2 (en) * | 2018-11-29 | 2021-08-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device and a semiconductor device |
US10797060B2 (en) | 2018-12-17 | 2020-10-06 | Sandisk Technologies Llc | Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same |
EP3711091A4 (en) | 2018-12-17 | 2021-11-24 | SanDisk Technologies LLC | THREE-DIMENSIONAL STORAGE DEVICE WITH TENSIONED VERTICAL SEMICONDUCTOR CHANNELS AND PROCESS FOR THEIR PRODUCTION |
US11721727B2 (en) | 2018-12-17 | 2023-08-08 | Sandisk Technologies Llc | Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same |
US10797061B2 (en) | 2018-12-17 | 2020-10-06 | Sandisk Technologies Llc | Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same |
US10985172B2 (en) | 2019-01-18 | 2021-04-20 | Sandisk Technologies Llc | Three-dimensional memory device with mobility-enhanced vertical channels and methods of forming the same |
US10825919B2 (en) * | 2019-02-21 | 2020-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of fabricating semiconductor devices having gate-all-around structure with inner spacer last process |
US10886415B2 (en) | 2019-03-07 | 2021-01-05 | International Business Machines Corporation | Multi-state transistor devices with multiple threshold voltage channels |
US11217694B2 (en) * | 2019-03-18 | 2022-01-04 | Shanghai Industrial Μtechnology Research Institute | Field-effect transistor and method for manufacturing the same |
KR20200135662A (ko) | 2019-05-24 | 2020-12-03 | 삼성전자주식회사 | 반도체 장치 |
KR20200136133A (ko) | 2019-05-27 | 2020-12-07 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
CN110233108B (zh) * | 2019-06-24 | 2022-07-22 | 中国科学院微电子研究所 | 一种围栅器件及其制造方法 |
CN112309860B (zh) * | 2019-07-30 | 2023-07-04 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
TW202129061A (zh) * | 2019-10-02 | 2021-08-01 | 美商應用材料股份有限公司 | 環繞式閘極輸入/輸出工程 |
TWI805947B (zh) * | 2019-10-21 | 2023-06-21 | 美商應用材料股份有限公司 | 水平gaa奈米線及奈米平板電晶體 |
US11424338B2 (en) | 2020-03-31 | 2022-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal source/drain features |
CN111613676B (zh) * | 2020-04-11 | 2021-06-04 | 复旦大学 | 一种具有层叠结构的多栅指数晶体管及其制备方法 |
CN114334833A (zh) * | 2020-09-29 | 2022-04-12 | 长鑫存储技术有限公司 | 半导体器件及其制备方法 |
KR20220149828A (ko) | 2021-04-30 | 2022-11-09 | 삼성전자주식회사 | 반도체 소자 |
CN113471214B (zh) * | 2021-05-18 | 2023-09-19 | 中国科学院微电子研究所 | 一种多层绝缘体上硅锗衬底结构及其制备方法和用途 |
WO2023286666A1 (en) * | 2021-07-12 | 2023-01-19 | Fujifilm Corporation | Semiconductor etching solution |
CN113707613B (zh) * | 2021-08-12 | 2023-07-04 | 长鑫存储技术有限公司 | 半导体结构的形成方法 |
CN114121960A (zh) * | 2021-11-19 | 2022-03-01 | 北京超弦存储器研究院 | 存储器件及其制造方法及包括存储器件的电子设备 |
CN117794231A (zh) * | 2022-09-20 | 2024-03-29 | 长鑫存储技术有限公司 | 半导体结构及其形成方法 |
CN116666439B (zh) * | 2023-04-20 | 2024-04-26 | 中国科学院微电子研究所 | 具有连续栅长的竖直半导体器件及其制造方法及电子设备 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000068517A (ja) * | 1998-08-24 | 2000-03-03 | Nec Corp | 半導体装置の製造方法 |
JP2000260986A (ja) * | 1999-03-12 | 2000-09-22 | Toyota Central Res & Dev Lab Inc | 双方向電流阻止機能を有する電界効果トランジスタ及びその製造方法 |
JP2000277745A (ja) * | 1999-03-19 | 2000-10-06 | Internatl Business Mach Corp <Ibm> | ダブルゲート集積回路及びその製造方法 |
WO2000079602A1 (de) * | 1999-06-22 | 2000-12-28 | Infineon Technologies Ag | Mehrkanal-mosfet und verfahren zu seiner herstellung |
JP2003324200A (ja) * | 2002-05-02 | 2003-11-14 | Tokyo Inst Of Technol | 電界効果トランジスタ及びその製造方法 |
JP2004119693A (ja) * | 2002-09-26 | 2004-04-15 | Tokyo Inst Of Technol | 強誘電体メモリデバイス及び強誘電体メモリデバイスの製造方法 |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0214578A (ja) | 1988-07-01 | 1990-01-18 | Fujitsu Ltd | 半導体装置 |
JPH05226655A (ja) * | 1992-02-18 | 1993-09-03 | Fujitsu Ltd | 半導体装置の製造方法 |
US5241202A (en) * | 1992-03-12 | 1993-08-31 | Micron Technology, Inc. | Cell structure for a programmable read only memory device |
JPH05259439A (ja) * | 1992-03-12 | 1993-10-08 | Toshiba Corp | 半導体装置 |
US5412224A (en) | 1992-06-08 | 1995-05-02 | Motorola, Inc. | Field effect transistor with non-linear transfer characteristic |
US5221849A (en) | 1992-06-16 | 1993-06-22 | Motorola, Inc. | Semiconductor device with active quantum well gate |
KR950002202B1 (ko) * | 1992-07-01 | 1995-03-14 | 현대전자산업주식회사 | 적층 박막 트랜지스터 제조방법 |
JPH0629535A (ja) * | 1992-07-09 | 1994-02-04 | Casio Comput Co Ltd | 薄膜トランジスタ |
JP3460863B2 (ja) | 1993-09-17 | 2003-10-27 | 三菱電機株式会社 | 半導体装置の製造方法 |
JPH098291A (ja) * | 1995-06-20 | 1997-01-10 | Fujitsu Ltd | 半導体装置 |
US6444506B1 (en) * | 1995-10-25 | 2002-09-03 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing silicon thin film devices using laser annealing in a hydrogen mixture gas followed by nitride formation |
FR2756974B1 (fr) * | 1996-12-10 | 1999-06-04 | Sgs Thomson Microelectronics | Transistor bipolaire a isolement par caisson |
JP3550019B2 (ja) * | 1997-03-17 | 2004-08-04 | 株式会社東芝 | 半導体装置 |
US5864129A (en) * | 1997-05-05 | 1999-01-26 | Psc Inc. | Bar code digitizer including a voltage comparator |
JPH118390A (ja) * | 1997-06-18 | 1999-01-12 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6004837A (en) * | 1998-02-18 | 1999-12-21 | International Business Machines Corporation | Dual-gate SOI transistor |
US5937297A (en) * | 1998-06-01 | 1999-08-10 | Chartered Semiconductor Manufacturing, Ltd. | Method for making sub-quarter-micron MOSFET |
US6239472B1 (en) * | 1998-09-01 | 2001-05-29 | Philips Electronics North America Corp. | MOSFET structure having improved source/drain junction performance |
US6190234B1 (en) | 1999-01-25 | 2001-02-20 | Applied Materials, Inc. | Endpoint detection with light beams of different wavelengths |
JP3086906B1 (ja) | 1999-05-28 | 2000-09-11 | 工業技術院長 | 電界効果トランジスタ及びその製造方法 |
DE19924571C2 (de) * | 1999-05-28 | 2001-03-15 | Siemens Ag | Verfahren zur Herstellung eines Doppel-Gate-MOSFET-Transistors |
US6410394B1 (en) * | 1999-12-17 | 2002-06-25 | Chartered Semiconductor Manufacturing Ltd. | Method for forming self-aligned channel implants using a gate poly reverse mask |
JP2001284598A (ja) * | 2000-03-31 | 2001-10-12 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6642115B1 (en) * | 2000-05-15 | 2003-11-04 | International Business Machines Corporation | Double-gate FET with planarized surfaces and self-aligned silicides |
US6413802B1 (en) | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
KR100414217B1 (ko) | 2001-04-12 | 2004-01-07 | 삼성전자주식회사 | 게이트 올 어라운드형 트랜지스터를 가진 반도체 장치 및그 형성 방법 |
US6440806B1 (en) * | 2001-04-30 | 2002-08-27 | Advanced Micro Devices, Inc. | Method for producing metal-semiconductor compound regions on semiconductor devices |
US6639246B2 (en) * | 2001-07-27 | 2003-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US6689650B2 (en) * | 2001-09-27 | 2004-02-10 | International Business Machines Corporation | Fin field effect transistor with self-aligned gate |
US6909145B2 (en) * | 2002-09-23 | 2005-06-21 | International Business Machines Corporation | Metal spacer gate for CMOS FET |
-
2002
- 2002-10-01 KR KR10-2002-0059886A patent/KR100481209B1/ko active IP Right Grant
-
2003
- 2003-07-01 US US10/610,607 patent/US7002207B2/en not_active Expired - Lifetime
- 2003-07-23 TW TW092120130A patent/TWI251343B/zh not_active IP Right Cessation
- 2003-08-01 CN CNB031524923A patent/CN100456498C/zh not_active Expired - Lifetime
- 2003-08-29 DE DE10339920.8A patent/DE10339920B4/de not_active Expired - Lifetime
- 2003-09-02 FR FR0310376A patent/FR2845203B1/fr not_active Expired - Lifetime
- 2003-09-19 GB GB0321985A patent/GB2395603B/en not_active Expired - Lifetime
- 2003-09-30 JP JP2003342265A patent/JP4667736B2/ja not_active Expired - Fee Related
- 2003-10-01 IT IT001884A patent/ITMI20031884A1/it unknown
-
2004
- 2004-05-07 US US10/841,870 patent/US7381601B2/en active Active
-
2005
- 2005-05-02 US US11/119,786 patent/US7026688B2/en not_active Expired - Lifetime
-
2007
- 2007-11-30 US US11/948,175 patent/US7615429B2/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000068517A (ja) * | 1998-08-24 | 2000-03-03 | Nec Corp | 半導体装置の製造方法 |
JP2000260986A (ja) * | 1999-03-12 | 2000-09-22 | Toyota Central Res & Dev Lab Inc | 双方向電流阻止機能を有する電界効果トランジスタ及びその製造方法 |
JP2000277745A (ja) * | 1999-03-19 | 2000-10-06 | Internatl Business Mach Corp <Ibm> | ダブルゲート集積回路及びその製造方法 |
WO2000079602A1 (de) * | 1999-06-22 | 2000-12-28 | Infineon Technologies Ag | Mehrkanal-mosfet und verfahren zu seiner herstellung |
JP2003324200A (ja) * | 2002-05-02 | 2003-11-14 | Tokyo Inst Of Technol | 電界効果トランジスタ及びその製造方法 |
JP2004119693A (ja) * | 2002-09-26 | 2004-04-15 | Tokyo Inst Of Technol | 強誘電体メモリデバイス及び強誘電体メモリデバイスの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
GB0321985D0 (en) | 2003-10-22 |
GB2395603B (en) | 2006-05-03 |
US20080090362A1 (en) | 2008-04-17 |
JP2004128508A (ja) | 2004-04-22 |
US20040209463A1 (en) | 2004-10-21 |
GB2395603A (en) | 2004-05-26 |
CN100456498C (zh) | 2009-01-28 |
US7002207B2 (en) | 2006-02-21 |
DE10339920B4 (de) | 2014-03-13 |
US20050189583A1 (en) | 2005-09-01 |
US7381601B2 (en) | 2008-06-03 |
FR2845203A1 (fr) | 2004-04-02 |
DE10339920A1 (de) | 2004-04-22 |
ITMI20031884A1 (it) | 2004-04-02 |
TWI251343B (en) | 2006-03-11 |
TW200417021A (en) | 2004-09-01 |
US7026688B2 (en) | 2006-04-11 |
FR2845203B1 (fr) | 2007-07-06 |
US20040063286A1 (en) | 2004-04-01 |
US7615429B2 (en) | 2009-11-10 |
CN1487599A (zh) | 2004-04-07 |
KR100481209B1 (ko) | 2005-04-08 |
KR20040029582A (ko) | 2004-04-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4667736B2 (ja) | 多重チャンネルを有するモストランジスターの製造方法 | |
JP4796329B2 (ja) | マルチ−ブリッジチャンネル型mosトランジスタの製造方法 | |
US7229884B2 (en) | Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels | |
CN107689394B (zh) | 半导体结构及其制作方法 | |
KR100499159B1 (ko) | 리세스 채널을 갖는 반도체장치 및 그 제조방법 | |
KR101637679B1 (ko) | Fⅰnfet을 형성하기 위한 메커니즘들을 포함하는 반도체 디바이스및 그 형성 방법 | |
TWI509736B (zh) | 半導體結構及其形成方法 | |
TWI691076B (zh) | 半導體結構及其製作方法 | |
US7368348B2 (en) | Methods of forming MOS transistors having buried gate electrodes therein | |
JP2008172082A (ja) | 半導体装置及び半導体装置の製造方法 | |
KR102331059B1 (ko) | 반도체 디바이스 및 방법 | |
US11942523B2 (en) | Semiconductor devices and methods of forming the same | |
US20180269107A1 (en) | Method of Forming a Semiconductor Device | |
US20230378001A1 (en) | Semiconductor device and method | |
US7858489B2 (en) | Method for manufacturing semiconductor device capable of increasing current drivability of PMOS transistor | |
US11652155B2 (en) | Air spacer and method of forming same | |
US20230261045A1 (en) | Semiconductor Device Including Air Spacer and Method of Manufacture | |
US20220406774A1 (en) | Doped well for semiconductor devices | |
US20230369134A1 (en) | Semiconductor device and manufacturing method thereof | |
KR20080011488A (ko) | 다중 채널 모스 트랜지스터를 포함하는 반도체 장치의 제조방법 | |
CN115706140A (zh) | 鳍的制备方法、鳍式场效应晶体管及其制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050324 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081209 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090306 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100209 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100609 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20100616 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101102 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101116 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101214 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110112 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140121 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4667736 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |