TWI805947B - 水平gaa奈米線及奈米平板電晶體 - Google Patents

水平gaa奈米線及奈米平板電晶體 Download PDF

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TWI805947B
TWI805947B TW109134035A TW109134035A TWI805947B TW I805947 B TWI805947 B TW I805947B TW 109134035 A TW109134035 A TW 109134035A TW 109134035 A TW109134035 A TW 109134035A TW I805947 B TWI805947 B TW I805947B
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班傑明 哥倫布
漢斯喬奇姆 高斯曼
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美商應用材料股份有限公司
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Abstract

茲描述水平全環繞式閘極元件及製造其之方法。所述hGAA元件包含位於該元件的源極區域與汲極區域之間的經摻雜半導體材料。所述方法包括：摻雜位於電子元件的源極區域與汲極區域之間的半導體材料層。

Description

水平GAA奈米線及奈米平板電晶體
本揭示內容之實施例大體上涉及半導體元件，且更具體而言，涉及水平全環繞式閘極元件結構及用於形成水平全環繞式閘極元件結構(horizontal gate all around device structure)之方法和設備。
電晶體是大多數積體電路之關鍵組件。由於電晶體的驅動電流及其所致之速度與電晶體的閘極寬度成正比，因此較快的電晶體通常需要更大的閘極寬度。因此，需要在電晶體尺寸與速度之間權衡，且已開發「鰭式」場效應電晶體(finFET)以解決具有最大驅動電流和最小尺寸之電晶體的矛盾目標。FinFET的特徵在於鰭狀通道區域，鰭狀通道區域可在不顯著增加電晶體的足跡之情況下大幅增加電晶體的尺寸，且現在已被應用於許多積體電路中。然而，finFET有其自身的缺點。
隨著電晶體元件的特徵尺寸持續縮減以實現更大的電路密度和更高的效能，需要改良的電晶體元件結構以改善靜電耦合並降低諸如寄生電容和關閉狀態洩漏(off-state leakage)等負面影響。電晶體元件結構的實例包括平面結構、鰭式場效應電晶體(FinFET)結構及水平全環繞式閘極(hGAA)結構。hGAA元件結構包括數個晶格匹配通道，所述晶格匹配通道以層疊配置方式懸置，並藉由源極區域/汲極區域連接。發明人相信，hGAA結構提供了良好的靜電控制，且可廣泛適用於互補式金屬氧化物半導體(CMOS)晶圓製造。
邏輯閘極效能與所使用之材料的特性還有結構層的厚度及面積有關。然而，隨著調整某些閘極特性來適應元件縮放，挑戰就出現了。此外，水平全環繞式閘極(hGAA)元件上之導線之間的空間侷限使用於I/O電晶體之閘極介電材料的厚度受到限制。
技術發展現狀的晶片上系統電路對於各類型的電路需要多達七個不同的閾值電壓。目前，這可藉由以下方式實現：(i) 藉由佈植各種劑量進入通道來摻雜通道，接著退火；或(ii) 藉由對覆蓋通道的多重超薄金屬層進行沉積、蝕刻及退火來修飾功函數。前者在通道中造成缺陷，而後者則非常昂貴、易造成產量損失並受到空間限制。
因此，有需要用於形成水平全環繞式閘極元件之改良方法。
本揭示內容之一或多個實施例涉及了形成半導體元件之方法。選擇性地蝕刻包含交替地排列成複數個層疊對(stacked pair)之複數個第一層及相應的複數個第二層之超晶格結構，以去除各所述第一層或各所述第二層，以在超晶格結構中形成複數個孔洞及在源極區域與汲極區域之間延伸之複數個半導體材料層。摻雜所述複數個半導體材料層，以形成經摻雜半導體材料層。
本揭示內容之額外實施例涉及水平全環繞式閘極元件，所述水平全環繞式閘極元件包含介於源極區域與汲極區域之間的複數個水平的經摻雜半導體材料層。
本揭示內容之進一步實施例涉及電腦可讀取媒體，所述電腦可讀取媒體具有儲存於其上之指令，當所述指令被執行時，導致形成半導體元件之方法。所述方法包含以下步驟：選擇性地蝕刻包含交替地排列成複數個層疊對(stacked pair)之複數個第一層及相應的複數個第二層之超晶格結構，以去除各所述第一層或各所述第二層，以在超晶格結構中形成複數個孔洞及在源極區域與汲極區域之間延伸之複數個半導體材料層；以及摻雜所述複數個半導體材料層，以形成經摻雜半導體材料層。
在描述本揭示內容的數個示例性實施例之前，應瞭解到本揭示內容不受限於下面說明書中所闡述的建置或處理程序的細節。本揭示內容能夠具有其他實施例，並能夠被由各種方式實作或執行。
如在此說明書及隨附申請專利範圍中所使用，術語「基板(substrate)」指的是表面，或表面的部分，其中製程在所述表面或表面的部分上進行。本案所屬技術領域中具通常知識者亦將理解的是，除非上下文另有明確指示，否則參照基板可僅指基板的一部分。此外，對沉積在基板上之參照可指裸基板和具有在其上沉積或形成的一或多個膜或特徵之基板二者。
如本文所用，「基板」指的是任何基板或形成於基板上之材料表面，在製造製程期間期間，在所述基板或形成於基板上之材料表面上進行膜處理。舉例而言，取決於應用，於上面可進行處理之基板表面可包括：諸如矽、氧化矽、應變矽、絕緣體上矽(SOI)、經碳摻雜的氧化矽、非晶矽、經摻雜的矽、鍺、砷化鎵、玻璃、藍寶石等材料，及任何其他材料(如金屬、金屬氮化物、金屬合金及其它導電材料)。基板可包括，但不限於，半導體晶圓。可將基板暴露於預處理製程，以研磨、蝕刻、還原、氧化、羥基化、退火及/或烘烤基板表面。除了在基板本身的表面上直接進行膜處理之外，在本揭示內容中，也可在形成於基板上的下方層(under-layer)上進行本文所揭示的任何膜處理程序(如下文更詳細地揭示)，且術語「基板表面」欲包括前後文所指的此類下方層。因此，舉例而言，當膜/層或部分膜/層已被沉積至基板表面上，新沉積之膜/層的暴露表面便成為基板表面。
如本說明書及隨附申請專利範圍所用，術語「前驅物」、「反應物」、「反應性氣體」等可互換使用，以指稱可與基板表面反應之任何氣態物種。
電晶體是通常形成於半導體元件上之電路組件或單元。取決於電路設計，除了電容器、電感器、電阻器、二極體、導線或其他單元以外，還有電晶體形成於半導體元件上。通常，電晶體包括形成於源極區域與汲極區域之間的閘極。在一或多個實施例中，源極區域和汲極區域包括基板的經摻雜區域，並表現出適合於特定應用之摻雜輪廓。閘極位於通道區域上方，且包括閘極介電質，而閘極介電質插設於閘極電極與基板中之通道區域之間。
如本文所用，術語「場效應電晶體」或「FET」指的是使用電場來控制元件的電氣行為之電晶體。增強模式場效應電晶體通常在低溫下顯現非常高的輸入阻抗。汲極端與源極端之間的導電率受元件中之電場的控制，所述電場是由元件的主體與閘極之間的電壓差所產生。FET的三個端部為：源極(S)，載體通過源極進入通道；汲極(D)，載體通過汲極離開通道；和閘極(G)，閘極端用於調節通道導電率。通常，在源極(S)處進入通道的電流被標記為IS，且在汲極(D)處進入通道的電流被標記為ID。汲極-至-源極電壓被標記為VDS。藉由對閘極(G)施加電壓，可控制在汲極處進入通道之電流(即，ID)。
金屬氧化物半導體場效應電晶體(MOSFET)是場效應電晶體(FET)的一個類型。它具有絕緣的閘極，其電壓決定了元件的導電率。這種以施加電壓量來改變導電率的能力被用來放大或切換電子訊號。MOSFET是基於主體電極與閘極電極之間的金屬氧化物半導體(MOS)電容對電荷濃度之調節，所述閘極電極位於主體上方並藉由閘極介電層與所有其他元件區域絕緣。相較於MOS電容器，MOSFET包括兩個額外端部(源極和汲極)，各額外端部連接至由主體區域分隔之高度摻雜區域。這些區域可為p型也可為n型，但它們都是相同型，且與主體區域的型相反。在摻雜的型後方以「+」符號表示源極和汲極(不同於主體)被高度摻雜。
若MOSFET為n-通道或nMOS FET，則源極和汲極為n+區域且主體為p區域。若MOSFET為p-通道或pMOS FET，則源極和汲極為p+區域且主體為n區域。之所以這樣稱呼源極是因為它是流過通道之電荷載體(對n-通道而言是電子，對p-通道而言是電洞)的源頭；類似地，汲極是電荷載體離開通道處。
如本文所用，術語「鰭式場效應電晶體(FinFET)」指的是建構在基板上的MOSFET電晶體，其中閘極位於通道的兩側或三側，形成雙重閘極結構或三重閘極結構。因為通道區域在基板上形成「鰭」，因此FinFET元件的通用名稱為FinFET。FinFET元件具有快速切換時間及高電流密度。
如本文所用，術語「全環繞式閘極(gate all-around；GAA)」用於指稱電子元件(如，電晶體)，其中閘極材料繞通道區域的所有側面。GAA電晶體的通道區域可包括奈米線或奈米板塊(nano-slab)、桿狀通道或本案所屬技術領域中具有通常知識者所知之其他合適通道配置。在一或多個實施例中，GAA元件的通道區域具有垂直間隔的多重水平奈米線或水平桿，從而使GAA電晶體成為層疊的水平全環繞式閘極(hGAA)電晶體。
在一或多個實施例中，水平全環繞式閘極(hGAA)電晶體包含：基板，具有頂表面；源極區域，具有源極和源極接點，源極區域位於基板的頂表面上；汲極區域，具有汲極和汲極接點，汲極區域位於基板的頂表面上；通道，定位在源極與汲極之間並具有軸，所述軸實質上與基板的頂表面平行；閘極，包圍源極區域與汲極區域之間的通道；熱氧化物層，覆蓋並接觸閘極、源極接點或汲極接點中之一或多者；以及低ĸ介電層，覆蓋所述熱氧化物層。在一或多個實施例中，低ĸ介電層具有小於約5 nm之厚度。
本揭示內容之一或多個實施例涉及了形成水平全環繞式閘極元件之方法。一些實施例有利地提供了將摻質擴散到活性區域以摻雜通道並移動閾值電壓(亦稱為閘極電壓)之方法。在一些實施例中，將通道表面暴露於適當的摻質乘載氣體(如，B2 H6 )，然後進行適當的退火(如，800 ºC雷射退火)。一些實施例有利地提供用於形成hGAA元件之無缺陷且簡單的方法。一些實施例有利地不受奈米線或奈米板塊之間的開放空間之限制。
在一些實施例中，用於形成hGAA元件之方法被擴增，以在導線釋放(wire-release)（蝕刻SiGe釋放層，使奈米導線變得自由）與金屬閘極替換（沉積閘極介電質、功函數金屬和相關金屬）之間插入一或多個製程。在一些實施例中，所述方法將導線暴露於摻質乘載氣體並將晶圓退火（如，藉由雷射或尖波退火(spike anneal)）。一些實施例有利地提供原子式清潔(如，無氧化物)表面。在一些實施例中，藉由一或多個溫度或氣體暴露來調整通道摻雜及所得Vt。
儘管參照硼摻雜及nFET來描述本揭示內容之實施例，但本案所屬技術領域中具通常知識者將認知到，本揭示內容不限於這種類型的電晶體。在一些實施例中，揭示了使用合適的p型摻雜氣體進行用於pFET的通道摻雜及閾值電壓之一或多種方法。
第1圖描繪根據本揭示內容的一些實施例之用於形成半導體元件的方法100之流程圖。以下參照第2A至2F圖來描述方法100，第2A至2F圖描繪根據本揭示內容的一些實施例之半導體結構的製造階段。本發明之方法100可為半導體元件之多步驟製造製程的一部分。因此，可在耦接至叢集工具之任何合適的製程腔室中進行所述方法。叢集工具可包括用於製造半導體元件之製程腔室，如經配置來蝕刻、沉積、物理氣相沉積(PVD)、化學氣相沉積(CVD)、氧化之腔室，或用於製造半導體元件之任何其他合適腔室。
方法100藉由提供具有頂表面202之基板200(如第2A圖所繪示)而始於102。在一些實施例中，基板200可為整塊半導體基板(bulk semiconductor substrate)。術語「整塊半導體基板」指的是其中基板的整體由半導體材料構成之基板。整塊半導體基板可包含任何合適的半導體材料及/或用於形成半導體結構之半導體材料的組合。舉例而言，半導體層可包含一或多種材料，如晶態矽(如，Si<100>或Si<111>)、氧化矽、應變矽、矽鍺、經摻雜的或未經摻雜的多晶矽、經摻雜的或未經摻雜的矽晶圓、經圖案化或不經圖案化的晶圓、摻雜的矽、鍺、砷化鎵或其他合適的半導體材料。在一些實施例中，半導體材料為矽(Si)。在一些實施例中，半導體材料可為經摻雜的材料，如經n型摻雜的矽(n-Si)或經p型摻雜的矽(p-Si)。在一些實施例中，可使用諸如離子佈植製程等任何合適的製程來摻雜基板。在一些實施例中，為了避免寄生底部元件啟動，可摻雜基板以在基板200的表面之第一位置處提供高劑量的摻質。於第一位置頂部形成超晶格結構。舉例而言，在一些實施例中，基板的表面可具有約1018 個原子/cm3 至約1019 個原子/cm3 之摻質密度。
在基板200的頂表面202的頂部形成至少一個超晶格結構204 (如第2A圖所描繪)。超晶格結構204包含交替地排列成複數個層疊對(stacked pair)之複數個第一層及相應的複數個第二層。在一些實施例中，複數個層疊的層組包含矽(Si)及矽鍺(SiGe)組和銦-磷(InP)及銦-鎵-磷(InGaP)組。在一些實施例中，複數個第一層及相應的複數個第二層可包含適於形成超晶格結構204之任何數目的晶格匹配材料對。在一些實施例中，複數個第一層及相應的複數個第二層包含2至50對的晶格匹配材料。
通常，寄生元件將存在於超晶格結構204的底部處。在一些實施例中，如上文所討論，在基板中佈植摻質被用於抑制寄生元件的啟動。在一些實施例中，基板200經蝕刻，使得超晶格結構204的底部部分包括未被去除的基板部分，從而允許所述基板部分作為超晶格結構204的底部釋放層(release layer)。
在一些實施例中，第一層及第二層的厚度在約2 nm至約50 nm的範圍內，或在約3 nm至約20 nm的範圍內。在一些實施例中，第一層的平均厚度為第二層的平均厚度之0.5至2倍。
在一些實施例中，使用常規化學氣相沉積方法將介電材料246沉積於基板200上。在一些實施例中，介電材料246凹進基板200的頂表面202下方，使得超晶格結構204的底部部分由基板200形成。
在一些實施例中，在超晶格結構204上方形成替換閘極結構(如，仿閘極結構208)。仿閘極結構208界定電晶體元件的通道區域。可使用本案所屬技術領域中已知的任何合適常規沉積和圖案化製程來形成仿閘極結構208。
在一些實施例中，沿著仿閘極結構208的外側壁形成側壁間隔物210。一些實施例的側壁間隔物210包含本案所屬技術領域中已知的合適絕緣材料，例如，氮化矽、氧化矽、氧氮化矽、碳化矽等等。在一些實施例中，使用諸如原子層沉積、電漿增進原子層沉積、電漿增進化學氣相沉積或低壓化學氣相沉積等本案所屬技術領域中已知的任何合適常規沉積和圖案化製程來形成側壁間隔物210。
在一些實施例中，分別在源極溝槽和汲極溝槽中形成嵌埋式源極區域232和汲極區域234。在一些實施例中，在超晶格結構204的第一端鄰近處形成源極區域232，且在超晶格結構的相對的第二端鄰近處形成汲極區域234。在第2A圖所繪示之實施例中，視圖在超晶格結構204的前面處未示出源極區域232或汲極區域234中之一者。超晶格結構204的另一端具有源極區域232或汲極區域234中之另一者。在一些實施例中，源極區域232及/或汲極區域234由任何合適的半導體材料形成，例如但不限於，矽、鍺、矽鍺等等。在一些實施例中，可使用諸如磊晶沉積製程等任何合適的沉積製程來形成源極區域232和汲極區域234。
在一些實施例中，在包括源極/汲極區域232、234、仿閘極結構208及側壁間隔物210之基板200上方毯覆沉積層間介電質(inter-layer dielectric；ILD)層220。可使用常規化學氣相沉積方法(如，電漿增進化學氣相沉積及低壓化學氣相沉積)來沉積ILD層220。在實施例中，由任何已熟知的介電材料來形成ILD層220，所述介電材料例如但不限於：未經摻雜的氧化矽、經摻雜的氧化矽(如，BPSG、PSG)、氮化矽及氧氮化矽。接著使用常規化學機械平坦化方法將ILD層220拋光回去，以暴露仿閘極結構208的頂部。在一些實施例中，拋光ILD層220以暴露仿閘極結構208的頂部和側壁間隔物210的頂部。
如第2B圖所示，在製程104中，去除仿閘極結構208，以暴露超晶格結構204的通道區域214。在去除仿閘極結構208期間，ILD層220可保護源極區域/汲極區域232、234。可使用諸如電漿乾式蝕刻或濕式蝕刻等常規蝕刻方法去除仿閘極結構208。在一些實施例中，仿閘極結構208包含多晶矽，並藉由選擇性蝕刻製程去除仿閘極結構。在一些實施例中，仿閘極結構208包含多晶矽，且超晶格結構204包含矽(Si)和矽鍺(SiGe)的交替層。
如第2C圖所示，在製程106中，選擇性地蝕刻超晶格結構204中之半導體材料層224之間的釋放層226。舉例而言，當超晶格結構204由矽層和矽鍺層構成，則選擇性地蝕刻矽鍺以形成通道奈米導線240。可使用任何已熟知的蝕刻劑來去除釋放層226，例如矽鍺，所述蝕刻劑對半導體材料層224的層具有選擇性，而所述蝕刻劑蝕刻釋放層226的層之速率顯著高於蝕刻半導體材料層224的層。在一些實施例中，可使用選擇性乾式蝕刻或濕式蝕刻製程。在一些實施例中，當半導體材料層224為矽且釋放層226為矽鍺，可使用濕式蝕刻劑來選擇性地去除矽鍺的層，濕式蝕刻劑可例如但不限於，水性羧酸/硝酸/HF溶液和水性檸檬酸/硝酸/HF溶液。去除釋放層226在半導體材料層224之間留下孔洞228。半導體材料層224之間的孔洞228具有約3 nm至約20 nm的厚度。餘留的半導體材料層224形成通道奈米導線240的垂直陣列，所述通道奈米導線240耦接源極區域/汲極區域232、234。通道奈米導線240平行於基板200的頂表面202行進並彼此對準，以形成單列的通道奈米線240。源極區域232和汲極區域234之形成和可選的側向蝕刻終止層(未示出)之形成有利地在通道結構的形成中提供自對準和結構完整性。
如第2D圖所示，在製程108中，將暴露於通道區域214中之半導體材料層224暴露於一或多個摻雜製程，以形成經摻雜半導體材料層245。在一些實施例中，藉由將半導體材料層224暴露於摻質氣體來完成對暴露的半導體材料層224之摻雜。摻質氣體可為本案所屬技術領域中具通常知識者已知可與半導體材料層224反應之任何合適氣體。在一些實施例中，摻質為n型摻質。在一些實施例中，摻質為p型摻質。在一些實施例中，摻質選自硼(B)、鋁(Al)、銦(In)、磷(P)、鎵(Ga)、砷(As)、氮(N)或銻(Sb)中之一或多者。在一些實施例中，摻質氣體包含B2 H6 。在一些實施例中，摻質氣體基本上由B2 H6 組成。以此方式所使用，術語「基本上由…組成」意指活性摻質物種的整體大於或等於整體摻雜物種之約95%、98%、99%或99.5%。舉例而言，不包括對半導體材料層224保持惰性的稀釋劑及/或載體氣體或其他氣態物種。
在一些實施例中，一或多個摻雜製程包括退火製程。在一或多個實施例中，將半導體材料層224暴露於摻質氣體導致形成摻質的梯度濃度，使得在經摻雜半導體材料層245的外邊緣處之摻質濃度大於在經摻雜半導體材料層245的內部中之濃度。在一些實施例中，摻質濃度在退火後保持不均勻。不受任何特定的操作理論束縛，咸信摻質均質程度會影響啟動元件之閘極電壓，或半導體部分的載流能力。在一些實施例中，摻質濃度梯度受到控制，使得濃度在最靠外側的0.5 nm、0.75 nm、1 nm、1.25 nm、1.5 nm、1.75 nm或2 nm下降一個數量級。
在一些實施例中，退火導致經摻雜半導體材料層245內之摻質濃度均質化或在整個經摻雜半導體材料層245的厚度內變得更均勻地分佈。在一些實施例中，經摻雜半導體材料層245在距離層的表面之任何給定的距離處之摻質濃度在平均摻質濃度的50%、60%、70%、80%、90%或95%以內。
在一些實施例中，經摻雜半導體材料層245中任一者之總摻質濃度在約1017 至1021 個原子/cm3 的範圍內。在一些實施例中，經摻雜半導體材料層245中任一者之總摻質濃度在約1018 至1019 個原子/cm3 的範圍內。在一些實施例中，摻質包含總摻質濃度為約1019 個原子/cm3 之硼。
藉由本案所屬技術領域中具通常知識者已知的任何合適退火製程和條件來完成經摻雜半導體材料層245之退火。在一些實施例中，退火包含尖波退火或雷射退火中之一或多者。
方法100的製程110代表根據一些實施例之一或多個摻雜後處理。一或多個摻雜後處理可為本案所屬技術領域中具通常知識者已知用於完成hGAA元件之製程中的任何製程。請參見第2E及2F圖，在一些實施例中，在經摻雜半導體材料層245上形成或生長氧化物層252。氧化物層252可為藉由本案所屬技術領域中具通常知識者已知之任何合適技術形成之任何合適的氧化物。
在圖解之實施例中，高k介電質254形成於氧化物層252上。高k介電質254可為藉由本案所屬技術領域中具通常知識者已知的任何合適沉積技術所沉積之任何合適的高k介電材料。一些實施例的高k介電質254包含氧化鉿。在一些實施例中，諸如氮化鈦、鎢、鈷、鋁等導電材料256位於高k介電質254上。使用諸如原子層沉積(ALD)等任何合適的沉積製程來形成導電材料256，以確保在各個經摻雜半導體材料層245周圍形成具有均勻厚度的層。
在一些實施例中，閘極電極242形成在基板200上並圍繞各個經摻雜半導體材料層245。可由本案所屬技術領域中已知的任何合適閘極電極材料來形成閘極電極242。使用諸如原子層沉積(ALD)等任何合適的沉積製程來沉積閘極電極材料，以確保在各個經摻雜半導體材料層245周圍和之間形成閘極電極242。根據本揭示內容的實施例，使用本文所述之方法形成之所得元件為水平全環繞式閘極元件。本揭示內容的一些實施例涉及水平全環繞式閘極元件，所述水平全環繞式閘極元件包含經摻雜半導體材料層245作為源極區域與汲極區域之間的通道中之奈米導線或奈米片。
一些實施例涉及半導體元件，所述半導體元件包含水平全環繞式閘極元件，所述水平全環繞式閘極元件之閘極電壓大於或等於約0.400V。在一些實施例中，元件的閘極電壓大於或等於約0.425V或0.450V。在一些實施例中，啟動所述元件所需之閘極電壓大於或等於啟動不具有摻質之類似元件所需之閘極電壓的約140%。在一些實施例中，啟動所述元件所需之閘極電壓是在啟動不具有摻質之類似元件所需之閘極電壓的1至2倍之範圍內。如以這種方式所使用，以與標的元件相同的方式但無摻雜製程來製備「類似元件」。
在整個說明書中對「一個實施例」、「某些實施例」、「一或多個實施例」或「一實施例」之參照意味著結合該實施例描述之具體特徵、結構、材料或特性包括在本揭示內容之至少一個實施例中。因此，在整個說明書多處出現之片語，如「在一或多個實施例中」、「在某些實施例中」、「在一個實施例中」或「在實施例中」不必然指稱本揭示內容之相同實施例。此外，在一或多個實施例中，具體特徵、結構、材料或特性可以任何方式組合。
儘管已參照特定實施例描述本文之揭示內容，但本案所屬技術領域中具通常知識者將可瞭解這些實施例僅是對本揭示內容之原理和應用的解說。對本案所屬技術領域中具通常知識者而言顯然可對本揭示內容之方法及設備進行各種修飾和變化，而不悖離本揭示內容之精神及範疇。因此，本揭示內容欲包括隨附申請專利範圍及其均等者之範疇內的修飾和變化。
100:方法 102~110:製程 200:基板 202:頂表面 204:超晶格結構 208:仿閘極結構 210:側壁間隔物 214:通道區域 220:層間介電質(ILD)層 224:半導體材料層 226:釋放層 232:源極區域 234:汲極區域 242:閘極電極 245:經摻雜半導體材料層 246:介電材料 252:氧化物層 254:高k介電質 256:導電材料
因此，可詳細理解本揭示內容之上述特徵之方式，即可參照實施例更具體描述上文簡要概述之本揭示內容，其中一些實施例圖示於隨附圖式中。然而，請注意，附圖僅示出了此揭示內容的典型實施例，因此不應視為對範圍的限制，因為本揭示內容可以允許其他等效實施例。
第1圖描繪根據本揭示內容的一些實施例之用於形成半導體元件之方法的流程圖；以及
第2A至2F圖繪示基板在根據本揭示內容的一些實施例之形成半導體元件之方法期間的製造階段。
為了便於理解，儘可能使用相同的元件符號來表示圖中共有的相同元件。附圖未按比例繪製，並且為清楚起見可以簡化。一個實施例的元件和特徵可以有益地併入其他實施例中，而無需進一步敘述。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
200:基板
210:側壁間隔物
220:層間介電質(ILD)層
232:源極區域
234:汲極區域
242:閘極電極
245:經摻雜半導體材料層
246:介電材料

Claims (19)

  1. 一種形成一半導體元件之方法，包含以下步驟：選擇性地蝕刻包含交替地排列成複數個層疊對(stacked pair)之複數個第一層及相應的複數個第二層之一超晶格結構，以去除各該等第一層或各該等第二層，以在該超晶格結構中形成複數個孔洞及在一源極區域與一汲極區域之間延伸之複數個半導體材料層；摻雜該複數個半導體材料層，包含將該等半導體材料層暴露於一摻質氣體源，以形成經摻雜半導體材料層，該摻質氣體源於該等半導體材料層上形成摻質之一表面濃度；以及將其上具有摻質之該表面濃度的該等半導體材料層暴露於一退火環境，以使該等半導體材料層的整個厚度中之該摻質濃度均質化。
  2. 如請求項1所述之方法，其中該退火環境具有大於或等於約750℃之一溫度。
  3. 如請求項2所述之方法，其中退火發生達小於或等於約5秒。
  4. 如請求項1所述之方法，其中該等半導體材料層的整個厚度中之該摻質濃度係在以下範圍內：從約1017個原子/cm3至約1021個原子/cm3。
  5. 如請求項4所述之方法，其中該摻質包含約1019個原子/cm3的硼。
  6. 如請求項4所述之方法，其中半導體元件包含一水平全環繞式閘極元件(horizontal gate-all-around device)，該水平全環繞式閘極元件之一閘極電壓係大於或等於約0.400V。
  7. 如請求項6所述之方法，其中啟動該元件所需之閘極電壓大於或等於啟動不具有摻質之一元件所需之閘極電壓的約140%。
  8. 如請求項6所述之方法，其中啟動該元件所需之閘極電壓是在啟動不具有摻質之一元件所需之閘極電壓的1至2倍之範圍內。
  9. 如請求項1所述之方法，進一步包含以下步驟：於一基板的一頂表面上形成該超晶格結構。
  10. 如請求項9所述之方法，進一步包含以下步驟：形成該源極區域及該汲極區域，該源極區域鄰近該超晶格結構之一第一端，且該汲極區域鄰近該超晶格結構之一第二相對端。
  11. 如請求項1所述之方法，其中該等第一層包含至少一種III-V族材料，且該等第二層包含至少一種III-V族材料，而該等第一層與該等第二層包含不同材料。
  12. 如請求項11所述之方法，其中該等第一層包含矽鍺(SiGe)，且該等第二層包含矽(Si)。
  13. 如請求項12所述之方法，其中選擇性地蝕刻該超晶格結構包含以下步驟：蝕刻該等矽鍺(SiGe) 第一層並留下該等矽(Si)第二層。
  14. 如請求項1所述之方法，其中該等第一層及該等第二層之厚度個別為約3nm至約20nm。
  15. 如請求項1所述之方法，其中該摻質氣體選自硼(B)、鋁(Al)、銦(In)、磷(P)、鎵(Ga)、砷(As)、氮(N)或銻(Sb)中之一或多者。
  16. 如請求項15所述之方法，其中該摻質氣體包含B2H6。
  17. 如請求項1所述之方法，進一步包含以下步驟：於該等經摻雜半導體材料層上形成一氧化物層。
  18. 如請求項17所述之方法，進一步包含以下步驟：於該氧化物層上形成一高k介電質。
  19. 一種電腦可讀取媒體，具有儲存於其上之指令，當該等指令被執行時，導致形成一半導體元件之方法，該方法包含以下步驟：選擇性地蝕刻包含交替地排列成複數個層疊對(stacked pair)之複數個第一層及相應的複數個第二層之一超晶格結構，以去除各該等第一層或各該等第二層，以在該超晶格結構中形成複數個孔洞及在一源極區域與一汲極區域之間延伸之複數個半導體材料層；摻雜該複數個半導體材料層，包含將該等半導體材料層暴露於一摻質氣體源，以形成經摻雜半導體材料層，該摻質氣體源於該等半導體材料層上形成摻質之一表面濃度；以及將其上具有摻質之該表面濃度的該等半導體材料層暴露於一退火環境，以使該等半導體 材料層的整個厚度中之該摻質濃度均質化。
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