CN116110941A - 水平环绕式栅极元件纳米线气隙间隔的形成 - Google Patents

水平环绕式栅极元件纳米线气隙间隔的形成 Download PDF

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CN116110941A
CN116110941A CN202310083382.8A CN202310083382A CN116110941A CN 116110941 A CN116110941 A CN 116110941A CN 202310083382 A CN202310083382 A CN 202310083382A CN 116110941 A CN116110941 A CN 116110941A
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layer
stack
nanowire structure
silicon
dielectric material
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孙世宇
纳姆·孙·基姆
邴希·孙·伍德
吉田娜奥米
龚盛钦
金苗
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Applied Materials Inc
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Abstract

本公开内容提供一种使用期望材料形成用于半导体晶片的水平环绕式栅极(hGAA)结构场效应晶体管(FET)的纳米线结构的设备与方法。一个范例中，一种形成纳米线结构的方法包括将介电材料沉积在堆叠的第一侧与第二侧上。堆叠可包括重复多对的第一层与第二层。第一侧与第二侧相对，且第一侧与第二侧具有形成于第一侧与第二侧中的一个或多个凹部。该方法包括从堆叠的第一侧及第二侧移除介电材料。介电材料保留在一个或多个凹部中。该方法包括沉积应力源层及在应力源层与堆叠的第一侧及所述第二侧之间形成一个或多个侧隙。

Description

水平环绕式栅极元件纳米线气隙间隔的形成
本申请是申请日为2017年3月21日、申请号为201780025153.3、发明名称为“水平环绕式栅极元件纳米线气隙间隔的形成”的发明专利申请的分案申请。
技术领域
本公开内容的实施方式大体上关于堆叠的hGAA元件。
背景技术
可靠地生产次半微米(sub-half micron)及更小的特征是半导体元件的下一代超大型集成电路(very large scale integration,VLSI)和特大型集成电路(ultra large-scale integration,ULSI)的一项关键技术挑战。然而，随着电路技术的极限的推进，VLSI及ULSI技术的持续缩小的尺寸已对处理能力有额外的要求。在基板上可靠地形成栅极结构对VLSI及ULSI的成功而言是重要的，且对持续致力增加电路密度及个别基板与裸片(die)的品质而言也是重要的。
随着下一代的元件的电路密度的增加，互连件(诸如过孔、沟槽、触点、栅极结构及其它特征)的宽度以及这些部件之间的介电材料的宽度减少到25nm及20nm的尺寸及更小，然而介电层的厚度维持实质上恒定，结果增加特征的深宽比。再者，减少的通道长度经常引发现有平面MOSFET架构中的显著短通道效应。为了实现下一代元件及结构的制造，三维(3D)元件结构经常用于改善晶体管的性能。尤其，鳍式场效应晶体管(FinFET)经常用于增强元件性能。FinFET元件一般包括具高深宽比的半导体鳍片，其中用于晶体管的通道及源极/漏极区域形成在所述半导体鳍片上。随后利用增加的通道及源极/漏极区域表面积的优点而在所述鳍片元件的一部分的侧面上且沿着所述侧面形成栅极电极，从而生产快速、更可靠、更好控制的半导体晶体管元件。FinFET的进一步优点包括减少短通道效应及提供更高的电流。有水平环绕式栅极(horizontal gate-all-around,hGAA)构造的元件结构经常通过环绕的栅极提供卓越的静电控制，从而抑制短通道效应及相关的漏电流。
一些应用中，hGAA结构用于下一代半导体元件应用。hGAA元件结构包括数个晶格匹配通道(例如纳米线)，这些晶格匹配通道悬挂在堆叠构造中且通过源极/漏极区域连接。
在hGAA结构中，经常利用不同的材料形成通道结构(例如纳米线)，所述通道结构可能会不期望地增加将所有这些材料整合于纳米线结构中且不恶化元件性能的制造困难度。例如，与hGAA结构相关的一项挑战包括金属栅极与源极/漏极之间存在大寄生电容。此类寄生电容的不适当管理可能造成相当劣化的元件性能。
因此，需要制造hGAA元件的改善结构与方法。
发明内容
本公开内容提供一种使用期望材料形成用于半导体晶片的水平环绕式栅极(hGAA)结构的纳米线结构的结构与方法。
一个实施方式中，公开一种处理基板的方法。所述方法包括，将介电材料沉积在堆叠的第一侧及所述堆叠的第二侧的每一个上。所述堆叠包括重复多对的第一层与第二层。所述堆叠的所述第一侧与所述堆叠的所述第二侧相对，且所述第一侧与所述第二侧的每一个包括一个或多个凹部。所述方法也包括，从所述堆叠的所述第一侧及所述堆叠的所述第二侧移除所述介电材料。所述介电材料保留在所述第一侧与所述第二侧的所述一个或多个凹部中。所述方法也包括，沉积应力源(stressor)层并形成一个或多个间隙，所述应力源层邻近所述第一侧与所述第二侧，并且所述间隙位于所述应力源层与所述堆叠的所述第一侧之间及所述应力源层与所述堆叠的所述第二侧之间。
另一实施方式中，公开另一种处理基板的方法。所述方法包括，在处理腔室中将堆叠沉积于所述基板上。所述堆叠包括重复多对的第一层与第二层。所述方法也包括，从所述堆叠移除材料，以在所述堆叠的第一侧及所述堆叠的与所述第一侧相对的第二侧的每一个上产生一个或多个凹部。所述方法也包括，将介电材料沉积在所述堆叠的所述第一侧上、所述堆叠的所述第二侧上，及所述一个或多个凹部内。所述方法也包括，从所述第一侧及所述第二侧的每一个移除所述介电材料。所述介电材料保留在所述一个或多个凹部中。所述方法也包括，沉积应力源(stressor)层并形成一个或多个间隙，所述应力源层邻近所述第一侧及所述第二侧，所述间隙位于所述应力源层与所述堆叠的所述第一侧之间及所述应力源层与所述堆叠的所述第二侧之间。
尚有另一实施方式中，公开一种纳米线结构。所述纳米线结构包括具有重复多对的第一层与第二层的堆叠。所述堆叠包括第一侧，所述第一侧与第二侧相对。所述纳米线结构也包括：环绕所述堆叠的栅极结构、邻近所述堆叠的第一侧的源极层、与所述源极层相对且邻近所述堆叠的所述第二侧的漏极层、设置在所述源极层与所述第二层之间的一个或多个间隙、以及设置在所述漏极层与所述第二层之间的一个或多个间隙。
附图说明
使得可详细地理解本公开内容的以上所述的特征的方式，可通过参考实施方式(其中一些实施方式绘示于附图中)，可得到上文简要总结的本公开内容的更详细的叙述。然而，应注意附图所说明的仅为本公开内容的典型实施方式，因此不应被视为限制本公开内容的保护范围，因为本公开内容可容许其它等效实施方式。
图1描绘了制造形成于基板上的纳米线结构的方法的流程图。
图2A、2B1、2C1、2D1、2E1、2F1描绘了图1的制造工艺期间以期望材料形成纳米线结构的序列的一个范例的剖面视图。
图2A、2B2、2C2、2D2、2E2、2F2描绘了图1的制造工艺期间以期望材料形成纳米线结构的序列的另一范例的剖面视图。
图3A至图3C描绘了水平环绕式栅极(hGAA)结构的范例的示意图。
图4描绘了等离子体处理腔室，所述等离子体处理腔室可用于在基板上执行沉积工艺。
图5描绘了处理系统，所述处理系统可包括图4的等离子体处理腔室，所述等离子体处理腔室并入所述处理系统中。
为了助于了解，已尽可能使用相同的元件符号指定各图共通的相同元件。可设想一个实施方式中公开的元件及特征可有利地并入其它实施方式中而无需赘述。
然而，应注意，附图所说明的仅为本公开内容的示范性实施方式，因此不应被视为限制本公开内容的保护范围，因为本公开内容可容许其它等效实施方式。
具体实施方式
本公开内容提供一种使用期望材料形成用于半导体晶片的水平环绕式栅极(hGAA)结构场效应晶体管(FET)的纳米线结构的设备与方法。一个范例中，一种形成纳米线结构的方法包括将介电材料沉积在堆叠的第一侧与第二侧上。所述堆叠可包括重复多对的第一层与第二层。所述第一侧与第二侧相对，且所述第一侧与所述第二侧具有一个或多个凹部这些凹部形成于所述第一侧与所述第二侧中。所述方法包括从所述堆叠的所述第一侧及所述第二侧移除所述介电材料。所述介电材料保留在所述一个或多个凹部中。所述方法包括沉积应力源层并形成一个或多个侧隙，所述侧隙位于所述应力源层与所述堆叠的所述第一侧中间及所述应力源层与所述堆叠的所述第二侧之间。在此提供一种用于水平环绕式栅极(hGAA)半导体元件结构的纳米线结构，所述纳米线结构具有受控的寄生电容。
图1是方法100的一个范例的流程图，所述方法100用于以复合材料制造纳米线结构(例如通道结构)，所述纳米线结构用于水平环绕式栅极(hGAA)半导体元件结构。图2A图至图2C是对应方法100的各阶段的复合基板的一部分的剖面视图。方法100可用于在基板上形成用于水平环绕式栅极(hGAA)半导体元件结构200的纳米线结构，所述纳米线结构具有之后可用于形成场效应晶体管(FET)的期望材料。替代地，方法100可有益于用以制造其它类型的结构。
方法100开始于操作102，在处理腔室中(如图4中所描述的腔室400)，将膜堆叠204(如图2A所示)沉积于基板202上。基板202可以是诸如结晶硅(例如Si<100>或Si<110>)、氧化硅、应变硅、硅锗、锗、掺杂或无掺杂的多晶硅、掺杂或无掺杂的硅晶片和图案化或无图案化晶片绝缘体上硅(silicon on insulator,SOI)、碳掺杂的氧化硅、氮化硅、掺杂硅、锗、砷化镓、玻璃、或蓝宝石的材料。基板202可具有各种尺寸，诸如200mm、300mm、450mm、或其它直径，且所述基板为矩形或方形面板(panel)。
膜堆叠204可设置在可选的材料层206上。在不存在可选的材料层206的实施方式中，膜堆叠204可视需求直接形成于基板202上。一个范例中，可选的材料层206是绝缘材料。绝缘材料的适合范例包括氧化硅材料、氮化硅材料、氮氧化硅材料、或任何适合的绝缘材料。替代地，可选的材料层206可以是视需求包括导电材料或非导电材料的任何适合的材料。堆叠204包括至少一对的层，每一对包括第一层212与第二层214。尽管在图2A中描绘的范例显示有四对，每一对包括第一层212及第二层214(交替对，每一对包括第一层212及第二层214)，但应注意，各自包括第一层212及第二层214的对的数量可根据不同工艺需求而有所不同。一个特定实施方式中，可沉积四对第一层212及第二层214，以在基板202上形成堆叠204。一个实施方式中，每个单一的第一层212的厚度可介于约20埃至约200埃之间(诸如约50埃)，每个单一的第二层214的厚度可介于约20埃至约200埃之间(诸如约50埃)。
第一层212可以是通过外延沉积工艺形成的结晶硅层，诸如单一结晶、多晶、或单晶硅层。替代地，第一层212可以是掺杂的硅层，包括p型掺杂硅层或n型掺杂层。适合的p型掺杂剂包括硼掺杂剂、铝掺杂剂、镓掺杂剂、铟掺杂剂、或类似掺杂剂。适合的n型掺杂剂包括氮掺杂剂、磷掺杂剂、砷掺杂剂、锑掺杂剂、或类似掺杂剂。尚有另一范例中，第一层212是III-V族材料，诸如GaAs层。
第二层214可以是含锗层，诸如SiGe层、Ge层、或其它适合的层。替代地，第二层214可以是掺杂的硅层，包括p型掺杂硅层或n型掺杂层。尚有另一范例中，第二层214是III-IV族材料，诸如GaAs层。还有另一范例中，第一层212可为硅层，而第二层214是金属材料，所述金属材料具有位于所述金属材料的外表面上的高k材料涂层。高k材料的适合的范例包括二氧化铪(HfO2)、二氧化锆(ZrO2)、硅酸铪(HfSiO4)、氧化铪铝(HfAlO)、硅酸锆(ZrSiO4)、二氧化钽(TaO2)、氧化铝、铝掺杂的二氧化铪、铋锶钛(BST)、或铂锆钛(PZT)，等等。一个特定实施方式中，涂层是二氧化铪(HfO2)层。应注意，基板材料及堆叠204中的第一层212与第二层214的选择可为利用如上所列的材料的不同组合。
在图2A中描绘的特定范例中，第一层212是结晶硅层，诸如单一结晶、多晶、或单晶硅层。第二层214是SiGe层。虚拟栅极208及栅极间隔物210可沉积在堆叠204的顶部上。一些范例中，硬掩模层(未示于图2中)及/或图案化光刻胶层可设置在虚拟栅极208、栅极间隔物210、及堆叠204上以进行图案化。图2A中所示的范例中，虚拟栅极208、栅极间隔物210、及堆叠204已于先前的图案化工艺中被图案化，从而暴露堆叠204的第一侧216并暴露堆叠204的第二侧218，第一侧216与第二侧218稍后可形成有邻近第一侧206及第二侧208的源极/漏极锚(anchor)。第一侧216与第二侧218相对并与基板202正交。
在操作104，蚀刻堆叠204以移除一些材料并在堆叠204的第一侧216及堆叠204的第二侧218的每一个上产生一个或多个凹部220，如图2B1及图2B2所示。一个实施方式中，凹部220选择性形成于堆叠204的第二层214内，如图2B1所示。另一实施方式中，凹部220选择性形成于堆叠204的第一层212内，如图2B2所示。凹部的深度大约是栅极间隔物210的宽度222。一个实施方式中，处理腔室(诸如图4的腔室400)内包括氟离子及自由基的等离子体用于选择性蚀刻一个或多个凹部220。处理腔室内的包括氟离子及自由基与氧离子及自由基的等离子体可用于选择性蚀刻一个或多个凹部220。也可包括氮离子及自由基。氟碳化合物前驱物可以以介于约300sccm至500sccm之间的流速流动。氧自由基可用于控制堆叠204的第二层214的蚀刻速率。另一实施方式中，氧自由基与氮自由基用于控制堆叠204的第一层212的蚀刻速率。氧离子与自由基可以以介于约10sccm至40sccm之间的流速使流动。氮离子与自由基可以以介于约10sccm至40sccm之间的流速流动。
在操作106，介电层224可沉积于堆叠204的侧壁216、218上并沉积于堆叠204的第一侧216与第二侧218的每一个的一个或多个凹部220的每一个内，如图2C1与图2C2中所示。介电层224也可沉积在栅极间隔物210上。介电层224可在凹部220内提供遮蔽，而防止下文所述的外延生长。介电层224衬在(line)凹部220的内表面上，同时维持凹部220内的气袋(air pocket)。一个实施方式中，介电层224衬在于第二层214内形成的凹部220的内表面上，同时维持凹部220内的气袋，如图2C1所示。另一实施方式中，介电层224衬在于第一层212内形成的凹部220的内表面上，同时维持凹部220内的气袋，如图2C2所示。介电层224可以从可防止在外延生长期间的沉积的材料中选择。一个实施方式中，介电层224是含硅介电层，诸如含氮化硅层、含碳化硅层、含硅氧层，举例而言，氧化硅、氮化硅(SiN)、氮氧化硅(SiON)、碳化硅(SiC)、氮碳化硅(SiCN)、碳氧化硅(SiOC)或氮碳氧化硅，或有掺杂剂的硅材料，及类似材料。在含硅介电层中形成的掺杂剂可具有相对低的浓度。介电层也可含有富含硅的膜性质。一个范例中，介电层224是氮化硅层或氮氧化硅(SiON)，并具有介于约5埃至约50埃之间，诸如约10埃的厚度。介电层224可通过CVD工艺、ALD工艺、或在PVD、CVD、ALD、或其它适合的等离子体处理腔室中的任何适合的沉积技术形成。
在操作108，在介电层224被形成在堆叠204的侧壁216、218上及凹部220内之后，来自堆叠204的第一侧216及堆叠204的第二侧218的每一个的介电材料被选择性地移除，如图2D1与图2D2中所示。介电材料226保留在第一侧216与第二侧218的凹部220内。换言之，介电材料226覆盖凹部220的内壁。一个实施方式中，介电材料226覆盖在第二层214内形成的凹部220的内壁，如图2D1所示。另一实施方式中，介电材料226覆盖在第一层212内形成的凹部220的内壁，如图2D2所示。介电材料224也从栅极间隔物210移除。通过从侧壁216、218选择性移除介电材料224并使介电材料226保持在凹部220内，这些凹部的内壁有利地屏蔽了在后续步骤的外延生长。
在操作110，可执行选择性沉积以将应力源层228沉积在第一侧216与第二侧218附近，如图2E1与图2E2中所示。应力源层228选择性沉积在未受介电材料226保护的某些区域上。可选择性图案化应力源层228，以移除与栅极间隔物210相邻的一部分。应力源层228稍后可称为环绕式栅极晶体管的源极/漏极。在操作112，一个或多个气隙(air gap)230形成于应力源层228与堆叠204的第一侧216之间及应力源层228与堆叠204的第二侧218之间，如图2E中所示。一个实施方式中，应力源层228的选择性沉积会在第二层214的边缘上形成气隙230。换言之，气隙230形成在第二层214与应力源层228之间，如图2E1至图2F1中所示。另一实施方式中，应力源层228的选择性沉积会在第一层212的边缘上形成气隙230，如图2E2至图2F2中所见。换言之，气隙230形成在第一层212与应力源层228之间。一个实施方式中，气隙230中的空气含有氧。可想象，气隙230中的空气可含有下述的至少一者：氢、氧、氩、氮、氦、或上述物质的混合物。如图2E1与图2E2中可以看出，水平环绕式半导体元件200可包括一个或多个气隙，这些气隙设置在堆叠204的第二层214与应力源层228之间，或堆叠204的第一层21与应力源层228之间，应力源层228可成为源极或漏极。一个实施方式中，虚拟栅极208随后被置换金属栅极(replacement metal gate,RMG)232置换，如图2F中所示。另一实施方式中，虚拟栅极208与第二层214两者被蚀刻并被置换金属栅极置换。换言之，虚拟栅极208可被金属栅极232置换，且第二层214可被金属栅极234置换。
电容直接与所用的材料的介电常数相关。相较于氧化材料及间隔物材料，气隙具有最小的介电常数k。因此，通过使用具有最小介电常数的方法，栅极与源极/漏极之间的寄生电容也可有利地受到限制。上述方法有利地运用k值在1左右的气隙，以限制水平环绕式栅极结构中的寄生电容。
一个实施方式中，可于适合的等离子体处理腔室中执行选择性沉积工艺，所述腔室包括处理腔室，诸如图4中所描绘的处理腔室400或其它适合的等离子体腔室。处理温度被控制在低温度范围，诸如低于摄氏1200度。一个实施方式中，沉积工艺可在含有等离子体的环境、热环境(诸如高温炉)或热等离子体环境中执行，热等离子体环境诸如等离子体增强化学气相沉积工艺(plasma enhanced chemical vapor deposition,PECVD)、低压化学气相沉积工艺(low pressure chemical vapor deposition,LPCVD)、次大气压化学气相沉积工艺(sub-atmospheric chemical vapor deposition,SACVD)、大气压化学气相沉积工艺(atmospheric chemical vapor deposition,APCVD)。
在一个或多个气隙230形成于膜堆叠204中之后，堆叠204可用作水平环绕式栅极结构中的纳米线，其具有减少的寄生电容和最小化的元件漏损。
图3A显示根据一个实施方式的水平环绕式栅极(hGAA)结构300。hGAA结构300可实质上类似于hGAA结构200，如图2E1中所示。另一实施方式中，hGAA结构300实质上类似于hGAA结构200，如图2E2中所示。水平环绕式栅极结构300包括基板302、可选的材料层306、源极332、漏极334、栅极308、栅极间隔物310、及堆叠304。
堆叠304可设置在基板302上。一个实施方式中，栅极304沉积在可选的材料层306上。堆叠304包括第一侧316与第二侧318。第一侧316与第二侧318相对。第一侧318与基板302正交。堆叠304可包括重复多对的第一层312与第二层314。一个实施方式中，堆叠304含有至少重复四对的第一层312与第二层314。堆叠304包括一个或多个气隙330。一个实施方式中，气隙330设置在第二层314的端部处。换言之，第二层314在两个端盖气隙330之间。另一实施方式中，气隙330设置在第一层312的端部处。换言之，第一层312在两个端盖气隙330之间。
第一层312可以是由外延沉积工艺形成的结晶硅层，诸如单一结晶、多晶、或单晶硅层。替代地，第一层312可以是掺杂的硅层，包括p型掺杂硅层或n型掺杂层。适合的p型掺杂剂包括硼掺杂剂、铝掺杂剂、镓掺杂剂、铟掺杂剂、或类似掺杂剂。适合的n型掺杂剂包括氮掺杂剂、磷掺杂剂、砷掺杂剂、锑掺杂剂、或类似掺杂剂。尚有另一范例中，第一层312可为III-V族材料，诸如GaAs层。
第二层314可以是含锗层，诸如SiGe层、Ge层、或其它适合的层。替代地，第二层314可以是掺杂的硅层，包括p型掺杂硅层或n型掺杂层。尚有另一范例中，第二层314是III-V族材料，诸如GaAs层。还有另一范例中，第一层312可为硅层，而第二层314是金属材料，所述金属材料具有位于所述金属材料的外表面上的高k材料涂层。高k材料的适合的范例包括二氧化铪(HfO2)、二氧化锆(ZrO2)、硅酸铪(HfSiO4)、氧化铪铝(HfAlO)、硅酸锆(ZrSiO4)、二氧化钽(TaO2)、氧化铝、铝掺杂的二氧化铪、铋锶钛(BST)、或铂锆钛(PZT)，等等。一个特定实施方式中，涂层是二氧化铪(HfO2)层。应注意，基板材料及堆叠304中的第一层312与第二层314的选择可为利用如上所列的材料的不同组合。
源极332设置在堆叠304的第一侧316附近且与基板302正交。漏极334设置在堆叠304的第二侧318附近且与基板302正交。源极332与漏极334相对。换言之，堆叠304设置在源极332与漏极334之间。一个实施方式中，第一组的一个或多个气隙330设置在源极332与堆叠304之间，具体而言，在源极332与堆叠304的第二层314之间。第二组的一个或多个气隙330设置在漏极334与堆叠304之间，具体而言，在漏极334与堆叠304的第二层314之间。
栅极308设置在堆叠304上。栅极308环绕堆叠304。一个实施方式中，栅极308设置在两侧上的间隔物310之间。换言之，栅极间隔物310可设置在栅极308的任意一侧上。栅极间隔物310也可环绕堆叠304。一个实施方式中，栅极间隔物环绕堆叠304的气隙330并与堆叠304的气隙330对齐。
图3B描绘不具有栅极间隔物层的hGAA元件300的剖面示意图。hGAA元件300包括多对的第一层312及第二层314，且气隙330形成于其中。水平环绕式栅极(hGAA)结构300利用堆叠304作为分别介于源极/漏极锚定件332、334与栅极结构308之间的纳米线(例如通道)。如图3C中圆圈340所指的堆叠304的放大视图中所示，在第二层314或第一层312的底部(或例如端部)形成的气隙330可助于管理介面(其中第二层314或第一层312接触栅极结构308及/或源极/漏极锚332、334)，以便减少寄生电容及维持最小的元件漏损。
图4是适合用于执行上文进一步叙述的选择性工艺的说明性处理系统432的剖面视图。所述处理系统432可以是
Figure BDA0004068175540000101
或
Figure BDA0004068175540000102
其皆可购自美国加州Santa Clara的应用材料公司。应设想，其它处理系统(包括购自其它贩售商的处理系统)可适于实行本公开内容。
处理系统432包括处理腔室400，处理腔室400耦接气体分配板430与控制器410。处理腔室400大体上包括界定内部容积426的顶部424、侧部401、及底壁422。
支撑底座450设置在腔室400的内部容积426中。底座450可由铝、陶瓷、或其它适合材料制造。底座450可包括嵌入的加热器元件470，加热器元件470适合用于控制支撑在底座450上的基板490的温度。一个实施方式中，通过从电源供应器406施加电流至加热器元件470而电阻加热底座450。从电源供应器406供应的电流由控制器410调控，以控制加热器元件470所生成的热，从而在任何适合温度范围内，在膜沉积期间将基板490与底座450维持在实质恒定的温度。
温度传感器472(诸如热电偶)可嵌在支撑底座450中，以用现有方式监控底座450的温度。控制器410使用测量到的温度，以控制供应至加热器元件470的功率，而将基板维持在期望温度。
真空泵402耦接腔室400的壁401中形成的端口。真空泵402用于维持处理腔室400中的期望气体压力。真空泵402也从腔室400抽空后处理气体及工艺副产物。
具有多个孔(aperture)428的喷头420在基板支撑底座450上方耦接处理腔室400的顶部424。喷头420的孔428用于将处理气体引入腔室400。孔428可具有不同尺寸、数目、分布、形状、设计、与直径，以有助于针对不同工艺需求的各种处理气体的流动。喷头420连接气体分配板430，气体分配板430允许各种气体在工艺期间供应至内部容积426。等离子体由离开喷头420的处理气体混合物形成，以增强处理气体的热分解，造成材料沉积于基板490的表面491上。
一个或多个射频电源440通过匹配网路438为喷头420提供偏压电位，以有助于在喷头420及底座450之间生成等离子体。控制器410包括中央处理单元(CPU)412、存储器416、及支援电路414，以用于控制处理序列及调控来自气体分配板430与WVG系统452的气流。控制器410与处理系统432的各种部件之间的双向通讯是通过多个个信号缆线来处理的，这些信号缆线通称信号总线418，其中一些说明于图4中。
图5描绘半导体处理系统500的平面图，其中可实施本文所述的方法。可适于受惠于本公开内容的一个处理系统是300mm的
Figure BDA0004068175540000111
处理系统，其可购自美国加州Santa Clara的应用材料公司。处理系统500大体上包括：前端平台502，其中包括在FOUP514中的基板匣518被支撑，且基板装载至装载栅腔室509并从装载栅腔室509卸载；移送腔室511，容纳基板处置器513；及一系列串接的处理腔室506，这些处理腔室506装设在移送腔室511上。
每个串接处理腔室506包括两个处理区域以处理基板。两个处理区域共用共通的气体供应器、共通的压力控制、及共通的处理气体排气/泵送系统。系统的模块化设计使得能够从任一种组装方式快速转换到任何其它组装方式。腔室的布置与组合可为了执行特定工艺步骤而更改。根据下文所述的本公开内容的方面，串接处理腔室506的任一者可包括盖，这些方面包括一个或多个腔室组装方式，如上文参考图4所绘的处理腔室400所述。应注意，处理腔室400可装设成根据需求执行沉积工艺、蚀刻工艺、固化工艺、或加热/退火工艺。一个实施方式中，处理腔室400(图中显示为所设计的单一腔室)可并入半导体处理系统500中。
一个实施方式中，处理系统432可适应串接处理腔室的一个或多个，所述处理腔室具有已知支援腔室硬件，以与各种其它已知工艺相容，诸如化学气相沉积(CVD)、物理气相沉积(PVD)、蚀刻、固化、或加热/退火、及类似工艺。
控制器540包括中央处理单元(CPU)544、存储器542、与支援电路546，控制器540耦接半导体处理系统500的各种部件，以有助于控制本公开内容的工艺。储存于存储器542中的软件程序或一系列的程序指令在由CPU544执行时，会执行这些串接处理腔室506。
从而，提供多种形成纳米线结构的方法，所述纳米线结构用于水平环绕式栅极(hGAA)结构且有减少的寄生电容及最小化的元件漏损。这些方法利用沉积工艺以在来自堆叠的某些类型的材料上选择性地形成气隙，从而形成具有在介面处减少的寄生电容和最小化的元件漏损的纳米线结构，所述纳米线结构稍后可用于形成水平环绕式栅极(hGAA)结构。从而，尤其是针对水平环绕式栅极场效应晶体管(hGAA FET)的应用，可获得有期望类型的材料及元件电性能的水平环绕式栅极(hGAA)结构。
虽然前述内容涉及本公开内容的实施方式，但可在不背离本公开内容的基本保护范围的情况下，设计本公开内容的其它与进一步实施方式，本公开内容的保护范围由随附的权利要求书所决定。

Claims (20)

1.一种纳米线结构，包括：
堆叠，所述堆叠包括重复多对的第一层与第二层，其中所述堆叠具有第一侧及第二侧，所述第一侧与所述第二侧相对；
栅极结构，所述栅极结构环绕所述堆叠；
源极层，所述源极层邻近所述第一侧；
漏极层，所述漏极层邻近所述第二侧；
间隙，所述间隙设置在所述源极层与所述第二层的每一者之间，并且设置在所述漏极层与所述第二层的每一者之间；以及
介电材料，所述介电材料在所述间隙内设置于所述第一层和所述第二层上。
2.根据权利要求1所述的纳米线结构，其中所述间隙的每一者含有下述的至少一者：氢、氧、氩、氮、氦、或上述物质的混合物。
3.根据权利要求1所述的纳米线结构，其中所述第一层的每一者是硅层，且所述第二层的每一者是SiGe层。
4.根据权利要求1所述的纳米线结构，其中所述堆叠包括至少重复四对的所述第一层和所述第二层。
5.根据权利要求2所述的纳米线结构，其中所述间隙的每一者含有氧、氮、以及氢、氦中的至少一者、或上述物质的混合物。
6.根据权利要求1所述的纳米线结构，其中所述间隙的每一者的介电常数的值约为1。
7.根据权利要求1所述的纳米线结构，其中所述介电材料包含氮化硅、氧化硅、氮氧化硅、碳氧化硅、氮碳化硅、氮碳氧化硅、具掺杂剂的硅材料、氮化物、氮氧化物、或上述材料的混合物。
8.根据权利要求7所述的纳米线结构，其中所述介电材料包括氮化硅、氧化硅或氮氧化硅。
9.根据权利要求1所述的纳米线结构，其中所述介电材料包含具有厚度为约5埃至约50埃的氮氧化硅层。
10.根据权利要求1所述的纳米线结构，其中所述介电材料是通过原子层沉积工艺产生的。
11.根据权利要求1所述的纳米线结构，其中所述堆叠位于包含氧化硅、氮化硅或氮氧化硅的材料层上。
12.根据权利要求11所述的纳米线结构，其中所述材料层位于包含硅的基板上。
13.一种纳米线结构，包括：
位于基板上的堆叠，其中所述堆叠包括重复多对的第一层与第二层，且其中所述堆叠具有第一侧及第二侧，所述第一侧与所述第二侧相对；
栅极结构，所述栅极结构环绕所述堆叠；
源极层，所述源极层邻近所述第一侧；
漏极层，所述漏极层邻近所述第二侧；
间隙，所述间隙设置在所述源极层与所述第二层的每一者之间，并且设置在所述漏极层与所述第二层的每一者之间，其中所述间隙的每一者的介电常数的值约为1；以及
介电材料，所述介电材料在所述间隙内设置于所述第一层和所述第二层上。
14.根据权利要求13所述的纳米线结构，其中所述间隙的每一者含有下述的至少一者：氢、氧、氩、氮、氦、或上述物质的混合物。
15.根据权利要求13所述的纳米线结构，其中所述间隙的每一者含有氧、氮、以及氢、氦中的至少一者、或上述物质的混合物。
16.根据权利要求13所述的纳米线结构，其中所述介电材料包含氮化硅、氧化硅或氮氧化硅。
17.根据权利要求13所述的纳米线结构，所述介电材料具有约5埃至约50埃的厚度，并且是通过原子层沉积工艺产生的。
18.根据权利要求13所述的纳米线结构，其中所述第一层的每一者是硅层，且所述第二层的每一者是SiGe层。
19.根据权利要求13所述的纳米线结构，其中所述堆叠包括至少重复四对的所述第一层和所述第二层。
20.一种纳米线结构，包括：
堆叠，所述堆叠包括重复多对的第一层与第二层，其中所述堆叠具有第一侧及第二侧，所述第一侧与所述第二侧相对，并且其中所述堆叠包括至少重复四对的所述第一层和所述第二层；
栅极结构，所述栅极结构环绕所述堆叠；
源极层，所述源极层邻近所述第一侧；
漏极层，所述漏极层邻近所述第二侧；
间隙，所述间隙设置在所述源极层与所述第二层的每一者之间，并且设置在所述漏极层与所述第二层的每一者之间，其中所述间隙的每一者的介电常数的值约为1；以及
介电材料，所述介电材料在所述间隙内设置于所述第一层和所述第二层上。
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