WO2022032488A1 - 场效应晶体管及其制造方法 - Google Patents

场效应晶体管及其制造方法 Download PDF

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WO2022032488A1
WO2022032488A1 PCT/CN2020/108485 CN2020108485W WO2022032488A1 WO 2022032488 A1 WO2022032488 A1 WO 2022032488A1 CN 2020108485 W CN2020108485 W CN 2020108485W WO 2022032488 A1 WO2022032488 A1 WO 2022032488A1
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layer
insulating
semiconductor material
gate
effect transistor
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PCT/CN2020/108485
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English (en)
French (fr)
Inventor
万光星
黄威森
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华为技术有限公司
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Priority to CN202080102318.4A priority Critical patent/CN115702487A/zh
Priority to PCT/CN2020/108485 priority patent/WO2022032488A1/zh
Publication of WO2022032488A1 publication Critical patent/WO2022032488A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a field effect transistor and a method for manufacturing the same.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • FinFET fin field-effect transistor
  • surrounding gate devices New devices such as gate-all-around, GAA
  • nanowires or nanosheets are the technologies most likely to be adopted for mass production.
  • the channel of GAA is completely surrounded by the gate, and a sacrificial layer is required to complete the release of the channel.
  • a first semiconductor material layer 11 and a second semiconductor material layer 12 are generally stacked in sequence, and a dummy gate structure 13 located on the first semiconductor material layer 11 forms a support structure 100 .
  • the first semiconductor material layer 11 and the dummy gate structure 13 can be removed by an etching process, and then, as shown in FIG. 2 ,
  • the positions of the first semiconductor material layer 11 and the dummy gate structure 13 can be filled with gate material, for example, a high-k metal gate (high-k metal gate), through an RMG (replacement metal gate) process. materials and metal materials (such as TiN) to form the real gate 21 .
  • the gate electrode 21 and the source electrode 14 are isolated after the release of the sacrificial layer (the first semiconductor material layer 11 ), the gate electrode 21 and the source electrode 14 (or An inner spacer 22 is added between the drain electrodes 15).
  • the internal isolation layer 22 can control the gate length of the GAA, realize the isolation between the gate 21 and the source 14 (or the drain 15 ), and reduce parasitic capacitance, which is an extremely important part of the GAA process.
  • the material of the internal isolation layer 22 usually has a certain dielectric constant, thereby introducing additional parasitic capacitance between the gate electrode 21 and the source electrode 14 (or the drain electrode 15 ).
  • the present application provides a field effect transistor and a manufacturing method thereof, which can reduce the parasitic capacitance between the gate, the source and the drain.
  • a method for fabricating a field effect transistor includes the steps of: forming a support structure on a semiconductor substrate, the support structure comprising alternately arranged first semiconductor material layers and second semiconductor material layers, and isolation layers are arranged on both sides of the support structure; The boundary between the isolation layer and the support structure forms a dummy gate structure covering the support structure, and the length of the dummy gate structure in the gate length direction is less than the length of the first semiconductor material layer in the gate length direction, so
  • the gate length direction is used to indicate the transport direction of carriers in the field effect transistor; along the gate length direction, deposit a first insulating layer on both sides of the dummy gate structure; along the gate length direction, remove all In the second semiconductor material layer except the sacrificial layer, an insulating groove is formed, the interior of the insulating groove is hollowed out and filled with air, and the sacrificial layer is located in the dummy gate in the second semiconductor material layer.
  • a support structure is firstly formed on a semiconductor substrate, the support structure includes alternately arranged first semiconductor material layers and second semiconductor material layers, and isolation layers are provided on both sides of the support structure;
  • the boundary of the structure forms a dummy gate structure covering the supporting structure, the length of the dummy gate structure in the gate length direction is less than the length of the first semiconductor material layer in the gate length direction, and the gate length direction is used to indicate the transport of carriers in the field effect transistor along the gate length direction, deposit the first insulating layer on both sides of the dummy gate structure; along the gate length direction, remove the area except the sacrificial layer in the second semiconductor material layer to form an insulating groove, and the interior of the insulating groove is hollowed out , filled with air, the sacrificial layer is the part of the second semiconductor material layer in the projection area of the dummy gate structure along the target direction, and the target direction is the direction perpendicular to the bottom surface of the semiconductor substrate; along the gate length direction, formed in the source and
  • the parasitic capacitance between the gate and the source and drain can be reduced, thereby reducing the parasitic capacitance between the gate and the source and drain.
  • the parasitic capacitance of the entire field effect transistor is reduced, and the performance and reliability of the field effect transistor are improved.
  • removing a region other than the sacrificial layer in the first semiconductor material layer to form an insulating groove includes: along the gate length direction, aligning the first semiconductor material layer on the first semiconductor material layer.
  • the second semiconductor material layer is subjected to a selective oxidation process, so that the region of the first semiconductor material layer other than the sacrificial layer is oxidized to form an insulating isolation wall, wherein the dielectric material of the insulating isolation wall is the second semiconductor material layer of oxide; after the gate is formed at the positions of the removed dummy gate structure and the sacrificial layer, the first insulating layer is removed; the insulating isolation wall is removed to form the insulating groove that is hollowed out and filled with air .
  • a selective oxidization process is performed on the second semiconductor material layer, so that in the second semiconductor material layer, the part outside the projection area of the dummy gate structure along the target direction is oxidized, and the oxidized part is oxidized.
  • Part of the space forms an insulating isolation wall, and a part of the second semiconductor material layer in the projection area of the dummy gate structure along the target direction is not oxidized to form a sacrificial layer.
  • the dielectric material of the insulating isolation wall is the oxide (eg, silicon oxide) of the second semiconductor material layer, and the insulating isolation wall is removed after the gate is formed in the subsequent step to form a hollowed-out insulating groove filled with air .
  • the hollowed-out, air-filled insulating groove can isolate the source (or drain) to be subsequently formed and the gate material filled with the sacrificial layer, for example, High-K (high dielectric constant) dielectric material and gate metal Materials, since the dielectric constant of air is low (the dielectric constant of air is about 1), the parasitic capacitance between the subsequently formed source (or drain) and the gate can be reduced.
  • the reason for forming the insulating isolation wall in this step is to avoid that the hollowed out insulating grooves filled with air that are directly formed in this step are filled with other deposited materials in subsequent steps.
  • the etching solution can be blocked to avoid etching to areas other than the sacrificial layer.
  • removing a region other than the sacrificial layer in the first semiconductor material layer to form an insulating groove includes: along the gate length direction, aligning the first semiconductor material layer on the first semiconductor material layer.
  • the second semiconductor material layer is selectively etched, so that the region other than the sacrificial layer in the second semiconductor material layer is removed to form the insulating groove; the insulating groove is filled with a dielectric material to form an insulating groove isolation wall; after the gate is formed at the position of the removed dummy gate structure and the sacrificial layer, the first insulating layer is removed; the insulating isolation wall is removed to form the insulating groove which is hollowed out and filled with air.
  • the second semiconductor material layer may be selectively etched (selectively removed) process, so that the part of the second semiconductor material layer that is outside the projection area of the dummy gate structure along the target direction is removed to form an insulating groove, and a portion of the second semiconductor material layer in the projection area of the dummy gate structure along the target direction is retained to form a sacrificial layer.
  • the hollowed-out, air-filled insulating groove can isolate the source (or drain) to be subsequently formed and the gate material filled with the sacrificial layer, for example, High-K (high dielectric constant) dielectric material and gate metal Since the dielectric constant of air is low (the dielectric constant of air is about 1), the parasitic capacitance generated by the source (or drain) and gate materials formed subsequently can be reduced.
  • the reason for filling the insulating grooves with dielectric materials to form insulating isolation walls in this step is to prevent the hollowed-out insulating grooves inside and filled with air from being filled with other deposition materials in subsequent steps. In addition, when replacing the sacrificial layer in the subsequent steps, it can be avoided that the etching solution is blocked to avoid etching to areas other than the sacrificial layer.
  • the method further includes: depositing a second insulating layer on the periphery of the gate, and the sidewall of the second insulating layer is aligned with the sidewall of the isolation layer flat; in the cross-sectional direction of the gate structure, both ends of the insulating groove are blocked by the second insulating layer.
  • the material in the subsequent manufacturing process fills up the insulating groove again.
  • nanosheet devices nanosheet devices
  • a material with less fluidity is usually used to deposit the second insulating layer, with the help of the second insulating layer.
  • the hollow part of the insulating groove forms a closed space to prevent the material of the second insulating layer from entering the insulating groove.
  • the method further includes: forming a barrier layer on the inner surface of the insulating groove.
  • a barrier layer may be formed on the inner surface of the insulating groove by an ALD (Atomic Layer Deposition, atomic layer deposition) or CVD process.
  • ALD Atomic Layer Deposition, atomic layer deposition
  • CVD chemical vapor deposition
  • the blocking layer can prevent the etching solution from being etched to areas other than the sacrificial layer.
  • the area surrounded by the barrier layer is air.
  • Air is a medium with a low dielectric constant, which can isolate the subsequently formed source (or drain) from the gate material filling the sacrificial layer, thereby reducing the direct contact between the subsequently formed source (or drain) and the gate material.
  • forming a support structure on a semiconductor substrate includes: alternately growing a periodic superlattice structure of a first semiconductor material layer and a second semiconductor material layer on the semiconductor substrate, the first semiconductor material layer being a periodic superlattice structure.
  • the thicknesses of the semiconductor material layer and the second semiconductor material layer are both less than 50 nm; the superlattice structure is etched to form the fin-shaped support structure.
  • forming a dummy gate structure covering the support structure along the boundary between the isolation layer and the support structure includes: forming an oxide layer on the exposed support structure; A dummy gate structure covering the support structure is formed on the layer.
  • a field effect transistor comprising a source electrode and a drain electrode, and a stack structure in which a channel including a channel and a gate are overlapped and stacked is formed between the source electrode and the drain electrode, and the gate electrode is overlapped and stacked.
  • An insulating groove which is hollowed out and filled with air is formed between the electrode and the source electrode and the drain electrode.
  • the channel is a semiconductor material layer, the material layer of the semiconductor material layer is in contact with the source electrode at one end of the channel, and the semiconductor material layer is in contact with the drain electrode at the other end of the channel; the adjacent Between the two semiconductor layers, an insulating groove hollowed out and filled with air is formed between the gate electrode and the source electrode or the drain electrode.
  • a barrier layer is formed on the inner surface of the insulating groove, and the opening of the insulating groove faces the source electrode or the drain electrode.
  • both ends of the insulating groove are provided with a second insulating layer, and the second insulating layer blocks the insulating groove.
  • a chip including the above field effect transistor.
  • an electronic device comprising a circuit board and a chip connected to the circuit board, the chip is provided with the above-mentioned field effect transistor.
  • FIG. 1 is a schematic structural diagram of a field effect transistor in a manufacturing process according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a field effect transistor according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a field effect transistor according to another embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method for fabricating a field effect transistor according to an embodiment of the present application
  • FIG. 5 is a first structural schematic diagram in a manufacturing process of a field effect transistor according to an embodiment of the present application
  • FIG. 6 is a second structural schematic diagram in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 7 is a third structural schematic diagram in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 8 is a fourth schematic structural diagram in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram 5 in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 10 is a sixth structural schematic diagram in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 11 is a seventh structural schematic diagram in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram eight in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram 9 in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram ten of a field effect transistor in a manufacturing process according to an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram eleven in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram 12 during the manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram thirteen in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram fourteen during a manufacturing process of a field effect transistor provided by an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram fifteenth during a manufacturing process of a field effect transistor provided by an embodiment of the present application.
  • FIG. 20 is a sixteenth schematic structural diagram in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 21 is a schematic structural diagram seventeen in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 22 is a schematic structural diagram eighteen in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 23 is a nineteenth structural schematic diagram in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • FIG. 24 is a schematic structural diagram 20 in a manufacturing process of a field effect transistor according to an embodiment of the present application.
  • circuits or other components may be described or referred to as “for” performing one or more tasks.
  • “for” is used to connote structure by indicating that the circuit/component includes structure (eg, circuitry) that performs one or more tasks during operation.
  • the specified circuit/component may be said to be used to perform the task even when the specified circuit/component is not currently operational (eg, not turned on).
  • Circuits/components used with the phrase “for” include hardware, such as circuits that perform operations, and the like.
  • At least one (a) of a, b or c may represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be It can be single or multiple.
  • words such as “first” and “second” do not limit the quantity and order.
  • Embodiments of the present application provide a field effect transistor, which may be a MOSFET, for example, a stacked gate-all-around nanowire transistor, a fin field-effect transistor , FinFET), etc., can also be a tunneling field effect transistor (tunneling field effect transistor, TFET), etc., which are not limited in the embodiments of the present application. Furthermore, embodiments of the present application may be applied to nanowire or nanosheet products.
  • a field effect transistor which may be a MOSFET, for example, a stacked gate-all-around nanowire transistor, a fin field-effect transistor , FinFET), etc.
  • TFET tunneling field effect transistor
  • FIG. A schematic diagram of the structure of the effect transistor, wherein a gate 32 is provided on the semiconductor substrate 31, and the two sides of the gate 32 are source and drain regions, and fin-shaped source 33 and drain 34 are respectively provided. Then, along the XX' direction It is used to indicate the gate length direction of the field effect transistor, that is, the transport direction of carriers in the field effect transistor; along the YY' direction, it is used to indicate the cross-sectional direction of the gate structure of the field effect transistor, and the gate length direction is related to the gate structure.
  • FIG. 3 only shows the structures of one group of gates 32 , source 33 and drain 34 in the field effect transistor. It can be understood that the field effect transistor may also include multiple groups of gates with similar structures. electrode, source electrode and drain electrode, which are not limited in this embodiment of the present application.
  • an embodiment of the present application provides a method for fabricating a field effect transistor, as shown in FIG. 4 , including:
  • a support structure is formed on a semiconductor substrate, where the support structure includes alternately arranged first semiconductor material layers and second semiconductor material layers, and isolation layers are arranged on both sides of the support structure.
  • the semiconductor substrate can be bulk silicon (bulk silicon), SOI (silicon-on-insulator, silicon on insulating substrate) substrate, ETSOI (extremely thin SOI, ultra-thin SOI) substrate, SGOI (siGe- on-insulator, germanium-silicon on insulating substrate) substrate or IIIV-OI (IIIV-on-insulator, IIIV compound on insulating substrate) substrate, etc., which are not limited in this embodiment of the present application.
  • the first semiconductor may be alternately grown on the semiconductor substrate 51 first.
  • the periodic superlattice structure of the material layer 52 and the second semiconductor material layer 53 wherein the superlattice structure refers to the alternate growth and maintenance of two different components in thin layers of several nanometers to tens of nanometers Strictly periodic multilayer films.
  • the thicknesses of the first semiconductor material layer 52 and the second semiconductor material layer 53 can both be less than 50 nm.
  • the second semiconductor material layer 53 can be a germanium silicon material.
  • the superlattice structure composed of the first semiconductor material layer 52 and the second semiconductor material layer 53 can be etched to form the support structure 61 shown in FIG. 7 and FIG. 8 .
  • the support structure 61 It may be provided on the semiconductor substrate 51 in a fin shape. 7 is a schematic cross-sectional view along the gate length direction, and FIG. 8 is a cross-sectional schematic view along the cross-sectional direction of the gate structure.
  • a shallow trench isolation can be formed on the above-mentioned substrate, for example, CMP (chemical mechanical flattening) can be continued. , chemical mechanical planarization) process and etch back (Recess) process to form isolation layers 71 on both sides of the support structure 61 .
  • the thickness of the isolation layer 71 is the same as the thickness of the etched semiconductor substrate 51 .
  • the isolation layer 71 may be specifically made of oxides such as silicon oxide or nitrides such as silicon nitride, which are not limited in this embodiment of the present application.
  • a dummy gate structure 81 covering the support structure 61 may be further formed on the isolation layer 71 .
  • the support structure 61 is embedded in the isolation layer 71 and the dummy gate. in the gap formed by the structure 81 .
  • the length of the dummy gate structure 81 in the gate length direction is smaller than the length of the first semiconductor material layer 52 in the gate length direction.
  • the dummy gate structure 81 may be specifically made of polysilicon or amorphous silicon material, which is not limited in this embodiment of the present application.
  • an oxide layer (dummy oxide), such as silicon oxide, may be formed on the exposed support structure 61 first; and then the dummy gate structure 81 covering the support structure 61 may be formed by etching on the oxide layer.
  • dummy oxide such as silicon oxide
  • a first insulating layer 91 may also be deposited on the periphery of the dummy gate structure 81 , and the sidewalls of the first insulating layer 91 are aligned with the sidewalls of the isolation layer 71 in the cross-sectional direction of the gate structure.
  • the first insulating layer 91 may be silicon nitride or silicon oxide.
  • the dummy gate structure 81 when forming the dummy gate structure 81, the anisotropy of etching is ensured as much as possible, and the etching selection ratio of polysilicon:silicon oxide is adjusted as high as possible, so as to form the dummy gate structure 81 with a relatively steep shape , the dummy gate structure 81 with a relatively steep shape is beneficial to make the dummy gate structure 81 and the first insulating layer 91 fit better when the first insulating layer 91 is subsequently formed.
  • the above-mentioned sacrificial layer is located in the second semiconductor material layer 53 in the dummy gate structure 81 along the target direction (the target direction is the direction perpendicular to the bottom surface of the semiconductor substrate 51 , that is, the orthographic projection direction of the dummy gate structure 81 on the second semiconductor material layer 53 ). ) part of the projected area.
  • the first semiconductor material layer 52 and the second semiconductor material layer 53 may be etched along the sidewall of the first insulating layer 91 first, so that the first semiconductor material layer 52 and the sidewalls of the second semiconductor material layer 53 are aligned with the first insulating layer 91 (as shown in FIGS. 11 and 12 ).
  • Method 1 Perform a selective oxidization process on the second semiconductor material layer 53 shown in FIG. 12 , so that the second semiconductor material layer 53 is outside the projection area of the dummy gate structure 81 along the target direction. Part of it is oxidized, and the oxidized part of the space forms the insulating isolation wall 103 as shown in FIG. 13 , and in the second semiconductor material layer 53, the part in the projection area of the dummy gate structure 81 along the target direction is not oxidized, forming The sacrificial layer 102 shown in FIG. 13 .
  • the dielectric material of the insulating isolation wall 103 is filled with the oxide (eg, silicon oxide) of the second semiconductor material layer 53, and the insulating isolation wall 103 is removed after the gate is formed in the subsequent steps, forming an inner hollow, filled with Insulating grooves 101 for air (as shown in Figure 23).
  • the oxide eg, silicon oxide
  • the hollowed-out, air-filled insulating groove 101 can isolate the source (or drain) to be subsequently formed and the gate material filled with the sacrificial layer 102, for example, a High-K (high dielectric constant) dielectric material and the gate
  • the dielectric constant of air is low (the dielectric constant of air is about 1)
  • the parasitic capacitance between the source (or drain) and the gate formed subsequently can be reduced.
  • the reason why the insulating isolation walls 103 are formed in this step is to avoid that the hollowed out insulating grooves 101 filled with air that are directly formed in this step are filled with other deposited materials in subsequent steps.
  • the etching solution may be blocked to avoid etching to areas other than the sacrificial layer 102 .
  • the second semiconductor material layer 53 shown in FIG. 12 may be selectively etched (selectively removed) process, so that the second semiconductor material layer 53 In the second semiconductor material layer 53, the part outside the projection area of the dummy gate structure 81 along the target direction is removed to form an insulating groove 101 as shown in FIG. A portion is left to form a sacrificial layer 102 as shown in FIG. 14 .
  • a dielectric material is filled in the insulating groove 101 to form an insulating isolation wall 103 , for example, the dielectric material is oxide or nitride (specifically, silicon oxide or silicon nitride); the insulating isolation wall 103 is in the subsequent steps.
  • the gate is removed to form an insulating groove 101 filled with air and hollowed out inside.
  • the air-filled, hollowed-out insulating groove 101 can isolate the subsequently formed source (or drain) and the gate material filled with the sacrificial layer 102, for example, a High-K (high dielectric constant) dielectric material and the gate
  • the dielectric constant of air is relatively low (the dielectric constant of air is about 1), the parasitic capacitance generated by the subsequently formed source (or drain) and gate materials can be reduced.
  • the reason for filling the insulating grooves 101 with dielectric materials to form the insulating isolation walls 103 in this step is to prevent the hollowed-out insulating grooves 101 filled with air from being filled with other deposition materials in subsequent steps.
  • the etching solution is blocked to avoid etching to areas other than the sacrificial layer 102 .
  • the second semiconductor material layer 53 shown in FIG. 12 may be selectively etched (selectively removed) process, so that the second semiconductor material layer 53 , the dummy gate structure 81 is removed in the area other than the projection area of the second semiconductor material layer 53 to form the insulating groove 101 as shown in FIG. left to form a sacrificial layer 102 as shown in FIG. 14 .
  • the barrier layer 111 may be formed on the inner surface of the insulating groove 101 by an ALD (Atomic Layer Deposition, atomic layer deposition) or CVD process, as shown in FIG. 16 .
  • the blocking layer 111 can prevent the etching solution from being etched to areas other than the sacrificial layer 102 .
  • the area surrounded by the barrier layer 111 is air. Air is a medium with a low dielectric constant, which can isolate the subsequently formed source (or drain) from the gate material that fills the sacrificial layer 102, thereby reducing the direct connection between the subsequently formed source (or drain) and the gate. Parasitic capacitance created between materials.
  • a source electrode and a drain electrode in the source-drain region along the gate length direction, and the source electrode and the drain electrode are isolated from the sacrificial layer by an insulating groove.
  • a selective epitaxy technique may be used to epitaxially grow materials such as silicon or germanium in the source and drain regions, and further, through a doping process, the source and drain regions may have a certain doping concentration, forming the structure shown in FIG. 17 or FIG. 18.
  • Source electrode 171 and drain electrode 172 are used to epitaxially grow materials such as silicon or germanium in the source and drain regions, and further, through a doping process, the source and drain regions may have a certain doping concentration, forming the structure shown in FIG. 17 or FIG. 18.
  • Source electrode 171 and drain electrode 172 Source electrode 171 and drain electrode 172 .
  • the insulating groove 101 is filled with a dielectric material, such as oxide, in this step, as shown in FIG. 17 .
  • a barrier layer 111 is formed on the surface layer of the insulating groove 101 in this step, as shown in FIG. 18 .
  • the materials of the source and drain electrodes will be epitaxially grown from the sidewalls of the first semiconductor material layer 52 in the gate length direction, so as to ensure that the grooves surrounded by the barrier layer 111 are filled with air and will not be blocked by other materials. material filled.
  • FIG. 19 shows the structure formed when the insulating groove 101 is fabricated corresponding to the first and second methods.
  • FIG. 19 shows the structure formed when the insulating groove 101 is fabricated according to the third mode.
  • the gate 211 shown in FIG. 21 and FIG. 22 is formed at the position of the removed dummy gate structure 81 and the sacrificial layer 102 (the gate 211 includes at least two Layer structure, one layer is a High-K dielectric material, and the other layer is a metal material with a specific work function, such as TiN), to form a field effect transistor.
  • 21 shows the structure formed when the insulating groove 101 is fabricated corresponding to the first and second methods.
  • FIG. 22 shows the structure formed when the insulating groove 101 is fabricated according to the third mode. When the insulating groove 101 is formed in the third method, go to step 407 to form a field effect transistor.
  • the insulating groove 101 is located at the insulating isolation wall 103 after the step 407 , that is, the insulating groove 101 is still filled with a dielectric material such as oxide or nitride. Therefore, it still brings parasitic capacitance between the gate and the source or drain. Therefore, it is also necessary to include the following steps to remove the dielectric material in the insulating groove.
  • the first insulating layer 91 blocks the insulating isolation wall 103 , in order to remove the insulating isolation wall 103 , the first insulating layer 91 needs to be removed first.
  • the insulating isolation wall can be removed by wet etching.
  • a second insulating layer 92 can be deposited on the periphery of the gate, and the sidewalls of the second insulating layer 92 It is flush with the sidewall of the isolation layer 71 ; in the cross-sectional direction of the gate structure, both ends of the insulating groove 101 are blocked by the second insulating layer 92 .
  • the second insulating layer 92 is usually deposited by a material with less fluidity. With the blocking effect of the second insulating layer 92 , the hollow portion of the insulating groove 101 forms a closed space, and on the other hand, the material of the second insulating layer 92 can be prevented from entering the insulating groove 101 .
  • an insulating groove 101 which is hollowed out and filled with air is provided between the gate electrode 211 and the source electrode 171 or the drain electrode 172 .
  • the parasitic capacitance between the gate, the source and the drain can be reduced, thereby reducing the parasitic capacitance of the entire field effect transistor and improving the performance and reliability of the field effect transistor.
  • the embodiments of the present application further provide a field effect transistor, and the field effect transistor may be a MOSFET or a tunneling field effect transistor, which is not limited in the embodiments of the present application.
  • the fabrication method of the field effect transistor provided by the embodiment of the present application reference may be made to the relevant content of steps 401 to 410 in the above-mentioned embodiment, so it is not repeated here.
  • the field effect transistor provided in the embodiment of the present application includes a source electrode 171 and a drain electrode 172 , and the source electrode 171 and the drain electrode 171 . Between 172 is formed a stack structure in which the channel (in the channel is the semiconductor material layer, that is, the first semiconductor material layer 52) and the gate electrode 211 are overlapped and stacked. An insulating groove 101 hollowed out inside and filled with air.
  • a barrier layer 111 is formed on the inner surface of the insulating recess 101 , and the opening of the insulating recess 101 faces the source electrode 171 or the drain electrode 172 .
  • both ends of the insulating groove 101 are provided with a second insulating layer 92 , and the second insulating layer 92 blocks the insulating groove 101 .
  • a support structure is first formed on a semiconductor substrate, and the support structure includes alternately arranged first semiconductor material layers and second semiconductor material layers.
  • the two sides of the support structure are provided with isolation layers; along the boundary between the isolation layer and the support structure, a dummy gate structure covering the support structure is formed, and the length of the dummy gate structure in the gate length direction is smaller than that of the first semiconductor material layer in the gate length direction.
  • the gate length direction is used to indicate the transport direction of carriers in the field effect transistor; along the gate length direction, deposit the first insulating layer on both sides of the dummy gate structure; along the gate length direction, remove the second semiconductor material layer in the gate length direction.
  • an insulating groove is formed, and the interior of the insulating groove is hollowed out.
  • the sacrificial layer is the part of the second semiconductor material layer in the projection area of the dummy gate structure along the target direction, and the target direction is perpendicular to the bottom surface of the semiconductor substrate.
  • source and drain are formed in the source and drain regions, and the source and drain are isolated from the sacrificial layer by insulating grooves; the dummy gate structure and the sacrificial layer are removed; the dummy gate structure and the sacrificial layer have been removed. position to form the gate. Since a hollow insulating groove is set between the gate and the source or drain, that is, through air isolation, the parasitic capacitance between the gate and the source and drain can be reduced, thereby reducing the parasitic capacitance of the entire field effect transistor. Improve the performance and reliability of field effect transistors.
  • an embodiment of the present application further provides a chip including the above-mentioned field effect transistor.
  • An electronic device is also provided, which includes a circuit board and a chip connected to the circuit board, the chip comprising any of the field effect transistors provided above.
  • the circuit board may be a printed circuit board (PCB), of course, the circuit board may also be a flexible circuit board (FPC) or the like, which is not limited in this embodiment.
  • the electronic device is different types of user equipment or terminal equipment such as a computer, a mobile phone, a tablet computer, a wearable device, and a vehicle-mounted device; the electronic device may also be a network device such as a base station.
  • the electronic device further includes a packaging substrate, the packaging substrate is fixed on the printed circuit board PCB by solder balls, and the chip is fixed on the packaging substrate by solder balls.
  • a non-transitory computer-readable storage medium for use with a computer having software for creating an integrated circuit, the computer-readable storage medium having stored thereon one or more A computer readable data structure, one or more computer readable data structures having photomask data for fabricating the field effect transistor provided by any one of the illustrations provided above.

Abstract

本申请的实施例提供一种场效应晶体管及其制造方法，涉及半导体技术领域，能够降低栅极与源极、漏极间的寄生电容。制作方法，包括：在半导体衬底上形成支撑结构，支撑结构包括交替设置的第一半导体材料层和第二半导体材料层，支撑结构的两侧设置有隔离层；沿着隔离层与支撑结构的交界形成覆盖支撑结构的假栅结构，假栅结构在栅长方向的长度小于第一半导体材料层在所述栅长方向的长度，栅长方向用于指示场效应晶体管中载流子的输运方向；沿栅长方向，在假栅结构的两侧沉积第一绝缘层；沿所述栅长方向，去除第二半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，绝缘凹槽的内部镂空、填充有空气。

Description

场效应晶体管及其制造方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种场效应晶体管及其制造方法。
背景技术
目前，随着MOSFET(metal-oxide-semiconductor field-effect transistor，金属-氧化物半导体场效应晶体管)器件的尺寸特征不断减小，FinFET(鳍式场效应晶体管)逐渐到达极限，环绕栅极器件(gate-all-around，GAA)等新型器件将被广泛采用。目前纳米线(nanowire)或纳米带(nanosheet)是最可能被大规模量产采用的技术。在FET的制作工艺中，相比于FinFET工艺，GAA的沟道被栅完全包围，需要有牺牲层来完成沟道的释放。
以MOSFET为例，如图1所示，一般依次堆叠第一半导体材料层11和第二半导体材料层12，以及位于第一半导体材料层11上的假栅结构13形成支撑结构100，在支撑结构100两侧的源漏区域通过掺杂工艺或外延工艺形成源极14和漏极15之后，可通过刻蚀工艺去除第一半导体材料层11以及假栅结构13，进而，如图2所示，可通过RMG(replacement metal gate，替代栅)工艺，在第一半导体材料层11和假栅结构13的位置填充栅极材料，例如，高介电常数金属栅(high-k metal gate)(高k材料以及金属材料(如TiN))，形成真正的栅极21。
在上述制作方法中，而为了保证牺牲层(第一半导体材料层11)释放后，栅极21与源极14(漏极15)是隔离的，需要提前在栅极21和源极14(或漏极15)之间增加内部隔离层(inner spacer)22。内部隔离层22能够控制GAA的栅极长度，实现栅极21与源极14(或漏极15)的隔离，与减小寄生电容的作用，是GAA工艺中极其重要的一环。但是内部隔离层22的材料通常存在一定的介电常数，从而在栅极21与源极14(或漏极15)引入了额外的寄生电容。
发明内容
本申请提供一种场效应晶体管及其制造方法，能够降低栅极与源极、漏极间的寄生电容。
第一方面，提供一种场效应晶体管的制作方法。该方法包括如下步骤：在半导体衬底上形成支撑结构，所述支撑结构包括交替设置的第一半导体材料层和第二半导体材料层，所述支撑结构的两侧设置有隔离层；沿着所述隔离层与所述支撑结构的交界形成覆盖所述支撑结构的假栅结构，所述假栅结构在栅长方向的长度小于所述第一半导体材料层在所述栅长方向的长度，所述栅长方向用于指示所述场效应晶体管中载流子的输运方向；沿栅长方向，在所述假栅结构的两侧沉积第一绝缘层；沿所述栅长方向，去除所述第二半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，所述绝缘凹槽的内部镂空、填充有空气，所述牺牲层为所述第二半导体材料层中处于所述假栅结构沿目标方向的投影区域中的部分，所述目标方向为垂直于所述半导体衬底底面的方向；沿所述栅长方向，在源漏区域形成源极和漏极，所述源极和漏极通过所述绝缘凹槽与所述牺牲层隔离；去除所述假栅结构和所述牺牲层；在已去除的假栅结构和牺牲层 的位置形成栅极。在该制作方法中，首先在半导体衬底上形成支撑结构，支撑结构包括交替设置的第一半导体材料层和第二半导体材料层，支撑结构的两侧设置有隔离层；沿着隔离层与支撑结构的交界形成覆盖支撑结构的假栅结构，假栅结构在栅长方向的长度小于第一半导体材料层在栅长方向的长度，栅长方向用于指示场效应晶体管中载流子的输运方向；沿栅长方向，在假栅结构的两侧沉积第一绝缘层；沿栅长方向，去除第二半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，绝缘凹槽的内部镂空、填充有空气，牺牲层为第二半导体材料层中处于假栅结构沿目标方向的投影区域中的部分，目标方向为垂直于半导体衬底底面的方向；沿栅长方向，在源漏区域形成源极和漏极，源极和漏极通过绝缘凹槽与牺牲层隔离；去除假栅结构和牺牲层；在已去除的假栅结构和牺牲层的位置形成栅极。由于栅极与源极或漏极之间设置了内部镂空的绝缘凹槽，并且绝缘凹槽中填充为空气，即通过空气隔离，可以降低栅极与源极、漏极间的寄生电容，从而降低了整个场效应晶体管的寄生电容，提高场效应晶体管的性能和可靠性。
在一种可能的实施方案中，沿所述栅长方向，去除所述第一半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，包括：沿所述栅长方向，对所述第二半导体材料层进行选择性氧化工艺，使得所述第一半导体材料层中除所述牺牲层以外的区域被氧化，形成绝缘隔离墙，其中，绝缘隔离墙的介质材料为所述第二半导体材料层的氧化物；在已去除的假栅结构和牺牲层的位置形成栅极后，去除所述第一绝缘层；将绝缘隔离墙去除，形成内部镂空的、填充有空气的所述绝缘凹槽。该可能的实施方式中对第二半导体材料层进行选择性氧化(selectively oxidization)工艺，使得第二半导体材料层中，处于假栅结构沿目标方向的投影区域以外的部分被氧化，被氧化的这部分空间形成了绝缘隔离墙，而第二半导体材料层中处于假栅结构沿目标方向的投影区域的部分没有被氧化，形成牺牲层。此时，绝缘隔离墙的介质材料为第二半导体材料层的氧化物(例如，氧化硅)，而绝缘隔离墙在后续步骤形成栅极后被去除，形成镂空的、填充有空气的绝缘凹槽。该内部镂空的、填充有空气的绝缘凹槽可以隔离后续形成的源极(或漏极)与填充牺牲层的栅极材料，例如，High-K(高介电常数)介质材料与栅极金属材料，由于空气的介电常数较低(空气的介电常数约为1)，可以降低后续形成的源极(或漏极)与栅极之间的寄生电容。其中在该步骤中形成绝缘隔离墙的原因是，避免直接在该步骤形成镂空的、填充有空气的绝缘凹槽在后续的步骤中被其他沉积的材料填满。另外,可以在后续步骤中替换牺牲层时，对刻蚀液进行阻挡避免刻蚀到牺牲层以外的区域。
在一种可能的实施方式中，沿所述栅长方向，去除所述第一半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，包括：沿所述栅长方向，对所述第二半导体材料层进行选择性刻蚀，使得所述第二半导体材料层中除所述牺牲层以外的区域被去除，形成所述绝缘凹槽；在所述绝缘凹槽中填充介质材料，形成绝缘隔离墙；在已去除的假栅结构和牺牲层的位置形成栅极后，去除所述第一绝缘层；将绝缘隔离墙去除，形成内部镂空的、填充有空气的所述绝缘凹槽。该可能的实施方式中，沿栅长方向，可以对第二半导体材料层进行选择性刻蚀(selectively removal)工艺，使得第二半导体材料层中处于假栅结构沿目标方向的投影区域以外的部分被去除，形成绝缘凹槽，而第二半导体材料层中处于假栅结构沿目标方向的投影区域的部分被保留，形成牺牲层。在绝缘凹槽中填充介质材料，形成绝缘隔离墙，例如填充氧化物或氮化物(具体可以是氧化硅或氮 化硅)；绝缘隔离墙在后续步骤形成栅极后被去除，形成内部镂空的、填充有空气的绝缘凹槽。该内部镂空的、填充有空气的绝缘凹槽可以隔离后续形成的源极(或漏极)与填充牺牲层的栅极材料，例如，High-K(高介电常数)介质材料与栅极金属材料，由于空气的介电常数较低(空气的介电常数约为1)，可以降低后续形成的源极(或漏极)与栅极材料产生的寄生电容。其中在该步骤中对绝缘凹槽以介质材料填充形成绝缘隔离墙的原因是，避免内部镂空的、填充有空气的绝缘凹槽在后续的步骤中被其他沉积材料填满。另外可以避免后续步骤中替换牺牲层时，对刻蚀液进行阻挡避免刻蚀到牺牲层以外的区域。
在一种可能的实施方式中，将绝缘隔离墙去除后，还包括：在所述栅极的外围沉积第二绝缘层，所述第二绝缘层的侧壁与所述隔离层的侧壁齐平；在栅结构截面方向，所述绝缘凹槽的两端被第二绝缘层封堵。在该可能的实施方式中，可以避免后续制程工艺中的材料再次将绝缘凹槽填满。其中，当用作制作纳米片器件(nanosheet器件)时，由于沟道的宽度大于支撑结构中材料层的间距，因此，通常选用流动性较小的材料沉积第二绝缘层，借助第二绝缘层的阻挡作用，绝缘凹槽的镂空部分形成封闭的空间，避免第二绝缘层的材料进入将绝缘凹槽。
在一种可能的实施方式中，沿所述栅长方向，在源漏区域形成源极和漏极之前，还包括：在所述绝缘凹槽的内表面上形成阻挡层。该可能的实施方式中，可以通过ALD(Atomic Layer Deposition，原子层沉积)或CVD工艺在绝缘凹槽的内表面上形成阻挡层。这样，后续在去除牺牲层时，阻挡层可以阻挡刻蚀液刻蚀到除牺牲层以外的区域。其中，绝缘凹槽中，阻挡层包围的区域为空气。空气是一种介电常数较低的介质，可以隔离后续形成的源极(或漏极)与填充牺牲层的栅极材料，从而降低后续形成的源极(或漏极)直接与栅极材料之间产生的寄生电容。
在一种可能的实施方式中，在半导体衬底上形成支撑结构，包括：在半导体衬底上交替生长第一半导体材料层和第二半导体材料层的周期性超晶格结构，所述第一半导体材料层和所述第二半导体材料层的厚度均小于50nm；对所述超晶格结构进行刻蚀，形成鳍状的所述支撑结构。
在一种可能的实施方式中，沿着所述隔离层与所述支撑结构的交界形成覆盖所述支撑结构的假栅结构，包括：在裸露出的支撑结构上形成氧化层；在所述氧化层上形成覆盖所述支撑结构的假栅结构。
第二方面，提供一种场效应晶体管，包括源极和漏极，所述源极与所述漏极之间形成有由沟道包括沟道与栅极交叠堆叠的堆叠结构，所述栅极与所述源极、漏极之间形成有内部镂空、填充有空气的绝缘凹槽。其中沟道中为半导体材料层，半导体材料层材料层在所述沟道的一端与所述源极接触，所述半导体材料层在所述沟道的另一端与所述漏极接触；相邻的两层半导体层之间，在所述栅极与所述源极或漏极之间形成有内部镂空、填充有空气的绝缘凹槽。
在一种可能的实施方式中，所述绝缘凹槽的内表面形成有阻挡层，所述绝缘凹槽的开口朝向所述源极或所述漏极。
在一种可能的实施方式中，所述绝缘凹槽的两端设置有第二绝缘层，所述第二绝缘层将所述绝缘凹槽封堵。
第三方面，提供一种芯片，包括上述的场效应晶体管。
第四方面，提供一种电子设备，包括电路板、以及与所述电路板连接的芯片，所述芯片上设置于如上述的场效应晶体管。
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图1为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图；
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图3为本申请另一实施例提供的一种场效应晶体管的结构示意图；
图4为本申请实施例提供的一种场效应晶体管的制作方法流程示意图；
图5为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图一；
图6为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图二；
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图8为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图四；
图9为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图五；
图10为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图六；
图11为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图七；
图12为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图八；
图13为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图九；
图14为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图十；
图15为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图十一；
图16为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图十二；
图17为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图十三；
图18为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图十四；
图19为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图十五；
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图24为本申请实施例提供的一种场效应晶体管的制作过程中的结构示意图二十。
具体实施方式
下文将详细论述各实施例的制作和使用。但应了解，本申请提供的许多适用发明概念可实施在多种具体环境中。所论述的具体实施例仅仅说明用以实施和使用本说明和本技术的具体方式，而不限制本申请的范围。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。
各电路或其它组件可描述为或称为“用于”执行一项或多项任务。在这种情况下，“用于”用来通过指示电路/组件包括在操作期间执行一项或多项任务的结构(例如电路系统)来暗指结构。因此，即使当指定的电路/组件当前不可操作(例如未打开)时，该电路/组件也可以称为用于执行该任务。与“用于”措辞一起使用的电路/组件包括硬件，例如执行操作的电路等。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在 本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请的实施例提供一种场效应晶体管，该场效应晶体管可以为MOSFET，例如，堆叠环栅纳米线晶体管(stacked gate-all-around nanowire transistor)，鳍式场效应晶体管(fin field-effect transistor，FinFET)等，也可以为隧穿场效应晶体管(tunneling field effect transistor，TFET)等，本申请实施例对此不作限制。此外本申请的实施例可应用于纳米线(nanowire)或纳米片(nanosheet)产品。
另外，为方便阐述本申请的实施例提供一种场效应晶体管及其制作方法，首先对场效应晶体管的各个截面方向进行解释，如图3所示，为本申请的实施例提供的一种场效应晶体管的结构示意图，其中，半导体衬底31上设置有栅极32，栅极32的两侧为源漏区域，分别设置有鳍状的源极33和漏极34，那么，沿XX’方向用于指示场效应晶体管的栅长方向，即场效应晶体管中载流子的输运方向；沿YY’方向用于指示场效应晶体管的栅结构(gate structure)截面方向，栅长方向与栅结构截面方向互相垂直。需要说明的是，图3中仅示出了场效应晶体管内一组栅极32，源极33和漏极34的结构，可以理解的是，场效应晶体管内还可以包括多组结构类似的栅极，源极和漏极，本申请实施例对此不作限制。
那么，基于图3所示的栅长方向和栅结构截面方向，本申请的实施例提供一种场效应晶体管的制作方法，如图4所示，包括：
401、在半导体衬底上形成支撑结构，该支撑结构包括交替设置的第一半导体材料层和第二半导体材料层，支撑结构的两侧设置有隔离层。
其中，该半导体衬底可以为体硅(bulk silicon)、SOI(silicon-on-insulator，绝缘衬底上的硅)衬底、ETSOI(extremely thin SOI，超薄SOI)衬底、SGOI(siGe-on-insulator，绝缘衬底上的锗硅)衬底或IIIV-OI(IIIV-on-insulator，绝缘衬底上的IIIV族化合物)衬底等，本申请实施例对此不作限制。
具体的，如图5、图6所示(图5中为沿栅长方向的截面示意图，图6为沿栅结构截面方向的截面示意图)，可以先在半导体衬底51上交替生长第一半导体材料层52和第二半导体材料层53的周期性超晶格(superlattice)结构，其中，超晶格结构是指两种不同组元以几个纳米到几十个纳米的薄层交替生长并保持严格周期性的多层膜。示例性的，第一半导体材料层52和第二半导体材料层53的厚度均可小于50nm，当第 一半导体材料层52为硅材料时，第二半导体材料层53可以为锗硅材料。进而，可以对上述第一半导体材料层52和第二半导体材料层53组成的超晶格结构进行刻蚀，形成如图7、图8所示的支撑结构61，示例性的，该支撑结构61可以呈鳍状设置在半导体衬底51上。其中，图7中的为沿栅长方向的截面示意图，图8为沿栅结构截面方向的截面示意图。
进一步地，如图9所示，为了实现半导体衬底上方的功能结构对硅的隔离，可以在上述衬底上形成浅槽隔离(shallow trench isolation，STI)，例如可继续通过CMP(chemical mechanical flattening，化学机械平坦化)工艺和回刻(Recess)工艺在支撑结构61的两侧形成隔离层71。可选的，隔离层71的厚度与刻蚀掉的半导体衬底51的厚度相同。隔离层71具体可以为氧化硅等氧化物或氮化硅等氮化物制成的，本申请实施例对此不作限制。
402、沿着隔离层与支撑结构的交界形成覆盖支撑结构的假栅结构，该假栅结构在栅长方向的长度小于第一半导体材料层在栅长方向的长度。
如图10所示，在形成隔离层71后，可进一步在隔离层71上形成覆盖支撑结构61的假栅(poly gate)结构81，此时，支撑结构61被镶嵌在隔离层71与假栅结构81形成的间隙中。其中，如图10所示，该假栅结构81在栅长方向的长度小于第一半导体材料层52在栅长方向的长度。示例性的，假栅结构81具体可以为多晶硅或者非晶硅材料制成的，本申请实施例对此不作限制。
具体的，可以先在裸露出的支撑结构61上形成氧化层(dummy oxide)，例如氧化硅；再在氧化层上刻蚀形成覆盖支撑结构61的假栅结构81。
403、沿栅长方向，在假栅结构的两侧沉积第一绝缘层。
如图11所示，还可以在假栅结构81的外围沉积第一绝缘层91，第一绝缘层91的侧壁在栅结构截面方向上与隔离层71的侧壁对齐。第一绝缘层91可以采用氮化硅或氧化硅。另外，在形成假栅结构81时，尽可能的保证刻蚀的各向异性，并调节使多晶硅:氧化硅的刻蚀选择比例尽可能的高，从而形成形貌较为陡直的假栅结构81，形貌较为陡直的假栅结构81有利于后续形成第一绝缘层91时，能够较好地使得假栅结构81与第一绝缘层91贴合。
404、沿栅长方向，去除第二半导体材料层中除牺牲层以外的区域，形成绝缘凹槽。
上述牺牲层为第二半导体材料层53中处于假栅结构81沿目标方向(该目标方向为垂直于半导体衬底51底面的方向，即假栅结构81在第二半导体材料层53的正投影方向)的投影区域中的部分。在一种可能的设计方式中，在栅长方向上，可以先沿第一绝缘层91的侧壁对第一半导体材料层52和第二半导体材料层53进行刻蚀，使第一半导体材料层52和第二半导体材料层53的侧壁与第一绝缘层91对齐(如图11、图12所示)。其中制作绝缘凹槽镂空结构的方式主要有以下三种：
方式一：对图12中的中所示的第二半导体材料层53进行选择性氧化(selectively oxidization)工艺，使得第二半导体材料层53中，处于假栅结构81沿目标方向的投影区域以外的部分被氧化，被氧化的这部分空间形成了如图13所示的绝缘隔离墙103，而第二半导体材料层53中，处于假栅结构81沿目标方向的投影区域的部分没有被氧化，形成如图13所示的牺牲层102。此时，绝缘隔离墙103的介质材料为第二半导体材料层53的氧化物(例如，氧化硅)填充，而绝缘隔离墙103在后续步骤形成栅极后被去除，形成内部镂空的、 填充有空气的绝缘凹槽101(如图23所示)。该内部镂空的、填充有空气的绝缘凹槽101可以隔离后续形成的源极(或漏极)与填充牺牲层102的栅极材料，例如，High-K(高介电常数)介质材料与栅极金属材料，由于空气的介电常数较低(空气的介电常数约为1)，可以降低后续形成的源极(或漏极)与栅极之间的寄生电容。其中在该步骤中形成绝缘隔离墙103的原因是，避免直接在该步骤形成镂空的、填充有空气的绝缘凹槽101在后续的步骤中被其他沉积的材料填满。另外,可以在后续步骤中替换牺牲层102时，对刻蚀液进行阻挡避免刻蚀到牺牲层102以外的区域。
方式二：在另一种可能的设计方式中，沿栅长方向，可以对图12中所示的第二半导体材料层53进行选择性刻蚀(selectively removal)工艺，使得第二半导体材料层53中处于假栅结构81沿目标方向的投影区域以外的部分被去除，形成如图14所示的绝缘凹槽101，而第二半导体材料层53中处于假栅结构81沿目标方向的投影区域的部分被保留，形成如图14所示的牺牲层102。如图15所示，在绝缘凹槽101中填充介质材料，形成绝缘隔离墙103，例如介质材料为氧化物或氮化物(具体可以是氧化硅或氮化硅)；绝缘隔离墙103在后续步骤形成栅极后被去除，形成填充有空气的、内部镂空的绝缘凹槽101。该填充有空气的、内部镂空的绝缘凹槽101可以隔离后续形成的源极(或漏极)与填充牺牲层102的栅极材料，例如，High-K(高介电常数)介质材料与栅极金属材料，由于空气的介电常数较低(空气的介电常数约为1)，可以降低后续形成的源极(或漏极)与栅极材料产生的寄生电容。其中在该步骤中对绝缘凹槽101以介质材料填充形成绝缘隔离墙103的原因是，避免内部镂空的、填充有空气的绝缘凹槽101在后续的步骤中被其他沉积材料填满。另外可以避免后续步骤中替换牺牲层102时，对刻蚀液进行阻挡避免刻蚀到牺牲层102以外的区域。
方式三：在另一种可能的设计方式中，沿栅长方向，可以对图12中所示的第二半导体材料层53进行选择性刻蚀(selectively removal)工艺，使得第二半导体材料层53中，假栅结构81在第二半导体材料层53的投影区域以外的区域被去除，形成如图14所示的绝缘凹槽101，而假栅结构81在第二半导体材料层53的投影区域被保留，形成如图14所示的牺牲层102。可以通过ALD(Atomic Layer Deposition，原子层沉积)或CVD工艺在绝缘凹槽101的内表面上形成阻挡层111，如图16所示。这样，后续在去除牺牲层102时，阻挡层111可以阻挡刻蚀液刻蚀到除牺牲层102以外的区域。其中，绝缘凹槽101中，阻挡层111包围的区域为空气。空气是一种介电常数较低的介质，可以隔离后续形成的源极(或漏极)与填充牺牲层102的栅极材料，从而降低后续形成的源极(或漏极)直接与栅极材料之间产生的寄生电容。
405、沿栅长方向，在源漏区域形成源极和漏极，源极和漏极通过绝缘凹槽与牺牲层隔离。
在步骤405中，可利用选择性外延技术，在源漏区域外延生长硅或锗硅等材料，进而，通过掺杂工艺使源漏区域具有一定的掺杂浓度，形成图17或图18所示源极171和漏极172。其中，采用上述方式一或方式二形成绝缘凹槽101时，该步骤中绝缘凹槽101内填充介质材料，如氧化物，如图17所示。其中采用上述方式三形成绝缘凹槽101时，该步骤中绝缘凹槽101的表层上形成阻挡层111，如图18所示。由于采用选择性外延，源极和漏极的材料会以第一半导体材料层52在栅长方向上的侧壁开始外延生成，这样能够保证阻挡层111包围的凹槽充满空气而不会被其他材料填满。
406、去除假栅结构和牺牲层。
如图19和图20所示，可通过刻蚀工艺去除上述假栅结构81和牺牲层102；其中图19是对应方式一和方式二制作绝缘凹槽101时，形成的结构。图19是对应方式三制作绝缘凹槽101时，形成的结构。
407、在已去除的假栅结构和牺牲层的位置形成栅极。
后续，通过RMG(replacement metal gate，替代栅)工艺，在已去除的假栅结构81和牺牲层102的位置形成如图21和图22所示的栅极211(该栅极211中至少包括两层结构，一层是High-K介质材料，另外一层是具有特定功函数的金属材料，例如可以是TiN)，形成场效应晶体管。其中图21是对应方式一和方式二制作绝缘凹槽101时，形成的结构。图22是对应方式三制作绝缘凹槽101时，形成的结构。当采用方式三形成绝缘凹槽101时，至步骤407形成场效应晶体管。而采用方式一或方式二形成绝缘凹槽101时，由于407步骤之后，绝缘凹槽101的位置为绝缘隔离墙103，即绝缘凹槽101中仍然填充有介质材料，例如氧化物或氮化物。因此其仍然会带来栅极与源极或漏极间的寄生电容。因此还需要包括如下步骤以去除绝缘凹槽中的介质材料。
408、去除第一绝缘层。
如图23所示，由于第一绝缘层91将绝缘隔离墙103封堵，因此为了对绝缘隔离墙103进行去除，还需要先将第一绝缘层91去除。
409、将绝缘隔离墙去除，形成内部镂空的、填充有空气的绝缘凹槽。
如图23所示，可以通过湿法刻蚀将绝缘隔离墙去除。
410、在栅极的外围沉积第二绝缘层，第二绝缘层的侧壁与隔离层的侧壁齐平；在栅结构截面方向，绝缘凹槽的两端被第二绝缘层封堵。
如图24所示，最终为了避免后续制程工艺中的材料再次将绝缘凹槽101填满，在该步骤中可以通过在栅极的外围沉积第二绝缘层92，第二绝缘层92的侧壁与隔离层71的侧壁齐平；在栅结构截面方向，绝缘凹槽101的两端被第二绝缘层92封堵。其中，当用作制作纳米片器件(nanosheet器件)时，由于沟道100的宽度大于支撑结构中材料层的间距，因此，通常选用流动性较小的材料沉积第二绝缘层92，一方面借助第二绝缘层92的阻挡作用，绝缘凹槽101的镂空部分形成封闭的空间，另一方面可以避免第二绝缘层92的材料进入将绝缘凹槽101。
如图22或图24所示，在形成的场效应晶体管中，由于栅极211与源极171或漏极172之间设置了内部镂空的、填充有空气的绝缘凹槽101，即通过空气隔离，可以降低栅极与源极、漏极间的寄生电容，从而降低了整个场效应晶体管的寄生电容，提高场效应晶体管的性能和可靠性。
另外，本申请实施例还提供一种场效应晶体管，该场效应晶体管可以为MOSFET或隧穿场效应晶体管等，本申请实施例对此不作限制。其中，本申请实施例还提供的场效应晶体管的制作方法可参见上述实施例中步骤401-410的相关内容，故此处不再赘述。
示例性的，如图24所示，采用上述方式一或方式二制作绝缘凹槽时，在本申请实施例提供的场效应晶体管中，包括源极171和漏极172，源极171与漏极172之间形成有由沟道(沟道中为半导体材料层、即第一半导体材料层52)与栅极211交叠堆叠的堆叠结构，栅极211与源极171、漏极172之间形成有内部镂空、填充有空气的绝缘凹 槽101。
在另一种方案中，如图22所示，绝缘凹槽101的内表面形成有阻挡层111，绝缘凹槽101的开口朝向源极171或漏极172。此外，如图24所示，绝缘凹槽101的两端设置有第二绝缘层92，第二绝缘层92将绝缘凹槽101封堵。
至此，本申请的实施例提供一种场效应晶体管及其制作方法，在该制作方法中，首先在半导体衬底上形成支撑结构，支撑结构包括交替设置的第一半导体材料层和第二半导体材料层，支撑结构的两侧设置有隔离层；沿着隔离层与支撑结构的交界形成覆盖支撑结构的假栅结构，假栅结构在栅长方向的长度小于第一半导体材料层在栅长方向的长度，栅长方向用于指示场效应晶体管中载流子的输运方向；沿栅长方向，在假栅结构的两侧沉积第一绝缘层；沿栅长方向，去除第二半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，绝缘凹槽内部镂空，牺牲层为第二半导体材料层中处于假栅结构沿目标方向的投影区域的部分，目标方向为垂直于半导体衬底底面的方向；沿栅长方向，在源漏区域形成源极和漏极，源极和漏极通过绝缘凹槽与牺牲层隔离；去除假栅结构和牺牲层；在已去除的假栅结构和牺牲层的位置形成栅极。由于栅极与源极或漏极之间设置了镂空的绝缘凹槽，即通过空气隔离，可以降低栅极与源极、漏极间的寄生电容，从而降低了整个场效应晶体管的寄生电容，提高场效应晶体管的性能和可靠性。
基于此，本申请实施例还提供一种包括上述的场效应晶体管的芯片。还提供一种电子设备，该电子设备包括电路板、以及与电路板连接的芯片，该芯片包含上文所提供的任一种场效应晶体管。其中，该电路板可以为印制电路板(printed circuit board，PCB)，当然电路板还可以为柔性电路板(FPC)等，本实施例对电路板不作限制。可选的，该电子设备为计算机、手机、平板电脑、可穿戴设备和车载设备等不同类型的用户设备或者终端设备；该电子设备还可以为基站等网络设备。可选的，该电子设备还包括封装基板，该封装基板通过焊球固定于印刷电路板PCB上，该芯片通过焊球固定于封装基板上。需要说明的是，关于电子设备中存储器的相关描述，具体可以参见上述实施例关于存储器的描述，本申请实施例在此不再赘述。
在本申请的另一方面，还提供一种与计算机一起使用的非瞬时性计算机可读存储介质，该计算机具有用于创建集成电路的软件，该计算机可读存储介质上存储有一个或多个计算机可读数据结构，一个或多个计算机可读数据结构具有用于制造上文所提供的任意一个图示所提供的场效应晶体管的光掩膜数据。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种场效应晶体管的制作方法，其特征在于，包括：
    在半导体衬底上形成支撑结构，所述支撑结构包括交替设置的第一半导体材料层和第二半导体材料层，所述支撑结构的两侧设置有隔离层；
    沿着所述隔离层与所述支撑结构的交界形成覆盖所述支撑结构的假栅结构，所述假栅结构在栅长方向的长度小于所述第一半导体材料层在所述栅长方向的长度，所述栅长方向用于指示所述场效应晶体管中载流子的输运方向；
    沿栅长方向，在所述假栅结构的两侧沉积第一绝缘层；
    沿所述栅长方向，去除所述第二半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，所述绝缘凹槽的内部镂空、填充有空气，所述牺牲层为所述第二半导体材料层中处于所述假栅结构沿目标方向的投影区域中的部分，所述目标方向为垂直于所述半导体衬底底面的方向；
    沿所述栅长方向，在源漏区域形成源极和漏极，所述源极和漏极通过所述绝缘凹槽与所述牺牲层隔离；
    去除所述假栅结构和所述牺牲层；
    在已去除的假栅结构和牺牲层的位置形成栅极。
  2. 根据权利要求1所述的场效应晶体管的制作方法，其特征在于，沿所述栅长方向，去除所述第一半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，包括：
    沿所述栅长方向，对所述第二半导体材料层进行选择性氧化工艺，使得所述第一半导体材料层中除所述牺牲层以外的区域被氧化，形成绝缘隔离墙，其中，所述绝缘隔离墙的介质材料为所述第二半导体材料层的氧化物；
    在已去除的假栅结构和牺牲层的位置形成栅极后，去除所述第一绝缘层；
    将所述绝缘隔离墙去除，形成内部镂空的、填充有空气的所述绝缘凹槽。
  3. 根据权利要求1所述的场效应晶体管的制作方法，其特征在于，沿所述栅长方向，去除所述第一半导体材料层中除牺牲层以外的区域，形成绝缘凹槽，包括：
    沿所述栅长方向，对所述第二半导体材料层进行选择性刻蚀，使得所述第二半导体材料层中除所述牺牲层以外的区域被去除，形成所述绝缘凹槽；
    在所述绝缘凹槽中填充介质材料，形成绝缘隔离墙；
    在已去除的假栅结构和牺牲层的位置形成栅极后，去除所述第一绝缘层；
    将所述绝缘隔离墙去除，形成内部镂空的、填充有空气的所述绝缘凹槽。
  4. 根据权利要求2或3所述的场效应晶体管的制作方法，其特征在于，将所述绝缘隔离墙去除后，还包括：
    在所述栅极的外围沉积第二绝缘层，所述第二绝缘层的侧壁与所述隔离层的侧壁齐平；在栅结构截面方向，所述绝缘凹槽的两端被第二绝缘层封堵。
  5. 根据权利要求1所述的场效应晶体管的制作方法，其特征在于，沿所述栅长方向，在源漏区域形成源极和漏极之前，还包括：
    在所述绝缘凹槽的内表面上形成阻挡层。
  6. 根据权利要求1-5任一项所述的场效应晶体管的制作方法，其特征在于，在半导体衬底上形成支撑结构，包括：
    在半导体衬底上交替生长第一半导体材料层和第二半导体材料层的周期性超晶格结构，所述第一半导体材料层和所述第二半导体材料层的厚度均小于50nm；
    对所述超晶格结构进行刻蚀，形成鳍状的所述支撑结构。
  7. 根据权利要求1-5任一项所述的场效应晶体管的制作方法，其特征在于，沿着所述隔离层与所述支撑结构的交界形成覆盖所述支撑结构的假栅结构，包括：
    在裸露出的支撑结构上形成氧化层；
    在所述氧化层上形成覆盖所述支撑结构的假栅结构。
  8. 一种场效应晶体管，其特征在于，包括源极和漏极，所述源极与所述漏极之间形成有由沟道与栅极交替堆叠的堆叠结构；
    所述栅极与所述源极、漏极之间形成有内部镂空、填充有空气的绝缘凹槽。
  9. 根据权利要求8所述的场效应晶体管，其特征在于，所述绝缘凹槽的内表面形成有阻挡层，所述绝缘凹槽的开口朝向所述源极或所述漏极。
  10. 根据权利要求8或9所述的场效应晶体管，其特征在于，所述绝缘凹槽的两端设置有第二绝缘层，所述第二绝缘层将所述绝缘凹槽封堵。
  11. 一种芯片，其特征在于，包括如权利要求8-10任一项所述的场效应晶体管。
  12. 一种电子设备，其特征在于，包括电路板、以及与所述电路板连接的芯片，所述芯片上设置于如权利要求8-10任一项所述的场效应晶体管。
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