TW202017011A - 奈米線裝置的形成方法 - Google Patents

奈米線裝置的形成方法 Download PDF

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TW202017011A
TW202017011A TW108121712A TW108121712A TW202017011A TW 202017011 A TW202017011 A TW 202017011A TW 108121712 A TW108121712 A TW 108121712A TW 108121712 A TW108121712 A TW 108121712A TW 202017011 A TW202017011 A TW 202017011A
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坎達巴拉 Ｎ 泰伯利
傑佛瑞 史密斯
赫里特 Ｊ 盧森克
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日商東京威力科創股份有限公司
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Abstract

一種奈米線裝置的形成方法包含：提供一基板，其包含在垂直隔片間的奈米線；相對於該垂直隔片在該奈米線上選擇性沉積一高k膜；以及相對於該垂直隔片在該高k膜上選擇性沉積一含金屬閘電極層。該方法可更包含在選擇性沉積該高k膜之前在該垂直隔板上選擇性沉積一介電材料，其中該介電材料具有低於該高k膜之介電常數。

Description

奈米線裝置的形成方法
相關申請案的交互參照：本申請案主張以下優先權：於2018年6月22日提交之美國臨時專利申請案第62/688,906號，發明名稱為「Method for Forming an Advanced Gate Stack for 3D Integration」；其所揭露之全部內容通過引用明確於此納入。本申請案主張以下優先權：於2018年6月26日提交之美國臨時專利申請案第62/690,331號，發明名稱為「Method for Forming an Advanced Gate Stack for 3D Integration」；其所揭露之全部內容通過引用明確於此納入。
本發明與半導體製造及半導體裝置之領域相關，且更特別是與用於積體電路之奈米線裝置的形成方法相關。
半導體產業仰賴於縮減/降低裝置特徵部尺寸以提高效能及增加裝置密度。由於微縮所致持續的裝置效能進步已引進了獨特技術，諸如：半導體-絕緣體（semiconductor on insulator）（例如矽-絕緣體（SOI）及鍺-絕緣體（GeOI））的、應力源（諸如SiGe 、SiC），以改善在90奈米節點的遷移率，45奈米節點的源極和汲極（凸起的源極和汲極）之外延再成長、高k金屬閘極（HKMG），以及在22奈米節點諸如鰭式場效電晶體及三閘極的3D結構。
然而，在14奈米以下技術節點維持裝置效能及良好的短通道控制相當有挑戰性。需要新材料（例如III-V族半導體、Ge、SiGe、石磨烯、MoS2 、WS2 、MoSe2 、及WS2 ）以及新整合方案（例如奈米線）。奈米線裝置提供特徵部尺寸微縮、良好的短通道控制、以及增強的裝置遷移率，因而增強裝置速率。
一種奈米線裝置的形成方法。該方法包含：提供一基板，其包含在垂直隔片間的奈米線；相對於該垂直隔片在該奈米線上選擇性沉積一高k膜；以及相對於該垂直隔片在該高k膜上選擇性沉積一含金屬閘電極層。該方法可更包含在選擇性沉積該高k膜之前在該垂直隔板上選擇性沉積一介電材料，其中該介電材料具有低於該高k膜之介電常數。
圖1A-1J透過剖面圖示意地顯示根據本發明實施例之部分製造的奈米線裝置的形成。圖1A及1B示意地顯示形成於基板100上 之簡化的奈米線結構10/11的剖面圖，其中奈米線結構10/11包含垂直隔片104/106、以及在垂直隔片104/106之間垂直堆疊的奈米線102/103。根據另一實施例，奈米線102/103可在相同的垂直平面。舉例而言，基板100可為200毫米Si晶圓、300毫米Si晶圓、或更大的Si晶圓。垂直隔片104可包含具有小於約4之介電常數（k）的介電材料，例如具有在約2.8及3.5之間的介電常數（k）的SiCOH材料。在另一範例中，垂直隔片104可包含氣隙隔片。在一範例中，垂直隔片106可包含SiO2 材料。在奈米結構10/11中僅顯示三條奈米線102/103，然而本發明之實施例可包含任何數量的奈米線。
奈米線102可包含外延Si材料且奈米線結構10可在基板100上形成N型金氧半導體（NMOS）裝置。再者，奈米線103可包含外延SiGe材料且奈米線結構11可在基板100上形成P型金氧半導體（PMOS）裝置。在另一範例中，奈米線102/103可整合進形成NMOS裝置與PMOS裝置兩者的垂直偏移奈米線結構。部分製造的奈米線結構10/11可藉由移除在奈米線102/103上方的假性閘極（未示於圖中）以及移除在奈米線102/103之間的外延層而加以形成。此移除可使用在奈米線102/103之間形成開口140/141之選擇性等向性蝕刻來執行。
圖1C及1D顯示根據本發明之實施例的奈米結構10/11的選用性處理。該處理包含將奈米結構10/11暴露於等向性氧化電漿，其將奈米線102/103的表面氧化以在奈米線102/103上形成SiO2 層108/109。可使用含有氧及氫的製程氣體的微波電漿激發來執行對等向性氧化電漿的暴露步驟。在一範例中，製程氣體可含有O2 氣體及H2 氣體。微波電漿激發可由從日本赤坂的東京威力科創股份有限公司可取得的RLSATM 微波電漿系統所供應。替代地，可在氧化環境中使用高溫及高壓凝結熱處理來形成SiO2 層108/109。
此後，可從奈米線102/103移除SiO2 層108/109。這示意地顯示在圖1E及1F中。SiO2 層108/109的形成及後續的移除將缺陷從奈米線102/103的表面移除以及亦使奈米線102/103圓角化。再者，SiO2 層109的移除增加SiGe奈米線103外表面附近的Ge成分。可使用等向性蝕刻製程（例如：化學氧化物去除（COR）製程）來執行的SiO2 移除。舉例而言，COR製程可藉由連續或同時的HF氣體及NH3 氣體的暴露加以執行，接著熱處理，該熱處理將來自SiO2 與HF氣體及NH3 氣體反應的反應產物脫附。在一個範例中，COR製程可在Certas WING™中執行，其為從日本赤坂的東京威力科創股份有限公司可取得的高產量無氣體電漿之化學蝕刻系統。
在一個範例中，可將SiO2 的移除以及後續更進一步的處理整合進真空處理工具平台以避免奈米線結構10/11的再氧化。在另一範例中，可藉由將奈米線結構10/11浸沒於稀釋HF（DHF）浴中來執行的SiO2 移除，並接著快速將基板100放置在真空處理工具中以避免奈米線結構10/11的再氧化。
現在參考圖1G及1H，示意地顯示奈米線結構10/11的更進一步處理，其中將高k膜110/111選擇性沉積在奈米線102/103上。可藉由在垂直隔片104上阻擋沉積來執行選擇性高k沉積。在一個範例中，可使自組裝單層（SAM）選擇性吸附在垂直隔片104的表面上，且之後，由於在垂直隔片104上SAM的阻擋效應，高k膜110/111選擇性沉積在奈米線102/103上。
藉由使奈米線結構10/11處在包含能夠在基板上形成SAMs之分子的反應氣體，SAM可選擇性吸附在垂直隔片104上。SAM為分子組裝，其藉由吸附而自發性形成在基板表面上，且組織成或多或少的大型有序域。SAM可包含具有頭端基、尾端基、以及官能端基的分子，且SAM 係藉由在室溫或高於室溫下將頭端基從氣相化學吸附在基板上，接著緩慢組織尾端基而產生。起初，在表面上的小分子密度之下，被吸附分子形成無序的分子質量或形成有序的二維「下躺相」，且在較高的分子覆蓋率之下，在幾分鐘到幾小時的時間內，開始在基板表面上形成三維結晶或半晶質結構。頭端基在基板上組裝在一起，而尾端基則在遠離基板處組裝。
根據一實施例，形成SAM之分子的頭端基可包含：硫醇、矽烷、或磷酸酯。矽烷的例子包含分子，該分子含有C、H、Cl、F、以及Si原子，或C、H、Cl、及Si原子。該分子的非限制性例子包含全氟癸基三氯矽烷（CF3 (CF2 )7 CH2 CH2 SiCl3 ）、全氟癸硫醇（CF3 (CF2 )7 CH2 CH2 SH）、癸基二甲基氯矽烷（CH3 (CH2 )8 CH2 Si(CH3 )2 Cl）、以及叔丁基二甲基氯矽烷（(CH3 )3 CSi(CH3 )2 Cl) ）。矽烷的其他例子包含含有C、H、以及Si原子的烷基矽烷。
高k膜110/111可包含一或多個基於金屬的氧化物，例如：HfO2 、ZrO2 、TiO2 、Al2 O3 、或其組合。在某些例子中，高k膜110/111可以氣相沉積來沉積，例如化學氣相沉積（CVD）或原子層沉積（ALD）。高品質的高k膜可藉由氣相沉積來形成，其包含多個交替的沉積及退火步驟。在高k膜110/111的沉積（或是後續的退火）期間， Si 可從Si奈米線102擴散進入高k膜110而Ge可從SiGe奈米線擴散進入高k膜111。
在高k膜110/111的沉積之後，奈米線結構10/11可選用性暴露於等向性氧化電漿中，其在高k膜110/111與奈米線102/103的介面形成薄膜氧化介面層。可優化電漿處理條件以防對高k膜110/111的損害且僅形成氧化介面層而不氧化在奈米線結構10/11中的其他材料。根據一個實施例，可使用含有氧及氫的製程氣體的微波電漿激發來執行在等向性氧化電漿的暴露。在一個例子中，製程氣體可含有O2 氣體及H2 氣體。微波電漿激發可由從日本赤坂的東京威力科創股份有限公司可取得的RLSATM 微波電漿系統所供應。退火及等向性電漿暴露步驟將漏電流降低並將高k膜110/111的等效氧化物（EOT）減少。
根據一個實施例，可藉由在高k膜110上選擇性沉積第一含金屬閘電極膜112以及在高k膜111上選擇性沉積第二含金屬閘電極膜113來更進一步處理圖1G及1H中的基板100。在一個例子中，第一及第二含金屬閘電極膜112/113可完全填滿奈米線102/103之間的開口140/141的剩餘容積。這示意地顯示於圖1I及1J中。在一個範例中，用於含有Si奈米線102之NMOS裝置的第一含金屬閘電極膜112可包含TiSiN、TiAlC、富含Ti的TiN、W、WNx 、Mo、或Pt ，而用於含有SiGe奈米線103之PMOS裝置的第二含金屬閘電極膜113可包含TiN、TiON、Ru、W、WNx 、Mo、或Pt。富含Ti的TiN 可具有大於習知TiN材料的Ti含量。可使用包含遮罩層之使用的習知微影及蝕刻方法來執行選擇性沉積。再者，選擇性沉積可更包含使用如參考了圖1G及1H詳細描述之SAM，將在垂直隔片104上第一及第二含金屬閘電極膜112/113的沉積加以阻擋。
根據一個實施例，藉由在含金屬閘電極膜112/113的沉積之前在高k膜110/111上選擇性沉積介電閾電壓調整層，可更進一步處理圖1G及1H中的基板100。替代地，可在高k膜110/111之前沉積介電閾電壓調整層。介電閾電壓調整層可用於調整奈米線結構10/11的閾電壓（Vt ）。在一個範例中，介電閾電壓調整層可包含La2 O3 或Y2 O3 以用於含有SiGe奈米線103之PMOS裝置、以及Al2 O3 以用於含有Si奈米線102之NMOS裝置。再者，可將鐵電材料（例如HfYOx ，其中Y為Zr、Al、La、Y、或Si）添加至高k膜110/111以調制Vt 。在一個例子中，可藉由中斷高k膜110/111的沉積、沉積介電閾電壓調整層、且接著繼續高k膜110/111的沉積，以將介電閾電壓調整層與高k膜110/111混合。在其他範例中，藉由改變介電閾電壓調整層的厚度、將介電閾電壓調整層退火以促使進到高k膜110/111的擴散、或是上述兩者，可更進一步調制Vt 。可使用包含遮罩層之使用的習知微影及蝕刻方法來執行介電閾電壓調整層的選擇性沉積。再者，選擇性沉積可更包含使用如參考了圖1G及1H詳細描述之SAM，將在垂直隔片104上介電閾電壓調整層的沉積加以阻擋。此後，藉由在介電閾電壓調整層上選擇性沉積含金屬閘電極膜112/113，可更進一步處理奈米線結構10。根據另一實施例，藉由將第一及第二含金屬閘電極膜112/113摻雜、藉由使用第一及第二含金屬閘電極膜112/113的不同厚度、或是上述兩者，可調整奈米線結構10/11的Vt 。
圖2透過剖面圖示意地顯示根據本發明實施例之部分製造的奈米線裝置。奈米線結構20與圖1I中的奈米線結構10相似並包含：垂直隔片204/206，及在垂直隔片204/206之間垂直堆疊的奈米線202。垂直隔片204可含有介電材料，例如SiCOH材料。在奈米線結構20中僅顯示三條奈米線202，然而本發明之實施例可包含任何數量的奈米線。奈米線202可包含外延Si材料且奈米線結構20可在基板200上形成NMOS裝置。替代地，奈米線202可包含外延SiGe材料且奈米線結構200可在基板200上形成PMOS裝置。
奈米線結構20更包含：選擇性沉積在垂直隔片204上的介電膜207、在奈米線202上的高k膜210、在高k膜210上的含金屬閘電極膜212、以及金屬閘極209。介電膜207的選擇性沉積可在高k膜210沉積之前的製造製程期間的任何時間執行。介電膜207（例如SiOx ，其中x ≤ 2）具有低於高k膜210的介電常數（k），且這允許控制（降低）奈米線結構20的閘極與汲極間電容。這與圖1I中的奈米線結構10形成對比，其中這樣的介電膜不存在而高k膜110及第一含金屬閘電極膜112則在開口140中選擇性沉積在奈米線102周圍，從而導致較奈米線結構20高的閘極與汲極間電容。這亦與將高k膜非選擇性沉積在奈米線結構周圍以及在垂直隔片204表面上的奈米線結構形成對比。再者，在圖2中，在垂直隔片204上介電膜207的選擇性沉積並不影響在奈米線202上高k膜210的選擇性沉積以及在高k膜210上含金屬閘電極膜212的選擇性沉積。
在垂直隔片上選擇性沉積介電膜207以控制閘極與汲極間電容，可取代增加隔片204厚度的需求。增加隔片204的厚度可導致標準單元的接點多晶間距（CCP）的增加，或是若要維持CCP則可導致閘極長度或接點面積的減少。這些效應兩者皆可負面影響短通道效應及接觸電阻，且可因此對某些裝置造成問題。增加垂直隔片204的厚度亦更進一步延伸在源極及閘極間穿通之通道的長度，且這可導致效能劣化，而在垂直隔片204上選擇性放置介電膜207允許了薄垂直隔片204的使用並使源極及閘極間的距離維持在最小。
圖3透過剖面圖示意地顯示根據本發明實施例之部分製造的奈米線裝置。奈米線結構30與圖2中的奈米線結構20相似，但介電膜207由介電膜211所取代，介電膜211在高k膜210沉積在奈米線202上以及含金屬閘電極膜212沉積在高k膜210上之後，沉積在奈米線202上方。由於這允許介電膜211比介電膜207更厚，因為前者不佔據奈米線202周圍的空間。這可顯著地更進一步降低閘極與汲極間電容。
形成奈米線裝置之方法的複數個實施例已在此描述。出於說明與描述的目的，本發明的實施例已在前述內容表明。此內容並非旨在全面詳述或限制本發明於所揭露內容於此精確形式。此描述與後續申請專利範圍中包含之用語僅供描述性目的而不應解釋為其限制。與此發明相關之所屬領域中具有通常知識者可了解，鑒於上述教示，許多調整與改變是可行的。因此，上述旨在說明本發明的範圍不受細節描述所限，而是受隨附在此處之申請專利範圍所限。
10:奈米線結構 11:奈米線結構 20:奈米線結構 30:奈米線結構 100:基板 102:奈米線 103:奈米線 104:垂直隔片 106:垂直隔片 108:SiO2層 109:SiO2層 110:高k膜 111:高k膜 112:第一含金屬閘電極膜 113:第二含金屬閘電極膜 140:開口 141:開口 200:基板 202:奈米線 204:垂直隔片 206:垂直隔片 207:介電膜 209:金屬閘極 210:高k膜 211:介電膜 212:含金屬閘電極膜
當結合隨附圖式參考後續實施方式章節，將能更完整了解本發明且藉由參考後續說明書許多其伴隨的優點也同樣變得更能理解，其中：
圖1A-1J透過剖面圖示意地顯示根據本發明實施例之部分製造的奈米線裝置的形成；
圖2透過剖面圖示意地顯示根據本發明實施例之部分製造的奈米線裝置；
圖3透過剖面圖示意地顯示根據本發明實施例之部分製造的奈米線裝置。
10:奈米線結構
100:基板
102:奈米線
104:垂直隔片
106:垂直隔片
140:開口

Claims (20)

  1. 一種奈米線裝置的形成方法，該方法包含： 提供一基板，該基板包含在垂直隔片之間的奈米線； 相對於該垂直隔片在該奈米線上選擇性沉積一高k膜；以及 相對於該垂直隔片在該高k膜上選擇性沉積一含金屬閘電極層。
  2. 如申請專利範圍第1項之奈米線裝置的形成方法，更包含： 在選擇性沉積該高k膜之前，在該垂直隔片上選擇性沉積一介電材料，其中該介電材料具有低於該高k膜之介電常數。
  3. 如申請專利範圍第2項之奈米線裝置的形成方法，其中在該垂直隔片上選擇性沉積該介電材料的步驟包含沉積足夠的介電材料以降低該奈米線裝置中的閘極與汲極間電容。
  4. 如申請專利範圍第1項之奈米線裝置的形成方法，更包含： 在選擇性沉積該含金屬閘電極層之後，在該奈米線上方之垂直隔片上沉積一介電材料，其中該介電材料具有低於該高k膜之介電常數。
  5. 如申請專利範圍第1項之奈米線裝置的形成方法，更包含： 在選擇性沉積該高k膜之前，將該基板暴露於一等向性氧化電漿，其在該奈米線上形成氧化物層。
  6. 如申請專利範圍第4項之奈米線裝置的形成方法，更包含： 從該奈米線移除該氧化物層。
  7. 如申請專利範圍第1項之奈米線裝置的形成方法，其中該奈米線由Si、SiGe、或Si及SiGe兩者所組成。
  8. 如申請專利範圍第1項之奈米線裝置的形成方法，其中該垂直隔片含有SiCOH材料、低k材料、或氣隙隔片。
  9. 如申請專利範圍第1項之奈米線裝置的形成方法，其中該高k膜包含HfO2 、ZrO2 、TiO2 、或Al2 O3 。
  10. 如申請專利範圍第1項之奈米線裝置的形成方法，其中該奈米線由Si所組成，而該含金屬閘電極層含有TiSiN、TiAlC、富含Ti的TiN、W、WNx 、Mo、或Pt。
  11. 如申請專利範圍第1項之奈米線裝置的形成方法，其中該奈米線由SiGe所組成，而該含金屬閘電極層含有TiN、TiON、Ru、W、WNx 、Mo、或Pt。
  12. 如申請專利範圍第1項之奈米線裝置的形成方法，更包含在該高k膜上沉積一介電閾電壓調整層。
  13. 如申請專利範圍第12項之奈米線裝置的形成方法，其中該奈米線由Si所組成，而該介電閾電壓調整層包含La2 O3 或Y2 O3 。
  14. 如申請專利範圍第12項之奈米線裝置的形成方法，其中該奈米線由SiGe所組成，而該介電閾電壓調整層包含Al2 O3 。
  15. 如申請專利範圍第1項之奈米線裝置的形成方法，更包含將該高k膜暴露於一等向性氧化電漿，其在該奈米線及該高k膜的介面形成氧化物層。
  16. 如申請專利範圍第1項之奈米線裝置的形成方法，其中選擇性沉積該高k膜的步驟包含在該垂直隔片上阻擋該高k膜的沉積。
  17. 如申請專利範圍第16項之奈米線裝置的形成方法，其中該阻擋步驟包含在該垂直隔片上形成自組裝單層（SAM）。
  18. 如申請專利範圍第1項之奈米線裝置的形成方法，其中選擇性沉積該含金屬閘電極層的步驟包含在該垂直隔片上阻擋該含金屬閘電極層的沉積。
  19. 如申請專利範圍第18項之奈米線裝置的形成方法，其中該阻擋步驟包含在該垂直隔片上形成自組裝單層（SAM）。
  20. 一種奈米線裝置的形成方法，該方法包含： 提供一基板，該基板在垂直隔片之間含有Si、SiGe、或Si及SiGe兩者的奈米線； 在該垂直隔片上選擇性沉積一介電材料，其中在該垂直隔片上之該介電材料的該選擇性沉積步驟包含沉積足夠的介電材料以降低該奈米線裝置中的閘極與汲極間電容； 藉由將在該垂直隔片上之一高k膜的沉積加以阻擋，以相對於該垂直隔片在該奈米線上選擇性沉積該高k膜，其中該介電材料具有低於該高k膜之介電常數；以及 藉由將在該垂直隔片上之一含金屬閘電極層的沉積加以阻擋，以相對於該垂直隔片在該高k膜上選擇性沉積該含金屬閘電極層。
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