CN102214596B - 一种以空气为侧墙的围栅硅纳米线晶体管的制备方法 - Google Patents

一种以空气为侧墙的围栅硅纳米线晶体管的制备方法 Download PDF

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CN102214596B
CN102214596B CN201110139453.9A CN201110139453A CN102214596B CN 102214596 B CN102214596 B CN 102214596B CN 201110139453 A CN201110139453 A CN 201110139453A CN 102214596 B CN102214596 B CN 102214596B
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黄如
诸葛菁
樊捷闻
艾玉杰
王润声
黄欣
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Peking University
Semiconductor Manufacturing International Beijing Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66439Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/775Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

本发明公布了一种以空气为侧墙的围栅硅纳米线晶体管的制备方法。方法包括:隔离并淀积与Si有高刻蚀选择比的材料A;光刻定义Fin条硬掩膜;刻蚀材料A,形成Fin条的硬掩膜;源漏注入;光刻定义沟道区和大源漏区;形成Si Fin条和大源漏;去除材料A硬掩膜;形成纳米线;腐蚀SiO2,形成悬空纳米线;形成栅氧化层;淀积多晶硅;多晶硅注入;杂质激活退火;刻蚀多晶硅;淀积SiN;光刻定义栅线条;刻蚀SiN和多晶硅形成栅线条;将源漏与栅分离,之间区域为空气填充;淀积SiO2,形成空气侧墙;退火致密SiO2层;后续流程完成器件制备。本方法与CMOS工艺流程相兼容,空气侧墙的引入能有效减小器件的寄生电容,提高器件瞬态响应特性,适用于高性能逻辑电路应用。

Description

一种以空气为侧墙的围栅硅纳米线晶体管的制备方法
技术领域
本发明属于CMOS超大规模集成电路(ULSI)制造技术领域,具体涉及一种以空气为侧墙的围栅硅纳米线晶体管的制备方法。
背景技术
随着CMOS器件特征尺寸逐步缩小,进入到深亚微米、纳米领域,而寄生电容不能相应缩小,特别是栅和源漏之间的边缘(fringing)寄生电容(图1),在总电容中的比例越来越大,从而严重影响器件的瞬态相应。
另外一方面,随着器件尺寸的持续缩小,到深亚微米量级时,短沟道效应越来越明显,导致阈值电压漂移、亚阈值斜率增加、亚阈区泄漏电流增加、漏致势垒降低效应等等,为了抑制恶化的短沟道效应,可以从新结构方面来对传统平面管进行改革。由于具有围栅结构和纳米级的沟道直径,围栅硅纳米线器件具有非常优秀的短沟道效应控制能力,是在极短沟道条件下有希望替代传统平面器件的新器件结构。但是由于围栅硅纳米线晶体管的沟道直径仅为纳米级,本征电容很小,而栅到源漏的边缘电容较大(图2),使得寄生电容对器件瞬态响应的影响较之平面管而言更加严重。
采用较低介电常数的材料作为侧墙,能够减小栅和源漏之间的电容耦合效应,从而减小边缘寄生电容。空气具有极低的介电常数,可以预见,采用空气作为侧墙的围栅硅纳米线器件将具有较小的寄生电容。图3为采用传统SiO2侧墙和空气侧墙的围栅硅纳米线器件的示意图。图4和图5分别为器件沿着AA’和BB’的截面图。
图6(a)和6(b)分别为在沟道长度为20nm,纳米线直径10nm,侧墙厚度为10nm的围栅硅纳米线器件中,采用传统的SiO2侧墙和空气侧墙的示意图。图6(c)为其栅电容的对比图,可见,采用空气侧墙能够极大的减小寄生电容。
目前为止,关于围栅硅纳米线器件的实验研究主要集中在工艺集成、特性表征和以寄生电阻减小为主要目标的特性优化上,对于寄生电容的优化未有报道。使用空气作为侧墙能够减小寄生电容这样一种理念无论是在平面管还是多栅结构中应用都能够有效的减小寄生电容,但是由于纳米线独特的三维结构,如何形成空气侧墙需要特殊的工艺流程设计,这方面的研究目前未见报道。
发明内容
本发明的目的是提出一种以空气为侧墙的硅纳米线晶体管的制备方法,该晶体管在SOI(Silicon-On-Insulator,绝缘衬底上的硅)衬底上制备。
本发明提供的技术方案如下:
一种以空气为侧墙的硅纳米线晶体管的制备方法,其特征在于,在SOI衬底上制备,包括依次进行如下步骤:
1)隔离工艺;
2)淀积与Si有较高刻蚀选择比的材料A(如SiN、SiO2等);
3)光刻定义Fin条硬掩膜;
4)刻蚀材料A,将光刻胶上的图形转移到材料A上,形成Fin条的硬掩膜;
5)注入源漏;
6)光刻定义沟道区和大源漏区;
7)以光刻胶和材料A的Fin条硬掩膜为阻挡,刻蚀Si,形成Si Fin条和大源漏;
8)去除材料A硬掩膜;
9)氧化,形成纳米线;
10)各向同性湿法腐蚀SiO2,形成悬空纳米线;
11)形成栅氧化层;
12)淀积多晶硅;
13)注入多晶硅;
14)杂质激活退火;
15)刻蚀多晶硅,在源漏上剩下厚度为30~50纳米的多晶硅;
16)淀积SiN;
17)光刻定义栅线条;
18)刻蚀SiN和多晶硅,将光刻胶上的图形转移到多晶硅上,形成栅线条;
19)采用各向同性干法刻蚀或者各向同性湿法腐蚀多晶硅,将源漏与栅分离,之间区域为空气填充;
20)淀积SiO2,形成空气侧墙;
21)退火致密SiO2层;
22)采用常规CMOS后端工艺完成后续流程,完成器件制备。
所述步骤1)采用硅岛隔离。
所述步骤4)、7)、15)、18)采用各向异性干法刻蚀技术。
所述步骤5)采用的是0度角注入。
所述步骤8)采用的是170℃浓磷酸去除SiN。
所述步骤9)采用的是干氧氧化,或者氢氧合成氧化。
所述步骤10)采用的是氢氟酸去掉氧化硅。
所述步骤11)采用的是干氧氧化形成SiO2介质层,或者采用其他高介电常数的介质层。
所述步骤2)、12)、16)、20)采用的是化学气相淀积方法。
所述步骤19)采用各向同性干法刻蚀,或者采用各向同性湿法腐蚀。
本发明的有益效果:本发明提供的以空气为侧墙的硅纳米线晶体管的制备方法,与CMOS工艺流程相兼容,空气侧墙的引入能有效减小器件的寄生电容,提高器件瞬态响应特性,适用于高性能逻辑电路应用。
附图说明
图1栅与源漏的边缘(fringing)电容示意图
图2围栅硅纳米线器件边缘电容示意图
图3SiO2和空气侧墙的围栅硅纳米线器件
图4SiO2和空气侧墙的围栅硅纳米线器件沿着AA’的截面图
图5SiO2和空气侧墙的围栅硅纳米线器件沿着BB’的截面图
图6(a)SiO2和(b)空气侧墙的纳米线器件示意图及其(c)栅电容
图7至图16为实施实例的工艺流程图,图中各层材料的说明如下:
1-Si        2-埋氧化层
3-SiN       4-SiO2
5-多晶硅6-空气
具体实施方式
下面结合附图和具体实施例对本发明作进一步阐述。
实施例1:从SOI衬底(埋氧化层上的Si厚度为
Figure GDA0000143402110000031
)出发,依次进行如下步骤:
1.采用硅岛隔离方法
2.低压化学气相淀积(LPCVD)
Figure GDA0000143402110000041
3.光刻定义Fin硬掩膜
4.采用反应离子刻蚀技术(RIE)刻蚀并去胶清洗,如图7所示
5.As注入,0度角,能量50keV,剂量4×1015cm-2,如图8所示
6.光刻定义沟道区和大源漏区
7.以光刻胶和SiN Fin条硬掩膜为阻挡,感应耦合等离子(ICP)刻蚀
Figure GDA0000143402110000043
形成SiFin条和大源漏,并去胶清洗,如图9所示
8.170℃浓磷酸选择腐蚀SiN,将SiN硬掩膜去除干净
9.干氧氧化,形成硅纳米线
10.采用缓冲氢氟酸(BHF)将干氧氧化的SiO2腐蚀掉,形成悬空纳米线,如图10所示
11.栅氧氧化,形成5纳米栅氧化层
12.低压化学气相淀积(LPCVD)多晶硅
Figure GDA0000143402110000044
如图11所示
13.As注入,能量80KeV,剂量8×1015cm-2
14.氮气中1050℃快速热退火(RTP)10秒钟,激活杂质
15.感应耦合等离子(ICP)刻蚀多晶硅
Figure GDA0000143402110000045
如图12所示
16.低压化学气相淀积(LPCVD)
Figure GDA0000143402110000046
17.光刻定义栅线条
18.采用反应离子刻蚀技术(RIE)刻蚀
Figure GDA0000143402110000047
感应耦合等离子(ICP)刻蚀多晶硅,直到源漏上方的多晶硅被刻蚀干净,如图14所示
19.采用HNA溶液各向同性腐蚀多晶硅,将源漏与栅分离,之间区域为空气填充
20.低压化学气相淀积(LPCVD)形成空气侧墙
21.氮气中1050℃快速热退火(RTP)5秒钟,致密氧化层
22.光刻金属接触孔
23.采用反应离子刻蚀技术(RIE)刻蚀采用缓冲氢氟酸(BHF)将孔内剩余的氧化硅腐蚀干净,去胶清洗
24.溅射Ti/Al,
Figure GDA00001434021100000410
25.光刻金属引线
26.RIE刻蚀Al/Ti
Figure GDA00001434021100000411
去胶清洗
27.N2+H2中430℃下退火30分钟,合金化,器件制备完成
实施例2:如实施实例1,不同之处在于下列步骤:
1.采用LOCOS隔离方法
2.低压化学气相淀积(LPCVD)
4.采用反应离子刻蚀技术(RIE)刻蚀并去胶清洗
7.以光刻胶和SiO2 Fin条硬掩膜为阻挡,感应耦合等离子(ICP)刻蚀形成Si Fin条和大源漏,并去胶清洗
8.采用缓冲氢氟酸(BHF)腐蚀SiO2,将SiO2硬掩膜去除干净
9.氢氧合成氧化,形成硅纳米线
10.采用缓冲氢氟酸(BHF)将氢氧合成氧化的SiO2腐蚀掉,形成悬空纳米线。

Claims (9)

1.一种以空气为侧墙的硅纳米线晶体管的制备方法,其特征在于,在SOI衬底上制备,包括依次进行如下步骤:
1)隔离工艺;
2)淀积与Si有较高刻蚀选择比的材料A;
3)光刻定义Fin条硬掩膜;
4)刻蚀材料A,将光刻胶上的图形转移到材料A上,形成Fin条的硬掩膜;
5)注入源漏;
6)光刻定义沟道区和大源漏区;
7)以光刻胶和材料A的Fin条硬掩膜为阻挡,刻蚀Si,形成Si Fin条和大源漏;
8)去除材料A硬掩膜;
9)氧化,形成纳米线;
10)各向同性湿法腐蚀SiO2,形成悬空纳米线;
11)形成栅氧化层;
12)淀积多晶硅;
13)注入多晶硅;
14)杂质激活退火;
15)刻蚀多晶硅,在源漏上剩下厚度为30~50纳米的多晶硅;
16)淀积SiN;
17)光刻定义栅线条;
18)刻蚀SiN和多晶硅,将光刻胶上的图形转移到多晶硅上,形成栅线条;
19)采用各向同性干法刻蚀或者各向同性湿法腐蚀多晶硅,将源漏与栅分离,之间区域为空气填充;
20)淀积SiO2,形成空气侧墙;
21)退火致密SiO2层;
22)采用常规CMOS后端工艺完成后续流程,完成器件制备。
2.如权利要求1所述的制备方法,其特征在于,所述步骤1)采用硅岛隔离。
3.如权利要求1所述的制备方法,其特征在于,所述步骤4)、7)、15)、18)采用各向异性干法刻蚀技术。
4.如权利要求1所述的制备方法,其特征在于,所述步骤5)采用的是0度角注入。
5.如权利要求1所述的制备方法,其特征在于,所述步骤8)采用的是170℃浓磷酸去除SiN。
6.如权利要求1所述的制备方法,其特征在于,所述步骤9)采用的是干氧氧化,或者氢氧合成氧化。
7.如权利要求1所述的制备方法,其特征在于,所述步骤10)采用的是氢氟酸去掉氧化硅。
8.如权利要求1所述的制备方法,其特征在于,所述步骤11)采用的是干氧氧化形成SiO2介质层,或者采用其他高介电常数的介质层。
9.如权利要求1所述的制备方法,其特征在于,所述步骤2)、12)、16)、20)采用的是化学气相淀积方法。
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