CN102110648B - 一种制备体硅围栅金属半导体场效应晶体管的方法 - Google Patents

一种制备体硅围栅金属半导体场效应晶体管的方法 Download PDF

Info

Publication number
CN102110648B
CN102110648B CN2009102437801A CN200910243780A CN102110648B CN 102110648 B CN102110648 B CN 102110648B CN 2009102437801 A CN2009102437801 A CN 2009102437801A CN 200910243780 A CN200910243780 A CN 200910243780A CN 102110648 B CN102110648 B CN 102110648B
Authority
CN
China
Prior art keywords
etching
gate
sin
thickness
deposit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2009102437801A
Other languages
English (en)
Other versions
CN102110648A (zh
Inventor
宋毅
周华杰
徐秋霞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN2009102437801A priority Critical patent/CN102110648B/zh
Priority to PCT/CN2010/074699 priority patent/WO2011075997A1/zh
Priority to US12/912,531 priority patent/US7960235B1/en
Publication of CN102110648A publication Critical patent/CN102110648A/zh
Application granted granted Critical
Publication of CN102110648B publication Critical patent/CN102110648B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
    • Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种基于准平面工艺制备体硅围栅纳米线MOSFETs的方法：局部氧化隔离或浅槽隔离，在体硅上垫积缓冲SiO2氧化层/SiN介质层，电子束曝光，刻蚀两个距离较近的凹槽，垫积SiN侧墙，各向同性刻蚀Si，干氧氧化，湿法刻蚀去除SiN，应力自限制氧化形成纳米线，垫积并各向异性刻蚀氧化物介质层，并平坦化表面，湿法刻蚀释放纳米线的同时保留底部足够厚SiO2作隔离，长栅介质和垫积栅材料，反刻栅并以栅介质为阻挡层各向同性刻蚀栅材料，源/漏浅注入，垫积和刻蚀侧墙，源/漏深注入，形成接触。本发明消除了自加热效应和浮体效应，并且易于集成，有利于抑制短沟道效应，推动MOSFETs尺寸往小尺寸方向发展。

Description

一种制备体硅围栅金属半导体场效应晶体管的方法
技术领域
本发明属于微电子纳米尺度互补金属氧化物半导体器件(CMOS)及极大规模集成技术领域，特别是指一种基于准平面工艺制备体硅围栅金属半导体场效应晶体管(MOSFETs)的方法。
背景技术
纳米CMOS器件继续按照Moore定律向前发展，持续缩小平面体硅器件的尺寸遇到了严峻的挑战，各种新结构器件应运而生，器件的栅结构从最初的单栅发展到双栅、三栅，到完全包围沟道的围绕栅结构，栅控能力和抑制短沟道效应的能力随着栅的数目的增多而不断增强。具有包围沟道结构和准弹道输运特征的纳米线围栅MOSFET由于有很强的栅控能力和缩小尺寸的能力而成为集成电路技术发展预测路线图22nm及其以下技术节点的有力竞争者。
目前国内外有初步研究成功制备了纳米线围栅MOSFET的报道，表明围栅纳米线结构有近乎完美的抑制短沟道效应的能力、优异的驱动性能和关态特性。由于SOI衬底存在天然的BOX氧化层作为牺牲层，制备围栅结构更为容易，因此还是以SOI衬底为主。但是采用体硅衬底相对SOI衬底有非常明显的优势：
一)消除了SOI衬底存在自加热效应和浮体效应；
二)避免了复杂的源漏工程以降低源漏寄生电阻；
三)普通体硅衬底的价格较SOI圆片要便宜许多；
四)与传统体硅工艺完全兼容。
在体硅上制备围栅器件主要的困难在于形成牺牲层，迄今为止，为数不多的报道的采用体硅衬底的制备方法或需要复杂且昂贵的外延SiGe作为牺牲层的大马士革假栅工艺，或直接各向同性刻蚀Si而造成对衬底的污染，另外还无可避免地造成了大的寄生电容电阻，更重要的是，复杂的立体工艺大大加大了制备的难度，很难借用已有成熟的主流平面工艺。这些都存在明显的缺点和进一步缩小尺寸的局限性。
制备体硅围栅纳米线MOSFET，还有很多的问题要解决。在选择具体实施方案时首先要考虑很多因素，比如：
(1)与CMOS工艺的兼容性要好，应尽量避免造成工艺的不确定性和增加工艺难度，如果采用准平面工艺可借鉴已有的平面工艺技术，大大降低工艺的风险和不确定性；
(2)工艺的简化，可靠性和可重复性。工艺的简化对于提高成品率至关重要。要降低线边缘粗糙度、膜厚的非均匀性，尽可能地减小工艺浮动对器件性能的影响；
(3)进一步缩小尺寸的能力。
有必要寻找新的、易于集成到平面CMOS工艺中去的体硅纳米线围绕栅MOSFETs的制备方法。
发明内容
本发明目的在于提供一种易于集成的、与平面CMOS工艺兼容性好的体硅围栅金属半导体场效应晶体管(MOSFETs)的制备方法。
为了实现上述目的，本发明提供的基于准平面工艺制备体硅围栅纳米线金属半导体场效应晶体管的方法，其主要步骤是：
1)N阱和P阱形成；
2)场区光刻，场区注入，局部氧化隔离或浅槽隔离；
3)垫积缓冲SiO2氧化层/SiN介质层；
4)正性电子束曝光并刻蚀介质层形成凹槽；
5)垫积缓冲SiO2氧化层和SiN并刻蚀形成侧墙；
6)各向同性刻蚀Si；
7)第一步干氧氧化；
8)湿法腐蚀去除剩余的SiN；
9)第二步干氧氧化形成纳米线；
10)垫积并各向异性刻蚀硅酸四乙酯或低温垫积氧化物，然后平坦化表面；
11)湿法刻蚀各向同性释放纳米线；
12)淀积栅介质；
13)淀积栅电极材料；
14)各向异性刻蚀栅电极；
15)各向同性刻蚀栅电极；
16)源漏延伸区注入；
17)各向同性淀积SiN并各向异性刻蚀形成侧墙；
18)源漏深注入；
19)形成硅化物；
20)金属化；
所述的方法中，所述步骤3中淀积缓冲SiO2氧化层厚度为5-50nm，垫积SiN厚度为20-800nm。
所述的方法中，所述步骤4中正性电子束曝光采用正性电子束光刻胶；相邻的介质凹槽的刻蚀采用氟基反应离子刻蚀；相邻的硅凹槽的刻蚀采用氯基反应离子刻蚀。
所述的方法中，所述步骤5中垫积的缓冲氧化层厚度为5-15nm和SiN厚度为20-80nm并刻蚀形成侧墙；
所述的方法中，所述步骤6中各向同性刻蚀Si深度为20-80nm。
所述的方法中，所述步骤7中干氧氧化的厚度为40-100nm，步骤9中干氧氧化的厚度为10-60nm。
所述的方法中，所述步骤10中垫积并各向异性刻蚀较厚的硅酸四乙酯或低温垫积氧化物100nm-2000nm，然后平坦化表面。
所述的方法中，所述步骤12中栅介质的等效氧化层厚度为6至40
Figure G2009102437801D00031
栅介质为SiON、HfON、HfAlO、HfA1ON、HfTaO、HfTaON、HfSiO、HfSiON、HfLaO或HfLaON；栅介质层可通过低压化学气相沉积、物理气相淀积、金属有机化学气相沉积或者原子层淀积形成。
所述的方法中，所述步骤13中栅电极材料为W、Ti、Ta、Mo、TiN、TaN、HfN或MoN；栅电极材料可采用低压化学气相淀积、金属有机化学气相沉积或者原子层淀积形成，厚度为1000至2000
Figure G2009102437801D00032
所述的方法中，所述步骤15中以栅介质层为硬掩膜各向同性刻蚀栅材料，横向刻蚀深度为10-150nm。
本发明消除了自加热效应和浮体效应，具有更低的成本，完全采用传统的基于准平面的自顶向下工艺实现了与CMOS平面工艺的良好兼容，并且易于集成，有利于抑制短沟道效应，推动MOSFETs尺寸往小尺寸方向发展。
附图说明
图1(a)-(j)给出了本方法的悬浮纳米线的制备步骤；其中：
(a)为垫积预氧/SiN介质层；
(b)为正性电子束曝光并刻蚀两个凹槽；
(c)为化学气相垫积的缓冲氧化层厚度和SiN；
(d)为各向异性刻蚀SiO2/SiN叠层形成侧墙；
(e)为各向异性刻蚀Si；
(f)为第一次干氧氧化；
(g)为湿法各向同性刻蚀去除SiN；
(h)为第二次干氧氧化，应力限制作用形成纳米线；
(i)为各向同性垫积并刻蚀氧化物(TEOS或LTO)介质层，并对表面进行平坦化；
(j)为湿法腐蚀氧化物释放纳米线。
图2给出了器件制备工艺流程所用的版图。
图中各组件符号说明：
101Si衬底；102缓冲SiO2氧化层；103SiN介质层；104两个相邻的凹槽；105SiN侧墙；106侧墙缓冲SiO2氧化层；107第一次氧化SiO2氧化层；108第二次氧化SiO2氧化层；109Si纳米线；110氧化物(TEOS或LTO)介质层；201有源区版；202相邻凹槽版；203栅版；204接触版。
具体实施方式
本发明的制备步骤如下：
1)双阱工艺，推阱
2)局部氧化(LOCOS)隔离或浅槽(STI)隔离；
3)垫积缓冲SiO2氧化层/SiN介质层；
4)正性电子束曝光并刻蚀凹槽；
5)各向同性垫积缓冲SiO2氧化层和SiN薄膜并对其各向异性刻蚀形成侧墙；
6)各向同性刻蚀Si；
7)第一步干氧氧化；
8)湿法各向同性刻蚀SiN；
9)第二步干氧氧化形成纳米线；
10)垫积并各向异性刻蚀氧化物(TEOS或LTO)介质层，然后平坦化表面；
11)湿法刻蚀各向同性释放纳米线；
12)淀积栅介质；
13)淀积栅电极材料；
14)电子束光刻氧化物硬掩膜，各向异性刻蚀栅电极；
15)各向同性刻蚀栅电极；
16)源漏延伸区浅注入；
17)各向同性垫积SiN并各向异性刻蚀形成侧墙；
18)源漏深注入；
19)形成硅化物；
20)金属化。
步骤1中的N阱注入采用+P31，P阱注入采用+B11，阱深1-2微米。
步骤2中的局部氧化隔离或浅槽隔离中，隔离层厚度为4000至6000
Figure G2009102437801D00051
步骤3中缓冲SiO2氧化层厚度5-50nm，垫积SiN厚度20-800nm。
步骤4中正性电子束曝光采用正性电子束光刻胶。相邻的介质凹槽的刻蚀采用氟基反应离子刻蚀。相邻的硅凹槽的刻蚀采用氯基反应离子刻蚀。
步骤5中垫积的缓冲氧化层厚度5-15nm和SiN厚度20-80nm并刻蚀形成侧墙。
步骤6中各向同性刻蚀Si深度为20-80nm。
步骤7中干氧氧化的厚度分别为40-100nm。
步骤8中湿法腐蚀去除所有SiN。
步骤9中干氧氧化的厚度分别为10-60nm。
步骤10中垫积并各向异性刻蚀氧化物(TEOS或LTO)介质层，然后平坦化表面；
步骤11中释放纳米线采用各向同性腐蚀氧化物。
步骤12中栅介质的等效氧化层厚度为6至40
Figure G2009102437801D00061
栅介质可以是SiON、HfON、HfAlO、HfAlON、HfTaO、HfTaON、HfSiO、HfSiON、HfLaO和HfLaON，栅介质层可通过低压化学气相沉积、物理气相淀积、金属有机化学气相沉积或者原子层淀积形成。
步骤13中栅电极材料可以是多晶硅和金属栅材料(如难熔金属W，Ti，Ta，Mo和金属氮化物TiN，TaN，HfN，MoN等)，栅电极材料可采用低压化学气相淀积，金属有机化学气相沉积或者原子层淀积形成，厚度为1000至2000
Figure G2009102437801D00062
步骤14中电子束光刻氧化物硬掩膜，以氧化层为硬掩膜各向异性刻蚀栅材料，横向刻蚀深度为100-200nm。
步骤15中以栅介质层为硬掩膜各向同性刻蚀栅材料，横向刻蚀深度为10-100nm。
步骤16中源漏延伸区注入采用低能注入。
步骤17中各向同性淀积SiN并各向异性刻蚀形成侧墙的厚度为10-50nm。
步骤18中源漏注入nMOSFET采用As注入，pMOSFET采BF2注入。
步骤19中硅化物采用NiSi或其他金属硅化物，溅射金属如Ni后，采用两部步快速热退火形成。
步骤20中金属化采用多层金属Ti/TiN//Al-Si/TiN，光刻后刻蚀形成引线接触，然后合金。
以下结合附图作进一步的说明。
实施例
1)双阱工艺和推进：N+阱注入Si衬底(101)采用P31+，能量为110-150KeV，剂量为(1-2)e13，P+阱注入Si衬底(101)采用B11+，能量为110-150KeV，剂量为(1-2)e13；并推进，阱深1-2微米；
2)等平面局部氧化(LOCOS)隔离，长场氧：1000℃，3000-5000
Figure G2009102437801D00071
或浅沟槽隔离(STI)；
3)如图1(a)所示，热生长缓冲SiO2氧化层(102)15nm/化学气相垫积SiN(103)50nm；
4)如图1(b)所示，采用正性电子束曝光并刻蚀陡直的宽度为400nm*400nm间距为50nm的两相邻凹槽(104)；
5)如图1(c)和图1(d)所示，化学气相垫积的缓冲氧化层厚度10nm(106)和SiN厚度50nm(105)并刻蚀形成侧墙；
6)如图1(e)所示，各向同性刻蚀Si深度为50nm；
7)如图1(f)所示，干氧氧化的厚度分别为80nm(107)；
8)如图1(g)所示，湿法腐蚀去除所有剩余SiN，露出底部预氧；
9)如图1(h)所示，第二次氧化的厚度分别为40nm(108)，应力限制终止氧化形成纳米线(109)；
10)如图1(i)所示，垫积LTO 300nm，并各向异性刻蚀300nm，然后平坦化表面(110)；
11)如图1(j)所示，采用各向同性腐蚀80nm SiO2释放纳米线(109)；
12)干氧生长栅氧化介质的等效氧化层厚度为30
Figure G2009102437801D00072
13)多晶硅采用化学气相淀积LPCVD方法垫积，垫积的多晶硅的厚度为1500
Figure G2009102437801D00073
14)电子束光刻氧化物硬掩膜，以氧化层为硬掩膜各向异性刻蚀栅材料，横向刻蚀深度为100nm；
15)以栅介质层为硬掩膜各向同性刻蚀栅材料，横向刻蚀深度为80nm；
16)源延伸区和漏延伸区浅注入的能量为(As为2-6keV，B为1-6keV)剂量为(As为1-8e14/cm3，B为1-6e14/cm3)；
17)干氧生长缓冲SiO2氧化层10nm，各向同性垫积SiN厚度为30nm并各向异性刻蚀30nm的SiN和10nm的预氧形成侧墙；
18)源区漏区深注入的能量为(As为10-30keV，B为5-15keV)，剂量为(As为4e15/cm3，B为3e15/cm3)；
19)淀积金属镍Ni的厚度为120-200
Figure G2009102437801D00081
两步RTA退火形成Ni硅化物；
20)金属化，采用多层金属Ti/TiN/Al-Si/TiN，光刻、刻蚀后形成引线接触；合金：温度530℃，时间40秒。
以上通过详细实例描述了本发明所提供的纳米线围栅器件及其制备方法，本领域的技术人员应当理解，在不脱离本发明实质的范围内，可以对本发明的器件结构做一定的变形或修改，其制备方法也不限于实施例中所公开的内容。

Claims (10)

1.一种基于准平面工艺制备体硅围栅纳米线金属半导体场效应晶体管的方法，其主要步骤是： 
1)N阱和P阱形成； 
2)场区光刻，场区注入，局部氧化隔离或浅槽隔离； 
3)淀积缓冲SiO2氧化层/SiN介质层； 
4)正性电子束曝光并刻蚀介质层形成凹槽； 
5)淀积缓冲SiO2氧化层和SiN并刻蚀形成侧墙； 
6)各向同性刻蚀Si； 
7)第一步干氧氧化； 
8)湿法腐蚀去除剩余的SiN； 
9)第二步干氧氧化形成纳米线； 
10)淀积并各向异性刻蚀硅酸四乙酯或低温淀积氧化物，然后平坦化表面； 
11)湿法刻蚀各向同性释放纳米线； 
12)淀积栅介质； 
13)淀积栅电极材料； 
14)各向异性刻蚀栅电极； 
15)各向同性刻蚀栅电极； 
16)源漏延伸区注入； 
17)各向同性淀积SiN并各向异性刻蚀形成侧墙； 
18)源漏深注入； 
19)溅射金属后，采用两步快速热退火形成硅化物； 
20)采用多层金属，光刻后刻蚀形成金属化。 
2.根据权利要求1所述的方法，其中，所述步骤3中淀积缓冲SiO2氧化层厚度为5-50nm，淀积SiN厚度为20-800nm。 
3.根据权利要求1所述的方法，其中，所述步骤4中正性电子束曝光采用正性电子束光刻胶；相邻的介质凹槽的刻蚀采用氟基反应离子刻蚀；相邻的硅凹槽的刻蚀采用氯基反应离子刻蚀。 
4.根据权利要求1所述的方法，其中，所述步骤5中淀积的缓冲氧化层厚度为5-15nm和SiN厚度为20-80nm并刻蚀形成侧墙。 
5.根据权利要求1所述的方法，其中，所述步骤6中各向同性刻蚀Si深度为20-80nm。 
6.根据权利要求1所述的方法，其中，所述步骤7中干氧氧化的厚度为40-100nm，步骤9中干氧氧化的厚度为10-60nm。 
7.根据权利要求1所述的方法，其中，所述步骤10中淀积并各向异性刻蚀较厚的硅酸四乙酯或低温淀积氧化物100nm-2000nm，然后平坦化表面。 
8.根据权利要求1所述的方法，其中，所述步骤12中栅介质的等效氧化层厚度为6至
Figure FDA00002823830800021
栅介质为SiON、HfON、HfAlO、HfAlON、HfTaO、HfTaON、HfSiO、HfSiON、HfLaO或HfLaON；栅介质层可通过低压化学气相沉积、物理气相淀积、金属有机化学气相沉积或者原子层淀积形成。 
9.根据权利要求1所述的方法，其中，所述步骤13中栅电极材料为W、Ti、Ta、Mo、TiN、TaN、HfN或MoN；栅电极材料可采用低压化学气相淀积、金属有机化学气相沉积或者原子层淀积形成，厚度为1000至 
Figure FDA00002823830800022
10.根据权利要求1所述的方法，其中，所述步骤15中以栅介质层为硬掩膜各向同性刻蚀栅材料，横向刻蚀深度为10-150nm。 
CN2009102437801A 2009-12-24 2009-12-24 一种制备体硅围栅金属半导体场效应晶体管的方法 Active CN102110648B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2009102437801A CN102110648B (zh) 2009-12-24 2009-12-24 一种制备体硅围栅金属半导体场效应晶体管的方法
PCT/CN2010/074699 WO2011075997A1 (zh) 2009-12-24 2010-06-29 一种制备体硅围栅金属氧化物半导体场效应晶体管的方法
US12/912,531 US7960235B1 (en) 2009-12-24 2010-10-26 Method for manufacturing a MOSFET with a surrounding gate of bulk Si

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2009102437801A CN102110648B (zh) 2009-12-24 2009-12-24 一种制备体硅围栅金属半导体场效应晶体管的方法

Publications (2)

Publication Number Publication Date
CN102110648A CN102110648A (zh) 2011-06-29
CN102110648B true CN102110648B (zh) 2013-05-01

Family

ID=44121881

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009102437801A Active CN102110648B (zh) 2009-12-24 2009-12-24 一种制备体硅围栅金属半导体场效应晶体管的方法

Country Status (3)

Country Link
US (1) US7960235B1 (zh)
CN (1) CN102110648B (zh)
WO (1) WO2011075997A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8541293B2 (en) 2011-09-21 2013-09-24 Institute of Microelectronics, Academy of Sciences Method of controlled lateral etching
CN103021800B (zh) * 2011-09-21 2016-01-27 中国科学院微电子研究所 受控横向刻蚀方法
CN102508942A (zh) * 2011-09-29 2012-06-20 复旦大学 一种围栅结构mosfet源漏电流解析模型
CN102398893A (zh) * 2011-09-30 2012-04-04 中国科学院上海微系统与信息技术研究所 一种在（110）型硅片表面自上而下制备纳米结构的方法
CN102437190A (zh) * 2011-11-30 2012-05-02 上海华力微电子有限公司 硅纳米线器件及其制造方法
CN103378148B (zh) * 2012-04-13 2016-02-03 中芯国际集成电路制造(上海)有限公司 半导体器件及其制造方法
CN102980920A (zh) * 2012-11-14 2013-03-20 华东师范大学 同时检测miRNAs与蛋白标记物的硅纳米线芯片及其检测方法和应用
CN103151269B (zh) * 2013-03-28 2015-08-12 北京大学 制备源漏准soi多栅结构器件的方法
CN104078324B (zh) * 2013-03-29 2018-01-02 中国科学院微电子研究所 堆叠纳米线制造方法
KR102343223B1 (ko) 2015-07-16 2021-12-23 삼성전자주식회사 반도체 장치 및 이의 제조 방법
CN110767550B (zh) * 2018-07-27 2021-04-09 无锡华润上华科技有限公司 Mosfet制作方法
CN111076578A (zh) * 2019-12-25 2020-04-28 龙芯中科(南京)技术有限公司 热管、电子设备及加工工艺

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100707208B1 (ko) * 2005-12-24 2007-04-13 삼성전자주식회사 Ｇａａ 구조의 핀-펫 및 그 제조 방법
CN101060135A (zh) * 2007-06-05 2007-10-24 北京大学 一种双硅纳米线围栅场效应晶体管及其制备方法
CN101483192A (zh) * 2009-02-11 2009-07-15 西安交通大学 一种垂直围栅mosfet器件及其制造方法
CN101556922A (zh) * 2008-04-10 2009-10-14 北京大学 一种纳米环栅mosfet晶体管及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7230286B2 (en) * 2005-05-23 2007-06-12 International Business Machines Corporation Vertical FET with nanowire channels and a silicided bottom contact
JP2006108695A (ja) * 2005-10-27 2006-04-20 Sharp Corp 半導体素子
CN101359627B (zh) * 2008-09-12 2010-06-09 西安电子科技大学 一种SiN掩蔽技术制备多晶SiGe栅纳米级CMOS集成电路方法
US7816275B1 (en) * 2009-04-03 2010-10-19 International Business Machines Corporation Gate patterning of nano-channel devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100707208B1 (ko) * 2005-12-24 2007-04-13 삼성전자주식회사 Ｇａａ 구조의 핀-펫 및 그 제조 방법
CN101060135A (zh) * 2007-06-05 2007-10-24 北京大学 一种双硅纳米线围栅场效应晶体管及其制备方法
CN101556922A (zh) * 2008-04-10 2009-10-14 北京大学 一种纳米环栅mosfet晶体管及其制备方法
CN101483192A (zh) * 2009-02-11 2009-07-15 西安交通大学 一种垂直围栅mosfet器件及其制造方法

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
《Design and optimization considerations for bulk gate-all-around nanowire MOSFETs》;Yi Song et al.;《Semicond. Sci. Technol.》;20091031;第24卷(第10期);105006-1-7 *
《Fabrication of planar silicon nanowires on silicon-on-insulator using stress limited oxidation》;Jakub Kedzierski et al.;《J. Vac. Sci. Technol. B》;19971231;第15卷(第6期);2825-2828 *
《High-Performance Fully Depleted Silicon Nanowire (Diameter ≤ 5 nm) Gate-All-Around CMOS Devices》;N. Singh et al.;《IEEE ELECTRON DEVICE LETTERS》;20060531;第27卷(第5期);383-386 *
Jakub Kedzierski et al..《Fabrication of planar silicon nanowires on silicon-on-insulator using stress limited oxidation》.《J. Vac. Sci. Technol. B》.1997,第15卷(第6期),
N. Singh et al..《High-Performance Fully Depleted Silicon Nanowire (Diameter ≤ 5 nm) Gate-All-Around CMOS Devices》.《IEEE ELECTRON DEVICE LETTERS》.2006,第27卷(第5期),
Yi Song et al..《Design and optimization considerations for bulk gate-all-around nanowire MOSFETs》.《Semicond. Sci. Technol.》.2009,第24卷(第10期),

Also Published As

Publication number Publication date
US20110159656A1 (en) 2011-06-30
CN102110648A (zh) 2011-06-29
US7960235B1 (en) 2011-06-14
WO2011075997A1 (zh) 2011-06-30

Similar Documents

Publication Publication Date Title
CN102110648B (zh) 一种制备体硅围栅金属半导体场效应晶体管的方法
CN108091654B (zh) 用于垂直fet sram及逻辑单元微缩的金属层布线层级
CN104247016B (zh) 具有凹陷的合并鳍片和用于增强应力耦合的衬里的soi鳍片fet
CN106952956A (zh) 半导体器件及其制造方法
US20200279857A1 (en) Memory device
US20120149162A1 (en) Method for manufacturing suspended fin and gate-all-around field effect transistor
CN103730366A (zh) 堆叠纳米线mos晶体管制作方法
TW201019381A (en) Semiconductor devices and methods for making semiconductor devices having metal gate stacks
CN104112665A (zh) 半导体器件及其制造方法
US8288238B2 (en) Method for fabricating a tunneling field-effect transistor
US20150187942A1 (en) Semiconductor structure and method for manufacturing the same
JP2022021341A (ja) ラッチアップ防止
US20130011986A1 (en) Method for Manufacturing Full Silicide Metal Gate Bulk Silicon Multi-Gate Fin Field Effect Transistors
CN102142376A (zh) 硅纳米线围栅器件的制备方法
CN102104002B (zh) 一种制备极短栅长体硅围栅MOSFETs的方法
CN106531632B (zh) 堆叠纳米线mos晶体管制作方法
CN104112667A (zh) 半导体器件及其制造方法
CN104124164A (zh) 半导体器件及其制造方法
CN104124198B (zh) 半导体器件及其制造方法
CN106549054A (zh) Fet及其制作方法
Cheng et al. Improved air spacer co-integrated with self-aligned contact (SAC) and contact over active gate (COAG) for highly scaled CMOS technology
CN106952959A (zh) 一种锗硅沟道鳍式场效应晶体管及其制备方法
CN103579315A (zh) 半导体器件及其制造方法
CN104112668B (zh) 半导体器件及其制造方法
TW202316531A (zh) 形成底部介電隔離層的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant