CN102110648A - 一种制备体硅围栅金属半导体场效应晶体管的方法 - Google Patents
一种制备体硅围栅金属半导体场效应晶体管的方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000010703 silicon Substances 0.000 title claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 title claims description 17
- 239000002184 metal Substances 0.000 title claims description 17
- 230000005669 field effect Effects 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000005530 etching Methods 0.000 claims abstract description 68
- 230000003647 oxidation Effects 0.000 claims abstract description 23
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 18
- 239000002070 nanowire Substances 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 238000001039 wet etching Methods 0.000 claims abstract description 10
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 18
- 239000001301 oxygen Substances 0.000 claims description 18
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 229910003855 HfAlO Inorganic materials 0.000 claims description 3
- 229910004143 HfON Inorganic materials 0.000 claims description 3
- 229910004129 HfSiO Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 125000001309 chloro group Chemical group Cl* 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000001947 vapour-phase growth Methods 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 10
- 230000008569 process Effects 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 230000004888 barrier function Effects 0.000 abstract 1
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 238000010894 electron beam technology Methods 0.000 abstract 1
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 17
- 238000002360 preparation method Methods 0.000 description 12
- 239000000758 substrate Substances 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000000609 electron-beam lithography Methods 0.000 description 3
- 239000007792 gaseous phase Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910018125 Al-Si Inorganic materials 0.000 description 2
- 229910018520 Al—Si Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
一种基于准平面工艺制备体硅围栅纳米线MOSFETs的方法:局部氧化隔离或浅槽隔离,在体硅上垫积缓冲SiO2氧化层/SiN介质层,电子束曝光,刻蚀两个距离较近的凹槽,垫积SiN侧墙,各向同性刻蚀Si,干氧氧化,湿法刻蚀去除SiN,应力自限制氧化形成纳米线,垫积并各向异性刻蚀氧化物介质层,并平坦化表面,湿法刻蚀释放纳米线的同时保留底部足够厚SiO2作隔离,长栅介质和垫积栅材料,反刻栅并以栅介质为阻挡层各向同性刻蚀栅材料,源/漏浅注入,垫积和刻蚀侧墙,源/漏深注入,形成接触。本发明消除了自加热效应和浮体效应,并且易于集成,有利于抑制短沟道效应,推动MOSFETs尺寸往小尺寸方向发展。
Description
技术领域
本发明属于微电子纳米尺度互补金属氧化物半导体器件(CMOS)及极大规模集成技术领域,特别是指一种基于准平面工艺制备体硅围栅金属半导体场效应晶体管(MOSFETs)的方法。
背景技术
纳米CMOS器件继续按照Moore定律向前发展,持续缩小平面体硅器件的尺寸遇到了严峻的挑战,各种新结构器件应运而生,器件的栅结构从最初的单栅发展到双栅、三栅,到完全包围沟道的围绕栅结构,栅控能力和抑制短沟道效应的能力随着栅的数目的增多而不断增强。具有包围沟道结构和准弹道输运特征的纳米线围栅MOSFET由于有很强的栅控能力和缩小尺寸的能力而成为集成电路技术发展预测路线图22nm及其以下技术节点的有力竞争者。
目前国内外有初步研究成功制备了纳米线围栅MOSFET的报道,表明围栅纳米线结构有近乎完美的抑制短沟道效应的能力、优异的驱动性能和关态特性。由于SOI衬底存在天然的BOX氧化层作为牺牲层,制备围栅结构更为容易,因此还是以SOI衬底为主。但是采用体硅衬底相对SOI衬底有非常明显的优势:
一)消除了SOI衬底存在自加热效应和浮体效应;
二)避免了复杂的源漏工程以降低源漏寄生电阻;
三)普通体硅衬底的价格较SOI圆片要便宜许多;
四)与传统体硅工艺完全兼容。
在体硅上制备围栅器件主要的困难在于形成牺牲层,迄今为止,为数不多的报道的采用体硅衬底的制备方法或需要复杂且昂贵的外延SiGe作为牺牲层的大马士革假栅工艺,或直接各向同性刻蚀Si而造成对衬底的污染,另外还无可避免地造成了大的寄生电容电阻,更重要的是,复杂的立体工艺大大加大了制备的难度,很难借用已有成熟的主流平面工艺。这些都存在明显的缺点和进一步缩小尺寸的局限性。
制备体硅围栅纳米线MOSFET,还有很多的问题要解决。在选择具体实施方案时首先要考虑很多因素,比如:
(1)与CMOS工艺的兼容性要好,应尽量避免造成工艺的不确定性和增加工艺难度,如果采用准平面工艺可借鉴已有的平面工艺技术,大大降低工艺的风险和不确定性;
(2)工艺的简化,可靠性和可重复性。工艺的简化对于提高成品率至关重要。要降低线边缘粗糙度、膜厚的非均匀性,尽可能地减小工艺浮动对器件性能的影响;
(3)进一步缩小尺寸的能力。
有必要寻找新的、易于集成到平面CMOS工艺中去的体硅纳米线围绕栅MOSFETs的制备方法。
发明内容
本发明目的在于提供一种易于集成的、与平面CMOS工艺兼容性好的体硅围栅金属半导体场效应晶体管(MOSFETs)的制备方法。
为了实现上述目的,本发明提供的基于准平面工艺制备体硅围栅纳米线金属半导体场效应晶体管的方法,其主要步骤是:
1)N阱和P阱形成;
2)场区光刻,场区注入,局部氧化隔离或浅槽隔离;
3)垫积缓冲SiO2氧化层/SiN介质层;
4)正性电子束曝光并刻蚀介质层形成凹槽;
5)垫积缓冲SiO2氧化层和SiN并刻蚀形成侧墙;
6)各向同性刻蚀Si;
7)第一步干氧氧化;
8)湿法腐蚀去除剩余的SiN;
9)第二步干氧氧化形成纳米线;
10)垫积并各向异性刻蚀硅酸四乙酯或低温垫积氧化物,然后平坦化表面;
11)湿法刻蚀各向同性释放纳米线;
12)淀积栅介质;
13)淀积栅电极材料;
14)各向异性刻蚀栅电极;
15)各向同性刻蚀栅电极;
16)源漏延伸区注入;
17)各向同性淀积SiN并各向异性刻蚀形成侧墙;
18)源漏深注入;
19)形成硅化物;
20)金属化;
所述的方法中,所述步骤3中淀积缓冲SiO2氧化层厚度为5-50nm,垫积SiN厚度为20-800nm。
所述的方法中,所述步骤4中正性电子束曝光采用正性电子束光刻胶;相邻的介质凹槽的刻蚀采用氟基反应离子刻蚀;相邻的硅凹槽的刻蚀采用氯基反应离子刻蚀。
所述的方法中,所述步骤5中垫积的缓冲氧化层厚度为5-15nm和SiN厚度为20-80nm并刻蚀形成侧墙;
所述的方法中,所述步骤6中各向同性刻蚀Si深度为20-80nm。
所述的方法中,所述步骤7中干氧氧化的厚度为40-100nm,步骤9中干氧氧化的厚度为10-60nm。
所述的方法中,所述步骤10中垫积并各向异性刻蚀较厚的硅酸四乙酯或低温垫积氧化物100nm-2000nm,然后平坦化表面。
所述的方法中,所述步骤12中栅介质的等效氧化层厚度为6至40栅介质为SiON、HfON、HfAlO、HfA1ON、HfTaO、HfTaON、HfSiO、HfSiON、HfLaO或HfLaON;栅介质层可通过低压化学气相沉积、物理气相淀积、金属有机化学气相沉积或者原子层淀积形成。
所述的方法中,所述步骤15中以栅介质层为硬掩膜各向同性刻蚀栅材料,横向刻蚀深度为10-150nm。
本发明消除了自加热效应和浮体效应,具有更低的成本,完全采用传统的基于准平面的自顶向下工艺实现了与CMOS平面工艺的良好兼容,并且易于集成,有利于抑制短沟道效应,推动MOSFETs尺寸往小尺寸方向发展。
附图说明
图1(a)-(j)给出了本方法的悬浮纳米线的制备步骤;其中:
(a)为垫积预氧/SiN介质层;
(b)为正性电子束曝光并刻蚀两个凹槽;
(c)为化学气相垫积的缓冲氧化层厚度和SiN;
(d)为各向异性刻蚀SiO2/SiN叠层形成侧墙;
(e)为各向异性刻蚀Si;
(f)为第一次干氧氧化;
(g)为湿法各向同性刻蚀去除SiN;
(h)为第二次干氧氧化,应力限制作用形成纳米线;
(i)为各向同性垫积并刻蚀氧化物(TEOS或LTO)介质层,并对表面进行平坦化;
(j)为湿法腐蚀氧化物释放纳米线。
图2给出了器件制备工艺流程所用的版图。
图中各组件符号说明:
101Si衬底;102缓冲SiO2氧化层;103SiN介质层;104两个相邻的凹槽;105SiN侧墙;106侧墙缓冲SiO2氧化层;107第一次氧化SiO2氧化层;108第二次氧化SiO2氧化层;109Si纳米线;110氧化物(TEOS或LTO)介质层;201有源区版;202相邻凹槽版;203栅版;204接触版。
具体实施方式
本发明的制备步骤如下:
1)双阱工艺,推阱
2)局部氧化(LOCOS)隔离或浅槽(STI)隔离;
3)垫积缓冲SiO2氧化层/SiN介质层;
4)正性电子束曝光并刻蚀凹槽;
5)各向同性垫积缓冲SiO2氧化层和SiN薄膜并对其各向异性刻蚀形成侧墙;
6)各向同性刻蚀Si;
7)第一步干氧氧化;
8)湿法各向同性刻蚀SiN;
9)第二步干氧氧化形成纳米线;
10)垫积并各向异性刻蚀氧化物(TEOS或LTO)介质层,然后平坦化表面;
11)湿法刻蚀各向同性释放纳米线;
12)淀积栅介质;
13)淀积栅电极材料;
14)电子束光刻氧化物硬掩膜,各向异性刻蚀栅电极;
15)各向同性刻蚀栅电极;
16)源漏延伸区浅注入;
17)各向同性垫积SiN并各向异性刻蚀形成侧墙;
18)源漏深注入;
19)形成硅化物;
20)金属化。
步骤1中的N阱注入采用+P31,P阱注入采用+B11,阱深1-2微米。
步骤3中缓冲SiO2氧化层厚度5-50nm,垫积SiN厚度20-800nm。
步骤4中正性电子束曝光采用正性电子束光刻胶。相邻的介质凹槽的刻蚀采用氟基反应离子刻蚀。相邻的硅凹槽的刻蚀采用氯基反应离子刻蚀。
步骤5中垫积的缓冲氧化层厚度5-15nm和SiN厚度20-80nm并刻蚀形成侧墙。
步骤6中各向同性刻蚀Si深度为20-80nm。
步骤7中干氧氧化的厚度分别为40-100nm。
步骤8中湿法腐蚀去除所有SiN。
步骤9中干氧氧化的厚度分别为10-60nm。
步骤10中垫积并各向异性刻蚀氧化物(TEOS或LTO)介质层,然后平坦化表面;
步骤11中释放纳米线采用各向同性腐蚀氧化物。
步骤12中栅介质的等效氧化层厚度为6至40栅介质可以是SiON、HfON、HfAlO、HfAlON、HfTaO、HfTaON、HfSiO、HfSiON、HfLaO和HfLaON,栅介质层可通过低压化学气相沉积、物理气相淀积、金属有机化学气相沉积或者原子层淀积形成。
步骤13中栅电极材料可以是多晶硅和金属栅材料(如难熔金属W,Ti,Ta,Mo和金属氮化物TiN,TaN,HfN,MoN等),栅电极材料可采用低压化学气相淀积,金属有机化学气相沉积或者原子层淀积形成,厚度为1000至2000
步骤14中电子束光刻氧化物硬掩膜,以氧化层为硬掩膜各向异性刻蚀栅材料,横向刻蚀深度为100-200nm。
步骤15中以栅介质层为硬掩膜各向同性刻蚀栅材料,横向刻蚀深度为10-100nm。
步骤16中源漏延伸区注入采用低能注入。
步骤17中各向同性淀积SiN并各向异性刻蚀形成侧墙的厚度为10-50nm。
步骤18中源漏注入nMOSFET采用As注入,pMOSFET采BF2注入。
步骤19中硅化物采用NiSi或其他金属硅化物,溅射金属如Ni后,采用两部步快速热退火形成。
步骤20中金属化采用多层金属Ti/TiN//Al-Si/TiN,光刻后刻蚀形成引线接触,然后合金。
以下结合附图作进一步的说明。
实施例
1)双阱工艺和推进:N+阱注入Si衬底(101)采用P31+,能量为110-150KeV,剂量为(1-2)e13,P+阱注入Si衬底(101)采用B11+,能量为110-150KeV,剂量为(1-2)e13;并推进,阱深1-2微米;
3)如图1(a)所示,热生长缓冲SiO2氧化层(102)15nm/化学气相垫积SiN(103)50nm;
4)如图1(b)所示,采用正性电子束曝光并刻蚀陡直的宽度为400nm*400nm间距为50nm的两相邻凹槽(104);
5)如图1(c)和图1(d)所示,化学气相垫积的缓冲氧化层厚度10nm(106)和SiN厚度50nm(105)并刻蚀形成侧墙;
6)如图1(e)所示,各向同性刻蚀Si深度为50nm;
7)如图1(f)所示,干氧氧化的厚度分别为80nm(107);
8)如图1(g)所示,湿法腐蚀去除所有剩余SiN,露出底部预氧;
9)如图1(h)所示,第二次氧化的厚度分别为40nm(108),应力限制终止氧化形成纳米线(109);
10)如图1(i)所示,垫积LTO 300nm,并各向异性刻蚀300nm,然后平坦化表面(110);
11)如图1(j)所示,采用各向同性腐蚀80nm SiO2释放纳米线(109);
14)电子束光刻氧化物硬掩膜,以氧化层为硬掩膜各向异性刻蚀栅材料,横向刻蚀深度为100nm;
15)以栅介质层为硬掩膜各向同性刻蚀栅材料,横向刻蚀深度为80nm;
16)源延伸区和漏延伸区浅注入的能量为(As为2-6keV,B为1-6keV)剂量为(As为1-8e14/cm3,B为1-6e14/cm3);
17)干氧生长缓冲SiO2氧化层10nm,各向同性垫积SiN厚度为30nm并各向异性刻蚀30nm的SiN和10nm的预氧形成侧墙;
18)源区漏区深注入的能量为(As为10-30keV,B为5-15keV),剂量为(As为4e15/cm3,B为3e15/cm3);
20)金属化,采用多层金属Ti/TiN/Al-Si/TiN,光刻、刻蚀后形成引线接触;合金:温度530℃,时间40秒。
以上通过详细实例描述了本发明所提供的纳米线围栅器件及其制备方法,本领域的技术人员应当理解,在不脱离本发明实质的范围内,可以对本发明的器件结构做一定的变形或修改,其制备方法也不限于实施例中所公开的内容。
Claims (10)
1.一种基于准平面工艺制备体硅围栅纳米线金属半导体场效应晶体管的方法,其主要步骤是:
1)N阱和P阱形成;
2)场区光刻,场区注入,局部氧化隔离或浅槽隔离;
3)垫积缓冲SiO2氧化层/SiN介质层;
4)正性电子束曝光并刻蚀介质层形成凹槽;
5)垫积缓冲SiO2氧化层和SiN并刻蚀形成侧墙;
6)各向同性刻蚀Si;
7)第一步干氧氧化;
8)湿法腐蚀去除剩余的SiN;
9)第二步干氧氧化形成纳米线;
10)垫积并各向异性刻蚀硅酸四乙酯或低温垫积氧化物,然后平坦化表面;
11)湿法刻蚀各向同性释放纳米线;
12)淀积栅介质;
13)淀积栅电极材料;
14)各向异性刻蚀栅电极;
15)各向同性刻蚀栅电极;
16)源漏延伸区注入;
17)各向同性淀积SiN并各向异性刻蚀形成侧墙;
18)源漏深注入;
19)形成硅化物;
20)金属化。
2.根据权利要求1所述的方法,其中,所述步骤3中淀积缓冲SiO2氧化层厚度为5-50nm,垫积SiN厚度为20-800nm。
3.根据权利要求1所述的方法,其中,所述步骤4中正性电子束曝光采用正性电子束光刻胶;相邻的介质凹槽的刻蚀采用氟基反应离子刻蚀;相邻的硅凹槽的刻蚀采用氯基反应离子刻蚀。
4.根据权利要求1所述的方法,其中,所述步骤5中垫积的缓冲氧化层厚度为5-15nm和SiN厚度为20-80nm并刻蚀形成侧墙。
5.根据权利要求1所述的方法,其中,所述步骤6中各向同性刻蚀Si深度为20-80nm。
6.根据权利要求1所述的方法,其中,所述步骤7中干氧氧化的厚度为40-100nm,步骤9中干氧氧化的厚度为10-60nm。
7.根据权利要求1所述的方法,其中,所述步骤10中垫积并各向异性刻蚀较厚的硅酸四乙酯或低温垫积氧化物100nm-2000nm,然后平坦化表面。
10.根据权利要求1所述的方法,其中,所述步骤15中以栅介质层为硬掩膜各向同性刻蚀栅材料,横向刻蚀深度为10-150nm。
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