TW202002022A - 具改進的閘極－源／汲極金屬化隔離的半導體裝置 - Google Patents

具改進的閘極－源／汲極金屬化隔離的半導體裝置 Download PDF

Info

Publication number
TW202002022A
TW202002022A TW108115584A TW108115584A TW202002022A TW 202002022 A TW202002022 A TW 202002022A TW 108115584 A TW108115584 A TW 108115584A TW 108115584 A TW108115584 A TW 108115584A TW 202002022 A TW202002022 A TW 202002022A
Authority
TW
Taiwan
Prior art keywords
gate
layer
conductor layer
item
gate conductor
Prior art date
Application number
TW108115584A
Other languages
English (en)
Inventor
雷亞提斯 艾可納米克斯
輝 臧
謝瑞龍
燦魯 朴
Original Assignee
美商格芯（美國）集成電路科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商格芯（美國）集成電路科技有限公司 filed Critical 美商格芯（美國）集成電路科技有限公司
Publication of TW202002022A publication Critical patent/TW202002022A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1052—Formation of thin functional dielectric layers
    • H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
    • H01L2221/1063—Sacrificial or temporary thin dielectric films in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

一種形成諸如FinFET裝置之一半導體裝置之方法，其包括：在一半導體鰭片之通道區域上方於間隔層之間形成一閘極堆疊，將該閘極堆疊及該等間隔層凹入，及在該凹入之閘極堆疊及該等間隔層兩者上方形成一閘極導體層。調適該閘極導體層以抑制在一後續蝕刻步驟期間對該間隔層之蝕刻損害，該蝕刻步驟用來在該鰭片之源/汲極區域上方形成接觸開口。所得結構展現改善之在閘極及源/汲極接觸間之電性隔離。

Description

具改進的閘極-源/汲極金屬化隔離的半導體裝置
本申請案一般而言係關於用於形成半導體裝置之方法，且更特定言之，係關於用於形成鰭式場效電晶體(FinFET)之方法，其具有降低之閘極及源/汲極接觸間之電短路風險。
半導體製造技術發展之趨勢已增加了每個晶片之裝置密度，並因此減少主動結構之尺寸以及在此等結構間之距離。裝置密度之增加可有利地影響裝置性能，例如：電路速度，且亦可容許更加複雜之設計與功能。然而，尺寸之減少且伴隨之密度增加亦可產生不想要的效果，包括在相鄰導電元件間不想要的短路。
在高級節點FinFET裝置中，閘極接觸及源/汲極接觸之鄰近度可導致在該等相鄰結構之間不想要之寄生電容或導電性(即，漏電)，尤其是在該等結構之各別之頂部及底部部份。在比較結構中，例如，蝕刻層間介電質以形成源/汲極接觸開口可造成在一功能閘極上方佈置之一相鄰包覆層之不想要的侵蝕，其可損害在該閘極及其後形成之源/汲極金屬化間之介 電隔離。
因此需要發展半導體裝置架構及製造裝置架構之方法，其具有減少在相鄰導電元件間之不想要之短路的傾向，例如：在相鄰閘極及源/汲極接觸之間。如所應了解，儘管本文參照鰭式場效電晶體(FinFET)描述各種實施例，該半導體裝置可包括例如平面場效電晶體(FET)或奈米線FET，但亦考量更多裝置架構。
結合替代金屬閘極製程，根據各種實施例，形成一裝置之方法包括：在半導體鰭片之通道區域上方於間隔層之間形成一閘極堆疊，將該閘極堆疊及該間隔層凹入，及在該凹入之閘極堆疊及該等間隔層兩者上方形成一閘極導體層。調適該閘極導體層以抑制在一後續蝕刻步驟期間對該等間隔層之蝕刻損害，該蝕刻步驟用來在該鰭片之源/汲極區域上方形成接觸開口。
將一犧牲層沉積在該等接觸開口內，其在該閘極導體層之凹入蝕刻期間保護該鰭片之源/汲極區域。接著在該凹入閘極導體層上方形成一自對準包覆層。在特定實施例中，在蝕刻步驟後，形成該自對準包覆層以形成該等接觸開口。相對該自對準包覆層選擇性地移除該犧牲層，且在該鰭片之源/汲極區域上方形成一源/汲極金屬化層及源/汲極接觸。
根據某些實施例，形成一半導體裝置之方法包括：在間隔層之間及在半導體層之源/汲極區域上方形成源/汲極接面，在該源/汲極接面上方形成一層間介電質，及在該半導體層之通道區域上方在該等源/汲極區域 之間形成一閘極堆疊。藉由實例，該半導體層可包一半導體鰭片。
將該閘極堆疊凹入至一第一高度，且將該等間隔層凹入大於該第一高度之一第二高度。其後，在該凹入閘極堆疊上方及該等凹入間隔層上方形成一閘極導體層。該方法進一步包括相對該閘極導體層選擇性地蝕刻該層間介電質以在該等源/汲極接面上方形成接觸開口。
根據其它實施例，一半導體裝置包括具有一閘極介電層之一閘極堆疊及佈置在一半導體層之一通道區域上方在源/汲極區域之間的一功函數金屬層，及佈置在該閘極堆疊上方之一閘極導體層，其中該閘極導體層之一頂部表面係非平面的。
另一實例半導體裝置包括：具有一閘極介電層之一閘極堆疊及佈置在間隔層之間的一功函數金屬層，及佈置在該閘極堆疊上方之一閘極導體層，其中該閘極導體層之一頂部表面係非平面的。
100‧‧‧半導體基板
120‧‧‧鰭片
122‧‧‧通道區域
124‧‧‧源/汲極區域
200‧‧‧間隔層
300‧‧‧源/汲極接面
320‧‧‧層間介電質(及順應性襯裡)/ILD層
330‧‧‧接觸開口
340‧‧‧犧牲層
350‧‧‧導電接觸
410‧‧‧閘極介電質
420‧‧‧功函數金屬層
450‧‧‧遮罩層
460‧‧‧閘極開口
470‧‧‧閘極導體層
475‧‧‧橫向延伸部份
477‧‧‧向上凸出部份
490‧‧‧閘極罩
500‧‧‧遮罩層
510‧‧‧開口
600‧‧‧層間介電質
620‧‧‧金屬互連
結合以下圖式閱讀可最佳了解本申請案之特定實施例之以下實施方式，其中類似結構指示類似參照數字，且其中：圖1為在相鄰間隔層之間及在一半導體鰭片之通道區域上方連續沉積閘極介電質及功函數金屬層之後之一FinFET裝置之截面圖；圖2顯示在該閘極介電質及功函數金屬層上方在該等通道區域內形成一凹入遮罩層：圖3描述該閘極介電質及功函數金屬層之一凹入蝕刻；圖4顯示該等間隔層之一凹入蝕刻； 圖5描述在該凹入功函數金屬及閘極介電層上方，及在該凹入間隔層之一頂部表面上方沉積一閘極導體層；圖6顯示形成一遮罩層及蝕刻一層間介電質以在該鰭片之源/汲極區域上方產生接觸開口；圖7顯示在該等接觸開口內沉積一犧牲層；圖8描述該閘極導體層之一凹入蝕刻；圖9顯示在該凹入閘極導體層上方形成一自對準閘極罩；圖10描述自該等接觸開口內移除該犧牲層；圖11顯示在該等接觸開口內及在該鰭片之源/汲極區域上方形成一源/汲極金屬化層；及圖12顯示形成一接觸位準介電層及延伸通過該接觸位準介電層之源/汲極接觸。
現將更詳細參照本申請案之標的之各種實施例，其某些實施例在隨附圖式中說明。在整個圖式中相同參照數字將用來參照相同或類似之部件。
本文揭示一種製造一鰭片場效電晶體之方法。該鰭式場效電晶體(FinFET)為一吸引人之電晶體架構，因為其製造與其它雙閘極裝置相比相對簡單。在各種實施例中，該FinFET之通道為半導體材料(通常為矽)之薄、凸起條帶或鰭片。一電晶體閘極包封該鰭片，使得該通道在該鰭片之垂直部份之雙側上閘控，其提供優於一平面、單一閘極金屬氧化物半導體 場效電晶體(MOSFET)之閘極控制。
FinFET之製造通常充分利用一自對準製程以使用選擇性蝕刻技術在一基板之表面上製造極薄之鰭片，例如，20nm寬或更小。然後沉積一閘極結構以接觸各鰭片之多個表面以在該鰭片之源/汲極區域間形成一多重閘極架構。接著對該閘極及該等源/汲極區域之每一者形成各自之導電接觸。本文參照圖1-12描述一種形成一FinFET之方法，其在該等相鄰閘極及源/汲極接觸間具有強固之隔離。
參照圖1，在一半導體基板100上方形成一半導體鰭片120。該半導體基板100可為一塊體基板或一複合基板，例如：一絕緣體上覆半導體(SOI)基板，且可包括如熟習本技術者已知之任何合適之半導體材料。該半導體基板之部份可為非晶質、多晶體、或單晶。儘管在所述載面中顯示單一鰭片120，應了解可在該基板100上方形成鰭片陣列。
在各種實施例中，各鰭片120包括一半導體材料(例如：矽)，且可藉由圖案化然後蝕刻該半導體基板100形成，例如，該半導體基板之一頂部部份。在數個實施例中，該等鰭片120係蝕刻自該半導體基板100，且因此與其相鄰。例如，鰭片120可使用如熟習本技術者已知之側壁影像轉移(SIT)製程來形成。
各鰭片120可包括單晶半導體材料，其沿一縱向方向延伸。如本文所用，一「縱向方向(lengthwise direction)」係一物體沿其延伸最多的一水平方向。一「橫向方向(widthwise direction)」係與該縱向方向垂直之一水平方向。
如本文所用，「水平」係指沿著一基板之主要表面之大致方 向，及「垂直」為通常與其正交之方向。此外，「垂直」及「水平」係在三維空間中獨立於基板定向一般而言相對於彼此垂直之方向。
在某些實施例中，該鰭片120可具有5nm至20nm之一寬度，40nm至150nm之一高度，但亦考量其它尺寸。在包括複數鰭片之結構中(即，一鰭片陣列)，各鰭片可與其最近相鄰者以一週期性或以20nm至100nm之間距(d)間隔開，例如：20、30、40、50、60、70、80、90或100nm，包括在前述值任一者之間之範圍。如本文所用，該術語「間距」係指該鰭片寬度及相鄰鰭片間之間隔的總和。
此等複數鰭片通常彼此定向平行且垂直於一電路之庫邏輯流(the library logic flow of circuit)。在形成鰭片後，可使用一鰭片切割或鰭片移除製程來去除不想要之鰭片或其不想要之部份以用於特定電路或待製造之裝置上。因此，該鰭片-對-鰭片週期在鰭片之陣列上可為恆定或可變的。
鰭片120包括交替之通道區域122及源/汲極區域124，如熟習本技術者所了解。再參照圖1，圖1說明在移除一犧牲閘極後之一替代金屬閘極(RMG)結構，其顯示在該犧牲閘極之側壁上方形成之間隔層200，佈置在該鰭片120之源/汲極區域124上方之源/汲極接面300，及佈置在該源/汲極接面300上方在相鄰間隔層200之間之一層間介電質及順應性襯裡(總稱作320)。在移除該犧牲閘極之後，依序沉積閘極介電質及功函數金屬層410、420，即，在相鄰間隔層200之間在該鰭片120之通道區域122上方。
間隔層200可藉由覆蓋式沉積一間隔材料來形成(例如，使用原子層沉積)，接著進行一定向蝕刻，例如：反應性離子蝕刻(RIE)，以自水平表面移除該間隔材料。在某些實施例中，該間隔層200厚度為4至20 nm，例如：4、10、15或20nm，包括在任一上述值之間之範圍。
源/汲極接面300可在形成該犧牲閘極及間隔層200之後，視情況使用該等犧牲閘極及間隔層200作為一對準遮罩，藉由離子植入或選擇性磊晶形成。
根據各種實施例，源/汲極接面300係藉由選擇性磊晶形成於自對準模槽內，其經界定於該等犧牲閘極之間。源/汲極接面300可包括矽(例如，Si)或一含矽材料，例如：矽鍺(SiGe)。例如，SiGe源/汲極接面可併入一p-MOS裝置以提供對該通道之壓縮應力，其可改善載子移動率。
如本文所用，該等術語「磊晶」、「磊晶的」及/或「磊晶生長及/或沉積」係指在半導體材料之沉積表面上之半導體材料層之生長，在其中生長之該半導體材料層假設具有與該沉積表面之半導體材料相同之晶癖。例如，在一磊晶沉積程序中，控制由來源氣體提供之化學反應物且設定該等系統參數使得沉積原子落在該沉積表面上，並通過表面擴散保留充份的移動性以根據該沉積表面之原子之結晶定向將其等本身定向。因此，一磊晶半導體材料具有與該沉積表面(其在該沉積表面上形成)相同之結晶特性。例如，在一(100)晶體表面上沉積之一磊晶半導體材料可採用(100)定向。實例磊晶生長製程包括低能量電漿沉積、液相磊晶、分子束磊晶、及常壓化學氣相沉積。
可摻雜該鰭片120之該等源/汲極接面300及對應之(即，下層)源/汲極區域124，其可原位進行，即，在磊晶生長期間，或在磊晶生長之後，例如，使用離子植入。摻雜改變熱平衡時本質半導體之電子與電洞載體濃度。一摻雜層或區域可為p型或n型。
如本文所用，「p型」係指將雜質添加至一本質半導體中，其造成價電子不足。在一含矽鰭片中，實例p型摻雜物(即雜質)包括(但不限於)：硼、鋁、鎵、及銦。如本文所用，「n型」係指添加對固有半導體貢獻自由電子之雜質。在一含矽鰭片中，實例n型摻雜物(即雜質)包括(但不限於)：銻、砷、及磷。
在形成該源/汲極接面300之後，在接觸位置內在該源/汲極接面300上方，在相鄰間隔層200之間依次形成一順應性襯裡及一層間介電質320(未分開顯示)。該順應性襯裡佈置在該等間隔層200上方以及在該等源/汲極接面300之一頂部表面上方。該順應性襯裡經調適以作用為一接觸蝕刻停止層(CESL)。
順應性襯裡可藉由一合適接觸蝕刻停止材料之覆蓋式沉積(例如，使用原子層沉積)形成。在某些實施例中，該順應性襯裡厚度為2至10nm，例如：2、4、6、8或10nm，包括在任一上述值之間之範圍。
合適之間隔層200及順應性襯裡材料包括氧化物，氮化物及氮氧化物，例如：二氧化矽、氮化矽、氮氧化矽，及低介電常數(低k)材料，例如：非晶質碳、SiOC、SiOCN及SiBCN，以及一低k介電材料。如本文所用，一低k材料具有低於二氧化矽之介電常數。
實例低k材料包括(但不限於)：非晶質碳、氟摻雜氧化物、或碳摻雜氧化物。市售可得低k介電產品及材料包括道康寧公司(Dow Corning)的SiLKTM及多孔SiLKTM，應用材料公司(Applied Materials)的Black DiamondTM，德州儀器公司(Texas Instrument)的CoralTM及台灣積體電路(TSMC)的Black DiamondTM及CoralTM。
在各種實施例中，該間隔層200及該順應性襯裡係由可對另一者選擇性蝕刻之材料形成。在特定實施例中，該間隔層200包括SiOCN且該順應性襯裡(即，接觸蝕刻停止層)包括氮化矽。
層間介電質320佈置在相鄰犧牲閘極之間，即，直接在該順應性襯裡上方。該層間介電質320可包括任何介電材料，包括：例如，氧化物，氮化物或氮氧化物。在一實施例中，該等層間介電質320包括二氧化矽。在各種實施例中，該層間介電質可自平面化，或該層間介電質320之頂部表面可藉由化學機械抛光(CMP)使用該犧牲閘極作為一拋光停止來平面化。
「平面化」為一材料移除製程，其使用至少機械力(例如：摩擦介質)來產生一實質上二維之表面。一平面化製程可包括化學機械抛光(CMP)或研磨。化學機械抛光(CMP)為一材料移除製程，其使用化學反應及機械力兩者來移除材料及將一表面平面化。
再參照圖1，一替代金屬閘極(RMG)模組包括移除該犧牲閘極及其後在鰭片120之該通道區域122之該等頂部及側壁表面上方形成一閘極堆疊。該閘極堆疊包括直接在該鰭片120之暴露頂部及側壁表面上方形成之一順應性閘極介電質410，及在該閘極介電質410上方形成之一功函數金屬層420。
該閘極介電質410可包括二氧化矽、氮化矽、氮氧化矽，一高k介電質，或其它合適材料。如本文所用，一高k材料具有高於二氧化矽之介電常數。一高k介電質可包括二元或三元化合物，例如：氧化鉿(HfO2)。其它實例高k介電質包括(但不限於)：ZrO2、La2O3、Al2O3、TiO2、 SrTiO3、BaTiO3、LaAlO3、Y2O3、HfOxNy、HfSiOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaAlOxNy、Y2OxNy、SiOxNy、SiNx、其矽酸鹽，及其合金。各x值可獨立地自0.5至3變化，且各y值可獨立地自0至2變化。該閘極介電質厚度範圍可在1nm至10nm，例如：1、2、4、6、8或10nm，包括在任何前述值之間之範圍。
該功函數金屬層420可包括一導電材料，例如：碳化鈦(TiC)、鋁化鈦(TiAl)、鋁化鉭(TaAl3)、鋁化鉿(HfAl或HfAl3)或一金屬矽化物。該功函數金屬層厚度範圍可在2nm至12nm，例如：2、4、6、8、10或12nm，包括在任一前述值之間之範圍。
參照圖2，一遮罩層450在該閘極介電質及功函數金屬層上方形成，即，直接在該功函數金屬層420上方在該鰭片之通道區域上方。然後將該遮罩層450凹入。遮罩層450可包括一有機平面化層(OPL)，如熟習本技術者已知。如參照圖3所見，遮罩層450經調適以限制其後該閘極介電質及功函數金屬層410、420之凹入蝕刻的程度以在該鰭片120之通道區域上方形成閘極開口460。
根據各種實施例，遮罩層450可包括一光敏有機聚合物，其在暴露於電磁幅射時經化學改變，因此經配置以使用一顯影劑移除。例如，一光敏有機聚合物可包括：聚丙烯酸酯樹脂、環氧樹脂、酚醛樹脂、聚醯胺樹脂、聚醯亞胺樹脂、不飽和聚酯樹脂、聚苯醚樹脂、聚苯硫醚樹脂或苯並環丁烯。
參照圖4，該間隔層200之凹入蝕刻在該閘極介電質及功函數金屬層410、420之凹入蝕刻後。該等間隔層200之下拉蝕刻暴露該層間 介電質320之側壁。在該等間隔層200之凹入蝕刻及該閘極介電質及功函數金屬層410、420之凹入蝕刻後，該等間隔層200之一頂部表面在該閘極介電質及功函數金屬層410、420之一頂部表面之上。本文所述之凹入蝕刻製程通常包括一異向性蝕刻。在某些實施例中，可使用一乾式蝕刻製程，例如：反應性離子蝕刻。在其它實施例中，可使用一濕式化學蝕刻劑。在其它實施例中，可使用乾式蝕刻及濕式蝕刻之組合。
參照圖5，在該凹入功函數金屬及閘極介電層410、420上方，以及在該等凹入間隔層200之一頂部表面上方形成一閘極導體層470。即，該閘極導體層470之部份475橫向延伸在該等凹入間隔層200上方。可使用一拋光步驟來平面化該結構。
在各種實施例中，該閘極導體470可包括一導電材料，例如：聚合矽、矽-鍺，一導電金屬(例如：Al、W、Cu、Ti、Ta、W、Co、Pt、Ag、Au、Ru、Ir、Rh及Re)，以及導電金屬合金，例如，Al-Cu。在某些實施例中，該閘極導體層470包括直接在該功函數金屬層420上方之氮化鈦(TiN)層，及在該氮化鈦層上方之鎢或鈷填充層。該閘極導體層470(包括橫向延伸部份475)經配置以保護該等間隔層200在其後蝕刻步驟期間不受侵蝕。
參照圖6，一遮罩層500在圖5之結構上方形成。使用習知光刻微影，例如，開口510在該遮罩層500及該ILD層320之暴露部份中形成，且其後移除在開口510內之接觸蝕刻停止層以在源/汲極接面300上方形成接觸開口330。根據各種實施例，閘極導體層470之橫向延伸部份475抑制或防止在蝕刻該ILD層320及接觸蝕刻停止層期間之間隔層200 之侵蝕。
圖7顯示在接觸開口330內直接在源/汲極接面300上方沉積一犧牲層340。在某些實施例中，犧牲層340完全填充該等接觸開口330且經調適在其後該閘極導體層470之凹入蝕刻期間保護該源/汲極接面300。犧牲層340可包括一有機平面化層(OPL)，例如，如結合遮罩層450所述。
如在所述實施例中所示，凹入犧牲層340使得其頂部表面佈置在該閘極導體層470之一頂部表面之下。在此處理階段中，也移除該遮罩層500(即，在該犧牲層340之凹入蝕刻期間)，且該閘極導體層470之橫向延伸部份475延伸在間隔層200之一頂部表面上方。
參照圖8及9，該閘極導體層470相對間隔層200及犧牲層340選擇性地蝕刻以形成開口，其經回填以形成一閘極罩490。例如，可使用一反應性離子蝕刻步驟以將該閘極導體層470凹入。在某些實施例中，藉由該凹入蝕刻移除25%至75%之原始閘極導體層高度。
特別參照圖8，可將該閘極導體層470之較高區域倒角以包括一向上凸出部份477，使得該蝕刻閘極導體層470之一頂部表面實質上為非平面。即，該蝕刻閘極導體層470之向上凸出部份477對應於該閘極導體層470之部份，其在形成犧牲層340之前在遮罩層500底下。在所述實施例中，向上凸出部份477從鰭片120之末端橫向地位移。
談到圖9，該閘極罩490可包括氮化物材料，例如：氮化矽或氮氧化矽(SiON)。在沉積該閘極罩490之後，可再使用另一平面化製程以移除該覆蓋部份，且如在圖9中所示，完成該替代金屬閘極模組及形成 一平面化結構。
在某些實施例中，在該平面化結構中，該閘極罩490之一頂部表面及該犧牲層340及間隔層200之各別頂部表面係相互共平面的。如所應了解，該閘極罩490覆蓋該閘極導體層470之整個頂部表面，但該閘極罩490可具有不同厚度。
參照圖10，可自源/汲極接面300上方移除該犧牲層340以形成自對準接觸開口330。可使用對該相鄰暴露層具選擇性之一蝕刻劑移除該犧牲層340。例如，可藉由灰化、反應性離子蝕刻或等向性蝕刻(例如：一濕式蝕刻或一等向性電漿蝕刻)移除該犧牲層340。
在金屬化該源/汲極區域之前，可使用濕式蝕刻自該等源/汲極接面300上方移除原生氧化物。用於去除氧化物之一實例濕式蝕刻包括：氫氟酸或包括稀釋氫氟酸(d-HF)之溶液。
如在圖11中所示，藉由沉積(例如)一導電襯裡及一阻障層(未分開顯示)然後以一接觸層(例如：鎢或鈷)填充該等接觸開口而在該等接觸開口330內及在該源/汲極接面300之暴露表面上方形成導電接觸350。該導電襯裡通常為鈦且該阻障層可為氮化鈦(TiN)。
導電接觸350可包括與該源/汲極接面300形成一歐姆接觸之一金屬。可通過該導電襯裡(例如，鈦)及該等源/汲極接面300之間之反應原位形成矽化物層(例如，矽化鈦)以形成一溝槽矽化物接觸。
在形成該等導電接觸350之後，可使用一平面化製程以形成其中導電接觸350之頂部表面與該等相鄰閘極罩490之頂部表面共平面的結構。
可使用額外加工以形成一功能裝置，包括中段(middle-of-the line)及後段(back-of-the line)金屬化及內連線模組以形成合適之電性連接。如在圖12中所示，例如，可在該等閘極罩490及該等導電接觸350上方形成一層間介電質600。可使用習知光刻微影、蝕刻及沉積製程以形成在該層間介電質600中之開口內且與導電接觸350電接觸的金屬互連620。
如本文所揭示，一種形成FinFET裝置之方法包括：在一半導體鰭片之通道區域上方於間隔層之間形成一閘極堆疊，將該閘極堆疊及該等間隔層凹入，及在該凹入閘極堆疊及該等間隔層兩者上方形成一閘極導體層。調適該閘極導體層以抑制在一後續蝕刻步驟期間對該等間隔層之蝕刻損害，該蝕刻步驟用來在該鰭片之源/汲極區域上方形成接觸開口。所得結構展現在閘極及源/汲極接觸間改善之電隔離。
除非上下文另有說明，否則可藉由任何合適之技術形成或沉積的材料及材料層包括(但不限於)：化學氣相沉積(CVD)，物理氣相沉積(PVD)，原子層沉積(ALD)，旋轉塗佈，等等。或者，可例如藉由熱氧化原位形成材料層。
如本文所用，單數形式「一(a,an)」及「該(the)」包括複數參考物，除非本文明確地另外指示。因此，例如，對「鰭片」之參照包括具有二或多個此種「鰭片」之實例，除非上下文明確地另有說明。
本文絕對未意欲將本文提出之任何方法解釋為需要以特定順序進行其步驟。因此，其中一方法主張未實際敘述其步驟所依循的順序，或者未在申請專利範圍或描述中明確說明該等步驟限於特定之順序，其絕未意欲推斷任何特定之順序。在任一申請專利範圍中之任何所述之單一或 多個特徵或態樣可與在任何其它申請專利範圍中之任何其它所述特徵或態樣組合或以其替換。
應了解當一元件(例如：一層、區域或基板)係指出經形成於、沉積於、或佈置於另一元件「上」或「上方」時，其可係直接在該其它元件上或亦可出現插入之元件。相對地，當一元件係指「直接在另一元件上」或「直接在另一元件上方」時，不存在插入之元件。
儘管可使用過渡片語「包括」來揭示特定實施例的各種特徵、元件或步驟，但是應理解暗指包括可使用過渡片語「由...組成」或「基本上由...組成」描述之實施例的替代實施例。因此，例如，暗指包含半導體材料的鰭片的替代實施例包括鰭片基本上由半導體材料組成的實施例及鰭片由半導體材料組成的實施例。
熟習本技術者明顯得知可在不背離本發明之精神及範疇下對本發明進行各種修改及變化。由於熟習本技術者可得知涵蓋本發明之精神及實質之所揭示實施例之修改、組合、子組合及變化，本發明應視為包括在隨附申請專利範圍及其等效物之範疇內的所有事項。
100‧‧‧半導體基板
120‧‧‧鰭片
200‧‧‧間隔層
300‧‧‧源/汲極接面
320‧‧‧層間介電質(及順應性襯裡)/ILD層
350‧‧‧導電接觸
410‧‧‧閘極介電質
420‧‧‧功函數金屬層
470‧‧‧閘極導體層
477‧‧‧向上凸出部份
490‧‧‧閘極罩
600‧‧‧層間介電質
620‧‧‧金屬互連

Claims (18)

  1. 一種形成一半導體裝置之方法，包含：在間隔層間及在一半導體層之源/汲極區域上方形成源/汲極接面；在該源/汲極接面上方形成一層間介電質；在該半導體層之一通道區域上方在該等源/汲極區域間形成一閘極堆疊；凹入該閘極堆疊至一第一高度；凹入該等間隔層至大於該第一高度之一第二高度；在該凹入閘極堆疊上方及該等凹入間隔層上方形成一閘極導體層；及相對該閘極導體層選擇性地蝕刻該層間介電質以在該等源/汲極接面上方形成接觸開口。
  2. 如申請專利範圍第1項所述之方法，進一步包含：在該等接觸開口內形成一犧牲層；凹入該閘極導體層至低於該等側壁間隔件之高度的一高度；及在該閘極導體層上方形成一閘極罩。
  3. 如申請專利範圍第2項所述之方法，進一步包含在凹入該閘極導體層之前蝕刻該犧牲層以暴露該閘極導體層之一頂部表面。
  4. 如申請專利範圍第2項所述之方法，進一步包含： 移除該犧牲層以形成接觸開口；及在該等接觸開口內及在該等源/汲極接面上方形成一導電接觸。
  5. 如申請專利範圍第4項所述之方法，其中該犧牲層係藉由灰化移除。
  6. 如申請專利範圍第1項所述之方法，其中該閘極導體層直接在該等凹入間隔層之一頂部表面上方形成。
  7. 如申請專利範圍第1項所述之方法，其中該閘極導體層在蝕刻該層間介電質期間佈置在該等凹入間隔層之一頂部表面上方。
  8. 如申請專利範圍第1項所述之方法，其中凹入該閘極堆疊包含在該閘極堆疊之第一部份上方形成一遮罩層及移除佈置在該遮罩層上之該閘極堆疊之一第二部份。
  9. 一種半導體裝置，包含：一閘極堆疊，包含佈置在一半導體層之一通道區域上方之一閘極介電層及一功函數金屬層；及佈置在該閘極堆疊上方之一閘極導體層，其中該閘極導體層之一頂部表面為非平面的。
  10. 如申請專利範圍第9項所述之半導體裝置，其中該閘極導體層之頂部表面包含一向上凸出之部份。
  11. 如申請專利範圍第10項所述之半導體裝置，其中該半導體裝置為一FinFET，該半導體層包含一半導體鰭片且該向上凸出部份係自該半導體鰭片之末端橫向地位移。
  12. 如申請專利範圍第9項所述之半導體裝置，其進一步包含直接佈置在該閘極導體層之頂部表面上方之一閘極罩。
  13. 如申請專利範圍第12項所述之半導體裝置，其中該閘極罩具有可變之厚度。
  14. 如申請專利範圍第12項所述之半導體裝置，其中該閘極罩包含氮化矽。
  15. 如申請專利範圍第9項所述之半導體裝置，其中該閘極導體層包含直接佈置在該功函數金屬層上方之一層氮化鈦。
  16. 一種半導體裝置，包含：一閘極堆疊，其包含佈置在間隔層之間之一閘極介電層及一功函數金屬層；及佈置在該閘極堆疊上方之一閘極導體層，其中該閘極導體層之一頂 部表面為非平面的。
  17. 如申請專利範圍第16項所述之半導體裝置，進一步包含直接佈置在該閘極導體層之頂部表面上方之一閘極罩。
  18. 如申請專利範圍第17項所述之半導體裝置，其中該閘極罩之一頂部表面係與該等間隔層之一頂部表面共平面。
TW108115584A 2018-06-07 2019-05-06 具改進的閘極－源／汲極金屬化隔離的半導體裝置 TW202002022A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/002,207 2018-06-07
US16/002,207 US20190378722A1 (en) 2018-06-07 2018-06-07 Semiconductor device with improved gate-source/drain metallization isolation

Publications (1)

Publication Number Publication Date
TW202002022A true TW202002022A (zh) 2020-01-01

Family

ID=68651978

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108115584A TW202002022A (zh) 2018-06-07 2019-05-06 具改進的閘極－源／汲極金屬化隔離的半導體裝置

Country Status (3)

Country Link
US (1) US20190378722A1 (zh)
DE (1) DE102019206553A1 (zh)
TW (1) TW202002022A (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113161352A (zh) * 2020-01-23 2021-07-23 南亚科技股份有限公司 半导体元件及其制备方法
US11404323B2 (en) 2020-04-29 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Formation of hybrid isolation regions through recess and re-deposition
TWI778507B (zh) * 2020-04-29 2022-09-21 台灣積體電路製造股份有限公司 半導體元件及其形成方法
TWI832320B (zh) * 2022-02-14 2024-02-11 台灣積體電路製造股份有限公司 形成具有接觸特徵之半導體裝置的方法
US12100627B2 (en) 2021-01-19 2024-09-24 Taiwan Semiconductor Manufacturing Company Ltd. Method and structure for metal gates

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117727761A (zh) 2019-08-20 2024-03-19 联华电子股份有限公司 半导体装置
DE102021113053B4 (de) 2021-03-10 2024-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-feldeffekttransistorvorrichtung und verfahren
US11942372B2 (en) * 2021-08-27 2024-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric protection layer in middle-of-line interconnect structure manufacturing method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8877580B1 (en) * 2013-05-17 2014-11-04 Globalfoundries Inc. Reduction of oxide recesses for gate height control
CN106663694B (zh) * 2014-08-19 2021-05-25 英特尔公司 具有横向渐变功函数的晶体管栅极金属
CN108878358B (zh) * 2017-05-09 2021-05-04 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113161352A (zh) * 2020-01-23 2021-07-23 南亚科技股份有限公司 半导体元件及其制备方法
US11302814B2 (en) 2020-01-23 2022-04-12 Nanya Technology Corp. Semiconductor device with porous dielectric structure and method for fabricating the same
US11404323B2 (en) 2020-04-29 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Formation of hybrid isolation regions through recess and re-deposition
TWI778507B (zh) * 2020-04-29 2022-09-21 台灣積體電路製造股份有限公司 半導體元件及其形成方法
US11837505B2 (en) 2020-04-29 2023-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Formation of hybrid isolation regions through recess and re-deposition
US12112988B2 (en) 2020-04-29 2024-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid isolation regions having upper and lower portions with seams
US12100627B2 (en) 2021-01-19 2024-09-24 Taiwan Semiconductor Manufacturing Company Ltd. Method and structure for metal gates
TWI832320B (zh) * 2022-02-14 2024-02-11 台灣積體電路製造股份有限公司 形成具有接觸特徵之半導體裝置的方法

Also Published As

Publication number Publication date
DE102019206553A1 (de) 2019-12-12
US20190378722A1 (en) 2019-12-12

Similar Documents

Publication Publication Date Title
US10541331B2 (en) Fabrication of a vertical fin field effect transistor with an asymmetric gate structure
US10734233B2 (en) FinFET with high-k spacer and self-aligned contact capping layer
US9905663B2 (en) Fabrication of a vertical fin field effect transistor with a reduced contact resistance
US10374040B1 (en) Method to form low resistance contact
TWI737296B (zh) 半導體裝置及其製造方法
TW202002022A (zh) 具改進的閘極－源／汲極金屬化隔離的半導體裝置
US20190067115A1 (en) Gate cut method for replacement metal gate
US10164104B2 (en) Method to form air-gap spacers and air-gap spacer-containing structures
US10069011B2 (en) Method for fabricating a FinFET metallization architecture using a self-aligned contact etch
US20180108770A1 (en) Self-aligned gate cut with polysilicon liner oxidation
US10062787B2 (en) FinFET
US10014409B1 (en) Method and structure to provide integrated long channel vertical FinFET device
TWI710058B (zh) 積體單擴散阻斷
US10879180B2 (en) FinFET with etch-selective spacer and self-aligned contact capping layer
CN110326112B (zh) 用改进的垂直鳍片几何形状制作垂直场效应晶体管器件
US10777468B1 (en) Stacked vertical field-effect transistors with sacrificial layer patterning
US20230012216A1 (en) Gate all around transistor with dual inner spacers
US11081398B2 (en) Method and structure to provide integrated long channel vertical FinFet device
US10242867B2 (en) Gate pickup method using metal selectivity
US9905473B1 (en) Self-aligned contact etch for fabricating a FinFET
US11476342B1 (en) Semiconductor device with improved source and drain contact area and methods of fabrication thereof
US20230091229A1 (en) Bottom junction and contact area structures for vertical transport field-effect transistors
TW202213642A (zh) 半導體裝置及其製造方法
US20190287861A1 (en) Substrate with a fin region comprising a stepped height structure
US20230343583A1 (en) Methods of forming semiconductor device structure